1 /*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22 #include "priv.h"
23
24 #include <core/gpuobj.h>
25 #include <core/memory.h>
26 #include <subdev/timer.h>
27
28 static void
nvkm_falcon_v1_load_imem(struct nvkm_falcon * falcon,void * data,u32 start,u32 size,u16 tag,u8 port,bool secure)29 nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,
30 u32 size, u16 tag, u8 port, bool secure)
31 {
32 u8 rem = size % 4;
33 u32 reg;
34 int i;
35
36 size -= rem;
37
38 reg = start | BIT(24) | (secure ? BIT(28) : 0);
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg);
40 for (i = 0; i < size / 4; i++) {
41 /* write new tag every 256B */
42 if ((i & 0x3f) == 0)
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]);
45 }
46
47 /*
48 * If size is not a multiple of 4, mask the last work to ensure garbage
49 * does not get written
50 */
51 if (rem) {
52 u32 extra = ((u32 *)data)[i];
53
54 /* write new tag every 256B */
55 if ((i & 0x3f) == 0)
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16),
58 extra & (BIT(rem * 8) - 1));
59 ++i;
60 }
61
62 /* code must be padded to 0x40 words */
63 for (; i & 0x3f; i++)
64 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0);
65 }
66
67 static void
nvkm_falcon_v1_load_emem(struct nvkm_falcon * falcon,void * data,u32 start,u32 size,u8 port)68 nvkm_falcon_v1_load_emem(struct nvkm_falcon *falcon, void *data, u32 start,
69 u32 size, u8 port)
70 {
71 u8 rem = size % 4;
72 int i;
73
74 size -= rem;
75
76 nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), start | (0x1 << 24));
77 for (i = 0; i < size / 4; i++)
78 nvkm_falcon_wr32(falcon, 0xac4 + (port * 8), ((u32 *)data)[i]);
79
80 /*
81 * If size is not a multiple of 4, mask the last word to ensure garbage
82 * does not get written
83 */
84 if (rem) {
85 u32 extra = ((u32 *)data)[i];
86
87 nvkm_falcon_wr32(falcon, 0xac4 + (port * 8),
88 extra & (BIT(rem * 8) - 1));
89 }
90 }
91
92 static const u32 EMEM_START_ADDR = 0x1000000;
93
94 static void
nvkm_falcon_v1_load_dmem(struct nvkm_falcon * falcon,void * data,u32 start,u32 size,u8 port)95 nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,
96 u32 size, u8 port)
97 {
98 u8 rem = size % 4;
99 int i;
100
101 if (start >= EMEM_START_ADDR && falcon->has_emem)
102 return nvkm_falcon_v1_load_emem(falcon, data,
103 start - EMEM_START_ADDR, size,
104 port);
105
106 size -= rem;
107
108 nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 24));
109 for (i = 0; i < size / 4; i++)
110 nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), ((u32 *)data)[i]);
111
112 /*
113 * If size is not a multiple of 4, mask the last word to ensure garbage
114 * does not get written
115 */
116 if (rem) {
117 u32 extra = ((u32 *)data)[i];
118
119 nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8),
120 extra & (BIT(rem * 8) - 1));
121 }
122 }
123
124 static void
nvkm_falcon_v1_read_emem(struct nvkm_falcon * falcon,u32 start,u32 size,u8 port,void * data)125 nvkm_falcon_v1_read_emem(struct nvkm_falcon *falcon, u32 start, u32 size,
126 u8 port, void *data)
127 {
128 u8 rem = size % 4;
129 int i;
130
131 size -= rem;
132
133 nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), start | (0x1 << 25));
134 for (i = 0; i < size / 4; i++)
135 ((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));
136
137 /*
138 * If size is not a multiple of 4, mask the last word to ensure garbage
139 * does not get read
140 */
141 if (rem) {
142 u32 extra = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));
143
144 for (i = size; i < size + rem; i++) {
145 ((u8 *)data)[i] = (u8)(extra & 0xff);
146 extra >>= 8;
147 }
148 }
149 }
150
151 static void
nvkm_falcon_v1_read_dmem(struct nvkm_falcon * falcon,u32 start,u32 size,u8 port,void * data)152 nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size,
153 u8 port, void *data)
154 {
155 u8 rem = size % 4;
156 int i;
157
158 if (start >= EMEM_START_ADDR && falcon->has_emem)
159 return nvkm_falcon_v1_read_emem(falcon, start - EMEM_START_ADDR,
160 size, port, data);
161
162 size -= rem;
163
164 nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 25));
165 for (i = 0; i < size / 4; i++)
166 ((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));
167
168 /*
169 * If size is not a multiple of 4, mask the last word to ensure garbage
170 * does not get read
171 */
172 if (rem) {
173 u32 extra = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));
174
175 for (i = size; i < size + rem; i++) {
176 ((u8 *)data)[i] = (u8)(extra & 0xff);
177 extra >>= 8;
178 }
179 }
180 }
181
182 static void
nvkm_falcon_v1_bind_context(struct nvkm_falcon * falcon,struct nvkm_memory * ctx)183 nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx)
184 {
185 u32 inst_loc;
186 u32 fbif;
187
188 /* disable instance block binding */
189 if (ctx == NULL) {
190 nvkm_falcon_wr32(falcon, 0x10c, 0x0);
191 return;
192 }
193
194 switch (falcon->owner->index) {
195 case NVKM_ENGINE_NVENC0:
196 case NVKM_ENGINE_NVENC1:
197 case NVKM_ENGINE_NVENC2:
198 fbif = 0x800;
199 break;
200 case NVKM_SUBDEV_PMU:
201 fbif = 0xe00;
202 break;
203 default:
204 fbif = 0x600;
205 break;
206 }
207
208 nvkm_falcon_wr32(falcon, 0x10c, 0x1);
209
210 /* setup apertures - virtual */
211 nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_UCODE, 0x4);
212 nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_VIRT, 0x0);
213 /* setup apertures - physical */
214 nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_VID, 0x4);
215 nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_SYS_COH, 0x5);
216 nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6);
217
218 /* Set context */
219 switch (nvkm_memory_target(ctx)) {
220 case NVKM_MEM_TARGET_VRAM: inst_loc = 0; break;
221 case NVKM_MEM_TARGET_HOST: inst_loc = 2; break;
222 case NVKM_MEM_TARGET_NCOH: inst_loc = 3; break;
223 default:
224 WARN_ON(1);
225 return;
226 }
227
228 /* Enable context */
229 nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1);
230 nvkm_falcon_wr32(falcon, 0x054,
231 ((nvkm_memory_addr(ctx) >> 12) & 0xfffffff) |
232 (inst_loc << 28) | (1 << 30));
233
234 nvkm_falcon_mask(falcon, 0x090, 0x10000, 0x10000);
235 nvkm_falcon_mask(falcon, 0x0a4, 0x8, 0x8);
236 }
237
238 static void
nvkm_falcon_v1_set_start_addr(struct nvkm_falcon * falcon,u32 start_addr)239 nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr)
240 {
241 nvkm_falcon_wr32(falcon, 0x104, start_addr);
242 }
243
244 static void
nvkm_falcon_v1_start(struct nvkm_falcon * falcon)245 nvkm_falcon_v1_start(struct nvkm_falcon *falcon)
246 {
247 u32 reg = nvkm_falcon_rd32(falcon, 0x100);
248
249 if (reg & BIT(6))
250 nvkm_falcon_wr32(falcon, 0x130, 0x2);
251 else
252 nvkm_falcon_wr32(falcon, 0x100, 0x2);
253 }
254
255 static int
nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon * falcon,u32 ms)256 nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms)
257 {
258 struct nvkm_device *device = falcon->owner->device;
259 int ret;
260
261 ret = nvkm_wait_msec(device, ms, falcon->addr + 0x100, 0x10, 0x10);
262 if (ret < 0)
263 return ret;
264
265 return 0;
266 }
267
268 static int
nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon * falcon,u32 mask)269 nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask)
270 {
271 struct nvkm_device *device = falcon->owner->device;
272 int ret;
273
274 /* clear interrupt(s) */
275 nvkm_falcon_mask(falcon, 0x004, mask, mask);
276 /* wait until interrupts are cleared */
277 ret = nvkm_wait_msec(device, 10, falcon->addr + 0x008, mask, 0x0);
278 if (ret < 0)
279 return ret;
280
281 return 0;
282 }
283
284 static int
falcon_v1_wait_idle(struct nvkm_falcon * falcon)285 falcon_v1_wait_idle(struct nvkm_falcon *falcon)
286 {
287 struct nvkm_device *device = falcon->owner->device;
288 int ret;
289
290 ret = nvkm_wait_msec(device, 10, falcon->addr + 0x04c, 0xffff, 0x0);
291 if (ret < 0)
292 return ret;
293
294 return 0;
295 }
296
297 static int
nvkm_falcon_v1_enable(struct nvkm_falcon * falcon)298 nvkm_falcon_v1_enable(struct nvkm_falcon *falcon)
299 {
300 struct nvkm_device *device = falcon->owner->device;
301 int ret;
302
303 ret = nvkm_wait_msec(device, 10, falcon->addr + 0x10c, 0x6, 0x0);
304 if (ret < 0) {
305 nvkm_error(falcon->user, "Falcon mem scrubbing timeout\n");
306 return ret;
307 }
308
309 ret = falcon_v1_wait_idle(falcon);
310 if (ret)
311 return ret;
312
313 /* enable IRQs */
314 nvkm_falcon_wr32(falcon, 0x010, 0xff);
315
316 return 0;
317 }
318
319 static void
nvkm_falcon_v1_disable(struct nvkm_falcon * falcon)320 nvkm_falcon_v1_disable(struct nvkm_falcon *falcon)
321 {
322 /* disable IRQs and wait for any previous code to complete */
323 nvkm_falcon_wr32(falcon, 0x014, 0xff);
324 falcon_v1_wait_idle(falcon);
325 }
326
327 static const struct nvkm_falcon_func
328 nvkm_falcon_v1 = {
329 .load_imem = nvkm_falcon_v1_load_imem,
330 .load_dmem = nvkm_falcon_v1_load_dmem,
331 .read_dmem = nvkm_falcon_v1_read_dmem,
332 .bind_context = nvkm_falcon_v1_bind_context,
333 .start = nvkm_falcon_v1_start,
334 .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
335 .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
336 .enable = nvkm_falcon_v1_enable,
337 .disable = nvkm_falcon_v1_disable,
338 .set_start_addr = nvkm_falcon_v1_set_start_addr,
339 };
340
341 int
nvkm_falcon_v1_new(struct nvkm_subdev * owner,const char * name,u32 addr,struct nvkm_falcon ** pfalcon)342 nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr,
343 struct nvkm_falcon **pfalcon)
344 {
345 struct nvkm_falcon *falcon;
346 if (!(falcon = *pfalcon = kzalloc(sizeof(*falcon), GFP_KERNEL)))
347 return -ENOMEM;
348 nvkm_falcon_ctor(&nvkm_falcon_v1, owner, name, addr, falcon);
349 return 0;
350 }
351
