1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_UTIL_H 14 #define _DPU_HW_UTIL_H 15 16 #include <linux/io.h> 17 #include <linux/slab.h> 18 #include "dpu_hw_mdss.h" 19 20 #define REG_MASK(n) ((BIT(n)) - 1) 21 struct dpu_format_extended; 22 23 /* 24 * This is the common struct maintained by each sub block 25 * for mapping the register offsets in this block to the 26 * absoulute IO address 27 * @base_off: mdp register mapped offset 28 * @blk_off: pipe offset relative to mdss offset 29 * @length length of register block offset 30 * @xin_id xin id 31 * @hwversion mdss hw version number 32 */ 33 struct dpu_hw_blk_reg_map { 34 void __iomem *base_off; 35 u32 blk_off; 36 u32 length; 37 u32 xin_id; 38 u32 hwversion; 39 u32 log_mask; 40 }; 41 42 /** 43 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration 44 * @enable: detail enhancer enable/disable 45 * @sharpen_level1: sharpening strength for noise 46 * @sharpen_level2: sharpening strength for signal 47 * @ clip: clip shift 48 * @ limit: limit value 49 * @ thr_quiet: quiet threshold 50 * @ thr_dieout: dieout threshold 51 * @ thr_high: low threshold 52 * @ thr_high: high threshold 53 * @ prec_shift: precision shift 54 * @ adjust_a: A-coefficients for mapping curve 55 * @ adjust_b: B-coefficients for mapping curve 56 * @ adjust_c: C-coefficients for mapping curve 57 */ 58 struct dpu_hw_scaler3_de_cfg { 59 u32 enable; 60 int16_t sharpen_level1; 61 int16_t sharpen_level2; 62 uint16_t clip; 63 uint16_t limit; 64 uint16_t thr_quiet; 65 uint16_t thr_dieout; 66 uint16_t thr_low; 67 uint16_t thr_high; 68 uint16_t prec_shift; 69 int16_t adjust_a[DPU_MAX_DE_CURVES]; 70 int16_t adjust_b[DPU_MAX_DE_CURVES]; 71 int16_t adjust_c[DPU_MAX_DE_CURVES]; 72 }; 73 74 75 /** 76 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration 77 * @enable: scaler enable 78 * @dir_en: direction detection block enable 79 * @ init_phase_x: horizontal initial phase 80 * @ phase_step_x: horizontal phase step 81 * @ init_phase_y: vertical initial phase 82 * @ phase_step_y: vertical phase step 83 * @ preload_x: horizontal preload value 84 * @ preload_y: vertical preload value 85 * @ src_width: source width 86 * @ src_height: source height 87 * @ dst_width: destination width 88 * @ dst_height: destination height 89 * @ y_rgb_filter_cfg: y/rgb plane filter configuration 90 * @ uv_filter_cfg: uv plane filter configuration 91 * @ alpha_filter_cfg: alpha filter configuration 92 * @ blend_cfg: blend coefficients configuration 93 * @ lut_flag: scaler LUT update flags 94 * 0x1 swap LUT bank 95 * 0x2 update 2D filter LUT 96 * 0x4 update y circular filter LUT 97 * 0x8 update uv circular filter LUT 98 * 0x10 update y separable filter LUT 99 * 0x20 update uv separable filter LUT 100 * @ dir_lut_idx: 2D filter LUT index 101 * @ y_rgb_cir_lut_idx: y circular filter LUT index 102 * @ uv_cir_lut_idx: uv circular filter LUT index 103 * @ y_rgb_sep_lut_idx: y circular filter LUT index 104 * @ uv_sep_lut_idx: uv separable filter LUT index 105 * @ dir_lut: pointer to 2D LUT 106 * @ cir_lut: pointer to circular filter LUT 107 * @ sep_lut: pointer to separable filter LUT 108 * @ de: detail enhancer configuration 109 */ 110 struct dpu_hw_scaler3_cfg { 111 u32 enable; 112 u32 dir_en; 113 int32_t init_phase_x[DPU_MAX_PLANES]; 114 int32_t phase_step_x[DPU_MAX_PLANES]; 115 int32_t init_phase_y[DPU_MAX_PLANES]; 116 int32_t phase_step_y[DPU_MAX_PLANES]; 117 118 u32 preload_x[DPU_MAX_PLANES]; 119 u32 preload_y[DPU_MAX_PLANES]; 120 u32 src_width[DPU_MAX_PLANES]; 121 u32 src_height[DPU_MAX_PLANES]; 122 123 u32 dst_width; 124 u32 dst_height; 125 126 u32 y_rgb_filter_cfg; 127 u32 uv_filter_cfg; 128 u32 alpha_filter_cfg; 129 u32 blend_cfg; 130 131 u32 lut_flag; 132 u32 dir_lut_idx; 133 134 u32 y_rgb_cir_lut_idx; 135 u32 uv_cir_lut_idx; 136 u32 y_rgb_sep_lut_idx; 137 u32 uv_sep_lut_idx; 138 u32 *dir_lut; 139 size_t dir_len; 140 u32 *cir_lut; 141 size_t cir_len; 142 u32 *sep_lut; 143 size_t sep_len; 144 145 /* 146 * Detail enhancer settings 147 */ 148 struct dpu_hw_scaler3_de_cfg de; 149 }; 150 151 struct dpu_hw_scaler3_lut_cfg { 152 bool is_configured; 153 u32 *dir_lut; 154 size_t dir_len; 155 u32 *cir_lut; 156 size_t cir_len; 157 u32 *sep_lut; 158 size_t sep_len; 159 }; 160 161 /** 162 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure 163 * @num_ext_pxls_lr: Number of total horizontal pixels 164 * @num_ext_pxls_tb: Number of total vertical lines 165 * @left_ftch: Number of extra pixels to overfetch from left 166 * @right_ftch: Number of extra pixels to overfetch from right 167 * @top_ftch: Number of extra lines to overfetch from top 168 * @btm_ftch: Number of extra lines to overfetch from bottom 169 * @left_rpt: Number of extra pixels to repeat from left 170 * @right_rpt: Number of extra pixels to repeat from right 171 * @top_rpt: Number of extra lines to repeat from top 172 * @btm_rpt: Number of extra lines to repeat from bottom 173 */ 174 struct dpu_drm_pix_ext_v1 { 175 /* 176 * Number of pixels ext in left, right, top and bottom direction 177 * for all color components. 178 */ 179 int32_t num_ext_pxls_lr[DPU_MAX_PLANES]; 180 int32_t num_ext_pxls_tb[DPU_MAX_PLANES]; 181 182 /* 183 * Number of pixels needs to be overfetched in left, right, top 184 * and bottom directions from source image for scaling. 185 */ 186 int32_t left_ftch[DPU_MAX_PLANES]; 187 int32_t right_ftch[DPU_MAX_PLANES]; 188 int32_t top_ftch[DPU_MAX_PLANES]; 189 int32_t btm_ftch[DPU_MAX_PLANES]; 190 /* 191 * Number of pixels needs to be repeated in left, right, top and 192 * bottom directions for scaling. 193 */ 194 int32_t left_rpt[DPU_MAX_PLANES]; 195 int32_t right_rpt[DPU_MAX_PLANES]; 196 int32_t top_rpt[DPU_MAX_PLANES]; 197 int32_t btm_rpt[DPU_MAX_PLANES]; 198 199 }; 200 201 /** 202 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure 203 * @enable: Enables/disables detail enhancer 204 * @sharpen_level1: Sharpening strength for noise 205 * @sharpen_level2: Sharpening strength for context 206 * @clip: Clip coefficient 207 * @limit: Detail enhancer limit factor 208 * @thr_quiet: Quite zone threshold 209 * @thr_dieout: Die-out zone threshold 210 * @thr_low: Linear zone left threshold 211 * @thr_high: Linear zone right threshold 212 * @prec_shift: Detail enhancer precision 213 * @adjust_a: Mapping curves A coefficients 214 * @adjust_b: Mapping curves B coefficients 215 * @adjust_c: Mapping curves C coefficients 216 */ 217 struct dpu_drm_de_v1 { 218 uint32_t enable; 219 int16_t sharpen_level1; 220 int16_t sharpen_level2; 221 uint16_t clip; 222 uint16_t limit; 223 uint16_t thr_quiet; 224 uint16_t thr_dieout; 225 uint16_t thr_low; 226 uint16_t thr_high; 227 uint16_t prec_shift; 228 int16_t adjust_a[DPU_MAX_DE_CURVES]; 229 int16_t adjust_b[DPU_MAX_DE_CURVES]; 230 int16_t adjust_c[DPU_MAX_DE_CURVES]; 231 }; 232 233 /** 234 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler 235 * @enable: Scaler enable 236 * @dir_en: Detail enhancer enable 237 * @pe: Pixel extension settings 238 * @horz_decimate: Horizontal decimation factor 239 * @vert_decimate: Vertical decimation factor 240 * @init_phase_x: Initial scaler phase values for x 241 * @phase_step_x: Phase step values for x 242 * @init_phase_y: Initial scaler phase values for y 243 * @phase_step_y: Phase step values for y 244 * @preload_x: Horizontal preload value 245 * @preload_y: Vertical preload value 246 * @src_width: Source width 247 * @src_height: Source height 248 * @dst_width: Destination width 249 * @dst_height: Destination height 250 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 251 * @uv_filter_cfg: UV plane filter configuration 252 * @alpha_filter_cfg: Alpha filter configuration 253 * @blend_cfg: Selection of blend coefficients 254 * @lut_flag: LUT configuration flags 255 * @dir_lut_idx: 2d 4x4 LUT index 256 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 257 * @uv_cir_lut_idx: UV circular LUT index 258 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 259 * @uv_sep_lut_idx: UV separable LUT index 260 * @de: Detail enhancer settings 261 */ 262 struct dpu_drm_scaler_v2 { 263 /* 264 * General definitions 265 */ 266 uint32_t enable; 267 uint32_t dir_en; 268 269 /* 270 * Pix ext settings 271 */ 272 struct dpu_drm_pix_ext_v1 pe; 273 274 /* 275 * Decimation settings 276 */ 277 uint32_t horz_decimate; 278 uint32_t vert_decimate; 279 280 /* 281 * Phase settings 282 */ 283 int32_t init_phase_x[DPU_MAX_PLANES]; 284 int32_t phase_step_x[DPU_MAX_PLANES]; 285 int32_t init_phase_y[DPU_MAX_PLANES]; 286 int32_t phase_step_y[DPU_MAX_PLANES]; 287 288 uint32_t preload_x[DPU_MAX_PLANES]; 289 uint32_t preload_y[DPU_MAX_PLANES]; 290 uint32_t src_width[DPU_MAX_PLANES]; 291 uint32_t src_height[DPU_MAX_PLANES]; 292 293 uint32_t dst_width; 294 uint32_t dst_height; 295 296 uint32_t y_rgb_filter_cfg; 297 uint32_t uv_filter_cfg; 298 uint32_t alpha_filter_cfg; 299 uint32_t blend_cfg; 300 301 uint32_t lut_flag; 302 uint32_t dir_lut_idx; 303 304 /* for Y(RGB) and UV planes*/ 305 uint32_t y_rgb_cir_lut_idx; 306 uint32_t uv_cir_lut_idx; 307 uint32_t y_rgb_sep_lut_idx; 308 uint32_t uv_sep_lut_idx; 309 310 /* 311 * Detail enhancer settings 312 */ 313 struct dpu_drm_de_v1 de; 314 }; 315 316 317 u32 *dpu_hw_util_get_log_mask_ptr(void); 318 319 void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 320 u32 reg_off, 321 u32 val, 322 const char *name); 323 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off); 324 325 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) 326 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) 327 328 #define MISR_FRAME_COUNT_MASK 0xFF 329 #define MISR_CTRL_ENABLE BIT(8) 330 #define MISR_CTRL_STATUS BIT(9) 331 #define MISR_CTRL_STATUS_CLEAR BIT(10) 332 #define INTF_MISR_CTRL_FREE_RUN_MASK BIT(31) 333 334 void *dpu_hw_util_get_dir(void); 335 336 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 337 struct dpu_hw_scaler3_cfg *scaler3_cfg, 338 u32 scaler_offset, u32 scaler_version, 339 const struct dpu_format *format); 340 341 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 342 u32 scaler_offset); 343 344 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 345 u32 csc_reg_off, 346 struct dpu_csc_cfg *data, bool csc10); 347 348 #endif /* _DPU_HW_UTIL_H */ 349
