1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #include "dpu_hwio.h"
14 #include "dpu_hw_catalog.h"
15 #include "dpu_hw_intf.h"
16 #include "dpu_dbg.h"
17 #include "dpu_kms.h"
18
19 #define INTF_TIMING_ENGINE_EN 0x000
20 #define INTF_CONFIG 0x004
21 #define INTF_HSYNC_CTL 0x008
22 #define INTF_VSYNC_PERIOD_F0 0x00C
23 #define INTF_VSYNC_PERIOD_F1 0x010
24 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
25 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
26 #define INTF_DISPLAY_V_START_F0 0x01C
27 #define INTF_DISPLAY_V_START_F1 0x020
28 #define INTF_DISPLAY_V_END_F0 0x024
29 #define INTF_DISPLAY_V_END_F1 0x028
30 #define INTF_ACTIVE_V_START_F0 0x02C
31 #define INTF_ACTIVE_V_START_F1 0x030
32 #define INTF_ACTIVE_V_END_F0 0x034
33 #define INTF_ACTIVE_V_END_F1 0x038
34 #define INTF_DISPLAY_HCTL 0x03C
35 #define INTF_ACTIVE_HCTL 0x040
36 #define INTF_BORDER_COLOR 0x044
37 #define INTF_UNDERFLOW_COLOR 0x048
38 #define INTF_HSYNC_SKEW 0x04C
39 #define INTF_POLARITY_CTL 0x050
40 #define INTF_TEST_CTL 0x054
41 #define INTF_TP_COLOR0 0x058
42 #define INTF_TP_COLOR1 0x05C
43 #define INTF_FRAME_LINE_COUNT_EN 0x0A8
44 #define INTF_FRAME_COUNT 0x0AC
45 #define INTF_LINE_COUNT 0x0B0
46
47 #define INTF_DEFLICKER_CONFIG 0x0F0
48 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
49 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
50
51 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
52 #define INTF_PANEL_FORMAT 0x090
53 #define INTF_TPG_ENABLE 0x100
54 #define INTF_TPG_MAIN_CONTROL 0x104
55 #define INTF_TPG_VIDEO_CONFIG 0x108
56 #define INTF_TPG_COMPONENT_LIMITS 0x10C
57 #define INTF_TPG_RECTANGLE 0x110
58 #define INTF_TPG_INITIAL_VALUE 0x114
59 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
60 #define INTF_TPG_RGB_MAPPING 0x11C
61 #define INTF_PROG_FETCH_START 0x170
62 #define INTF_PROG_ROT_START 0x174
63
64 #define INTF_FRAME_LINE_COUNT_EN 0x0A8
65 #define INTF_FRAME_COUNT 0x0AC
66 #define INTF_LINE_COUNT 0x0B0
67
68 #define INTF_MISR_CTRL 0x180
69 #define INTF_MISR_SIGNATURE 0x184
70
_intf_offset(enum dpu_intf intf,struct dpu_mdss_cfg * m,void __iomem * addr,struct dpu_hw_blk_reg_map * b)71 static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
72 struct dpu_mdss_cfg *m,
73 void __iomem *addr,
74 struct dpu_hw_blk_reg_map *b)
75 {
76 int i;
77
78 for (i = 0; i < m->intf_count; i++) {
79 if ((intf == m->intf[i].id) &&
80 (m->intf[i].type != INTF_NONE)) {
81 b->base_off = addr;
82 b->blk_off = m->intf[i].base;
83 b->length = m->intf[i].len;
84 b->hwversion = m->hwversion;
85 b->log_mask = DPU_DBG_MASK_INTF;
86 return &m->intf[i];
87 }
88 }
89
90 return ERR_PTR(-EINVAL);
91 }
92
dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf * ctx,const struct intf_timing_params * p,const struct dpu_format * fmt)93 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
94 const struct intf_timing_params *p,
95 const struct dpu_format *fmt)
96 {
97 struct dpu_hw_blk_reg_map *c = &ctx->hw;
98 u32 hsync_period, vsync_period;
99 u32 display_v_start, display_v_end;
100 u32 hsync_start_x, hsync_end_x;
101 u32 active_h_start, active_h_end;
102 u32 active_v_start, active_v_end;
103 u32 active_hctl, display_hctl, hsync_ctl;
104 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
105 u32 panel_format;
106 u32 intf_cfg;
107
108 /* read interface_cfg */
109 intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
110 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
111 p->h_front_porch;
112 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
113 p->v_front_porch;
114
115 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
116 hsync_period) + p->hsync_skew;
117 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
118 p->hsync_skew - 1;
119
120 if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
121 display_v_start += p->hsync_pulse_width + p->h_back_porch;
122 display_v_end -= p->h_front_porch;
123 }
124
125 hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
126 hsync_end_x = hsync_period - p->h_front_porch - 1;
127
128 if (p->width != p->xres) {
129 active_h_start = hsync_start_x;
130 active_h_end = active_h_start + p->xres - 1;
131 } else {
132 active_h_start = 0;
133 active_h_end = 0;
134 }
135
136 if (p->height != p->yres) {
137 active_v_start = display_v_start;
138 active_v_end = active_v_start + (p->yres * hsync_period) - 1;
139 } else {
140 active_v_start = 0;
141 active_v_end = 0;
142 }
143
144 if (active_h_end) {
145 active_hctl = (active_h_end << 16) | active_h_start;
146 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
147 } else {
148 active_hctl = 0;
149 }
150
151 if (active_v_end)
152 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
153
154 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
155 display_hctl = (hsync_end_x << 16) | hsync_start_x;
156
157 den_polarity = 0;
158 if (ctx->cap->type == INTF_HDMI) {
159 hsync_polarity = p->yres >= 720 ? 0 : 1;
160 vsync_polarity = p->yres >= 720 ? 0 : 1;
161 } else {
162 hsync_polarity = 0;
163 vsync_polarity = 0;
164 }
165 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
166 (vsync_polarity << 1) | /* VSYNC Polarity */
167 (hsync_polarity << 0); /* HSYNC Polarity */
168
169 if (!DPU_FORMAT_IS_YUV(fmt))
170 panel_format = (fmt->bits[C0_G_Y] |
171 (fmt->bits[C1_B_Cb] << 2) |
172 (fmt->bits[C2_R_Cr] << 4) |
173 (0x21 << 8));
174 else
175 /* Interface treats all the pixel data in RGB888 format */
176 panel_format = (COLOR_8BIT |
177 (COLOR_8BIT << 2) |
178 (COLOR_8BIT << 4) |
179 (0x21 << 8));
180
181 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
182 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
183 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
184 p->vsync_pulse_width * hsync_period);
185 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
186 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
187 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
188 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
189 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
190 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
191 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
192 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
193 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
194 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
195 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
196 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
197 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
198 }
199
dpu_hw_intf_enable_timing_engine(struct dpu_hw_intf * intf,u8 enable)200 static void dpu_hw_intf_enable_timing_engine(
201 struct dpu_hw_intf *intf,
202 u8 enable)
203 {
204 struct dpu_hw_blk_reg_map *c = &intf->hw;
205 /* Note: Display interface select is handled in top block hw layer */
206 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
207 }
208
dpu_hw_intf_setup_prg_fetch(struct dpu_hw_intf * intf,const struct intf_prog_fetch * fetch)209 static void dpu_hw_intf_setup_prg_fetch(
210 struct dpu_hw_intf *intf,
211 const struct intf_prog_fetch *fetch)
212 {
213 struct dpu_hw_blk_reg_map *c = &intf->hw;
214 int fetch_enable;
215
216 /*
217 * Fetch should always be outside the active lines. If the fetching
218 * is programmed within active region, hardware behavior is unknown.
219 */
220
221 fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
222 if (fetch->enable) {
223 fetch_enable |= BIT(31);
224 DPU_REG_WRITE(c, INTF_PROG_FETCH_START,
225 fetch->fetch_start);
226 } else {
227 fetch_enable &= ~BIT(31);
228 }
229
230 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
231 }
232
dpu_hw_intf_get_status(struct dpu_hw_intf * intf,struct intf_status * s)233 static void dpu_hw_intf_get_status(
234 struct dpu_hw_intf *intf,
235 struct intf_status *s)
236 {
237 struct dpu_hw_blk_reg_map *c = &intf->hw;
238
239 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
240 if (s->is_en) {
241 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
242 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);
243 } else {
244 s->line_count = 0;
245 s->frame_count = 0;
246 }
247 }
248
dpu_hw_intf_setup_misr(struct dpu_hw_intf * intf,bool enable,u32 frame_count)249 static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf,
250 bool enable, u32 frame_count)
251 {
252 struct dpu_hw_blk_reg_map *c = &intf->hw;
253 u32 config = 0;
254
255 DPU_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
256 /* clear misr data */
257 wmb();
258
259 if (enable)
260 config = (frame_count & MISR_FRAME_COUNT_MASK) |
261 MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
262
263 DPU_REG_WRITE(c, INTF_MISR_CTRL, config);
264 }
265
dpu_hw_intf_collect_misr(struct dpu_hw_intf * intf)266 static u32 dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf)
267 {
268 struct dpu_hw_blk_reg_map *c = &intf->hw;
269
270 return DPU_REG_READ(c, INTF_MISR_SIGNATURE);
271 }
272
dpu_hw_intf_get_line_count(struct dpu_hw_intf * intf)273 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
274 {
275 struct dpu_hw_blk_reg_map *c;
276
277 if (!intf)
278 return 0;
279
280 c = &intf->hw;
281
282 return DPU_REG_READ(c, INTF_LINE_COUNT);
283 }
284
_setup_intf_ops(struct dpu_hw_intf_ops * ops,unsigned long cap)285 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
286 unsigned long cap)
287 {
288 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
289 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
290 ops->get_status = dpu_hw_intf_get_status;
291 ops->enable_timing = dpu_hw_intf_enable_timing_engine;
292 ops->setup_misr = dpu_hw_intf_setup_misr;
293 ops->collect_misr = dpu_hw_intf_collect_misr;
294 ops->get_line_count = dpu_hw_intf_get_line_count;
295 }
296
297 static struct dpu_hw_blk_ops dpu_hw_ops = {
298 .start = NULL,
299 .stop = NULL,
300 };
301
dpu_hw_intf_init(enum dpu_intf idx,void __iomem * addr,struct dpu_mdss_cfg * m)302 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
303 void __iomem *addr,
304 struct dpu_mdss_cfg *m)
305 {
306 struct dpu_hw_intf *c;
307 struct dpu_intf_cfg *cfg;
308 int rc;
309
310 c = kzalloc(sizeof(*c), GFP_KERNEL);
311 if (!c)
312 return ERR_PTR(-ENOMEM);
313
314 cfg = _intf_offset(idx, m, addr, &c->hw);
315 if (IS_ERR_OR_NULL(cfg)) {
316 kfree(c);
317 pr_err("failed to create dpu_hw_intf %d\n", idx);
318 return ERR_PTR(-EINVAL);
319 }
320
321 /*
322 * Assign ops
323 */
324 c->idx = idx;
325 c->cap = cfg;
326 c->mdss = m;
327 _setup_intf_ops(&c->ops, c->cap->features);
328
329 rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
330 if (rc) {
331 DPU_ERROR("failed to init hw blk %d\n", rc);
332 goto blk_init_error;
333 }
334
335 return c;
336
337 blk_init_error:
338 kzfree(c);
339
340 return ERR_PTR(rc);
341 }
342
dpu_hw_intf_destroy(struct dpu_hw_intf * intf)343 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
344 {
345 if (intf)
346 dpu_hw_blk_destroy(&intf->base);
347 kfree(intf);
348 }
349
350
