1 /* Copyright (c) 2009-2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
15 #include <linux/delay.h>
16 #include <linux/spinlock.h>
17 #include <linux/ktime.h>
18 #include <linux/debugfs.h>
19 #include <linux/uaccess.h>
20 #include <linux/dma-buf.h>
21 #include <linux/slab.h>
22 #include <linux/list_sort.h>
23 #include <linux/pm_runtime.h>
24
25 #include "dpu_dbg.h"
26 #include "disp/dpu1/dpu_hw_catalog.h"
27
28
29 #define DEFAULT_DBGBUS_DPU DPU_DBG_DUMP_IN_MEM
30 #define DEFAULT_DBGBUS_VBIFRT DPU_DBG_DUMP_IN_MEM
31 #define REG_BASE_NAME_LEN 80
32
33 #define DBGBUS_FLAGS_DSPP BIT(0)
34 #define DBGBUS_DSPP_STATUS 0x34C
35
36 #define DBGBUS_NAME_DPU "dpu"
37 #define DBGBUS_NAME_VBIF_RT "vbif_rt"
38
39 /* offsets from dpu top address for the debug buses */
40 #define DBGBUS_SSPP0 0x188
41 #define DBGBUS_AXI_INTF 0x194
42 #define DBGBUS_SSPP1 0x298
43 #define DBGBUS_DSPP 0x348
44 #define DBGBUS_PERIPH 0x418
45
46 #define TEST_MASK(id, tp) ((id << 4) | (tp << 1) | BIT(0))
47
48 /* following offsets are with respect to MDP VBIF base for DBG BUS access */
49 #define MMSS_VBIF_CLKON 0x4
50 #define MMSS_VBIF_TEST_BUS_OUT_CTRL 0x210
51 #define MMSS_VBIF_TEST_BUS_OUT 0x230
52
53 /* Vbif error info */
54 #define MMSS_VBIF_PND_ERR 0x190
55 #define MMSS_VBIF_SRC_ERR 0x194
56 #define MMSS_VBIF_XIN_HALT_CTRL1 0x204
57 #define MMSS_VBIF_ERR_INFO 0X1a0
58 #define MMSS_VBIF_ERR_INFO_1 0x1a4
59 #define MMSS_VBIF_CLIENT_NUM 14
60
61 /**
62 * struct dpu_dbg_reg_base - register region base.
63 * may sub-ranges: sub-ranges are used for dumping
64 * or may not have sub-ranges: dumping is base -> max_offset
65 * @reg_base_head: head of this node
66 * @name: register base name
67 * @base: base pointer
68 * @off: cached offset of region for manual register dumping
69 * @cnt: cached range of region for manual register dumping
70 * @max_offset: length of region
71 * @buf: buffer used for manual register dumping
72 * @buf_len: buffer length used for manual register dumping
73 * @cb: callback for external dump function, null if not defined
74 * @cb_ptr: private pointer to callback function
75 */
76 struct dpu_dbg_reg_base {
77 struct list_head reg_base_head;
78 char name[REG_BASE_NAME_LEN];
79 void __iomem *base;
80 size_t off;
81 size_t cnt;
82 size_t max_offset;
83 char *buf;
84 size_t buf_len;
85 void (*cb)(void *ptr);
86 void *cb_ptr;
87 };
88
89 struct dpu_debug_bus_entry {
90 u32 wr_addr;
91 u32 block_id;
92 u32 test_id;
93 void (*analyzer)(void __iomem *mem_base,
94 struct dpu_debug_bus_entry *entry, u32 val);
95 };
96
97 struct vbif_debug_bus_entry {
98 u32 disable_bus_addr;
99 u32 block_bus_addr;
100 u32 bit_offset;
101 u32 block_cnt;
102 u32 test_pnt_start;
103 u32 test_pnt_cnt;
104 };
105
106 struct dpu_dbg_debug_bus_common {
107 char *name;
108 u32 enable_mask;
109 bool include_in_deferred_work;
110 u32 flags;
111 u32 entries_size;
112 u32 *dumped_content;
113 };
114
115 struct dpu_dbg_dpu_debug_bus {
116 struct dpu_dbg_debug_bus_common cmn;
117 struct dpu_debug_bus_entry *entries;
118 u32 top_blk_off;
119 };
120
121 struct dpu_dbg_vbif_debug_bus {
122 struct dpu_dbg_debug_bus_common cmn;
123 struct vbif_debug_bus_entry *entries;
124 };
125
126 /**
127 * struct dpu_dbg_base - global dpu debug base structure
128 * @reg_base_list: list of register dumping regions
129 * @dev: device pointer
130 * @dump_work: work struct for deferring register dump work to separate thread
131 * @dbgbus_dpu: debug bus structure for the dpu
132 * @dbgbus_vbif_rt: debug bus structure for the realtime vbif
133 */
134 static struct dpu_dbg_base {
135 struct list_head reg_base_list;
136 struct device *dev;
137
138 struct work_struct dump_work;
139
140 struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
141 struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
142 } dpu_dbg_base;
143
_dpu_debug_bus_xbar_dump(void __iomem * mem_base,struct dpu_debug_bus_entry * entry,u32 val)144 static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
145 struct dpu_debug_bus_entry *entry, u32 val)
146 {
147 dev_err(dpu_dbg_base.dev, "xbar 0x%x %d %d 0x%x\n",
148 entry->wr_addr, entry->block_id, entry->test_id, val);
149 }
150
_dpu_debug_bus_lm_dump(void __iomem * mem_base,struct dpu_debug_bus_entry * entry,u32 val)151 static void _dpu_debug_bus_lm_dump(void __iomem *mem_base,
152 struct dpu_debug_bus_entry *entry, u32 val)
153 {
154 if (!(val & 0xFFF000))
155 return;
156
157 dev_err(dpu_dbg_base.dev, "lm 0x%x %d %d 0x%x\n",
158 entry->wr_addr, entry->block_id, entry->test_id, val);
159 }
160
_dpu_debug_bus_ppb0_dump(void __iomem * mem_base,struct dpu_debug_bus_entry * entry,u32 val)161 static void _dpu_debug_bus_ppb0_dump(void __iomem *mem_base,
162 struct dpu_debug_bus_entry *entry, u32 val)
163 {
164 if (!(val & BIT(15)))
165 return;
166
167 dev_err(dpu_dbg_base.dev, "ppb0 0x%x %d %d 0x%x\n",
168 entry->wr_addr, entry->block_id, entry->test_id, val);
169 }
170
_dpu_debug_bus_ppb1_dump(void __iomem * mem_base,struct dpu_debug_bus_entry * entry,u32 val)171 static void _dpu_debug_bus_ppb1_dump(void __iomem *mem_base,
172 struct dpu_debug_bus_entry *entry, u32 val)
173 {
174 if (!(val & BIT(15)))
175 return;
176
177 dev_err(dpu_dbg_base.dev, "ppb1 0x%x %d %d 0x%x\n",
178 entry->wr_addr, entry->block_id, entry->test_id, val);
179 }
180
181 static struct dpu_debug_bus_entry dbg_bus_dpu_8998[] = {
182
183 /* Unpack 0 sspp 0*/
184 { DBGBUS_SSPP0, 50, 2 },
185 { DBGBUS_SSPP0, 60, 2 },
186 { DBGBUS_SSPP0, 70, 2 },
187 { DBGBUS_SSPP0, 85, 2 },
188
189 /* Upack 0 sspp 1*/
190 { DBGBUS_SSPP1, 50, 2 },
191 { DBGBUS_SSPP1, 60, 2 },
192 { DBGBUS_SSPP1, 70, 2 },
193 { DBGBUS_SSPP1, 85, 2 },
194
195 /* scheduler */
196 { DBGBUS_DSPP, 130, 0 },
197 { DBGBUS_DSPP, 130, 1 },
198 { DBGBUS_DSPP, 130, 2 },
199 { DBGBUS_DSPP, 130, 3 },
200 { DBGBUS_DSPP, 130, 4 },
201 { DBGBUS_DSPP, 130, 5 },
202
203 /* qseed */
204 { DBGBUS_SSPP0, 6, 0},
205 { DBGBUS_SSPP0, 6, 1},
206 { DBGBUS_SSPP0, 26, 0},
207 { DBGBUS_SSPP0, 26, 1},
208 { DBGBUS_SSPP1, 6, 0},
209 { DBGBUS_SSPP1, 6, 1},
210 { DBGBUS_SSPP1, 26, 0},
211 { DBGBUS_SSPP1, 26, 1},
212
213 /* scale */
214 { DBGBUS_SSPP0, 16, 0},
215 { DBGBUS_SSPP0, 16, 1},
216 { DBGBUS_SSPP0, 36, 0},
217 { DBGBUS_SSPP0, 36, 1},
218 { DBGBUS_SSPP1, 16, 0},
219 { DBGBUS_SSPP1, 16, 1},
220 { DBGBUS_SSPP1, 36, 0},
221 { DBGBUS_SSPP1, 36, 1},
222
223 /* fetch sspp0 */
224
225 /* vig 0 */
226 { DBGBUS_SSPP0, 0, 0 },
227 { DBGBUS_SSPP0, 0, 1 },
228 { DBGBUS_SSPP0, 0, 2 },
229 { DBGBUS_SSPP0, 0, 3 },
230 { DBGBUS_SSPP0, 0, 4 },
231 { DBGBUS_SSPP0, 0, 5 },
232 { DBGBUS_SSPP0, 0, 6 },
233 { DBGBUS_SSPP0, 0, 7 },
234
235 { DBGBUS_SSPP0, 1, 0 },
236 { DBGBUS_SSPP0, 1, 1 },
237 { DBGBUS_SSPP0, 1, 2 },
238 { DBGBUS_SSPP0, 1, 3 },
239 { DBGBUS_SSPP0, 1, 4 },
240 { DBGBUS_SSPP0, 1, 5 },
241 { DBGBUS_SSPP0, 1, 6 },
242 { DBGBUS_SSPP0, 1, 7 },
243
244 { DBGBUS_SSPP0, 2, 0 },
245 { DBGBUS_SSPP0, 2, 1 },
246 { DBGBUS_SSPP0, 2, 2 },
247 { DBGBUS_SSPP0, 2, 3 },
248 { DBGBUS_SSPP0, 2, 4 },
249 { DBGBUS_SSPP0, 2, 5 },
250 { DBGBUS_SSPP0, 2, 6 },
251 { DBGBUS_SSPP0, 2, 7 },
252
253 { DBGBUS_SSPP0, 4, 0 },
254 { DBGBUS_SSPP0, 4, 1 },
255 { DBGBUS_SSPP0, 4, 2 },
256 { DBGBUS_SSPP0, 4, 3 },
257 { DBGBUS_SSPP0, 4, 4 },
258 { DBGBUS_SSPP0, 4, 5 },
259 { DBGBUS_SSPP0, 4, 6 },
260 { DBGBUS_SSPP0, 4, 7 },
261
262 { DBGBUS_SSPP0, 5, 0 },
263 { DBGBUS_SSPP0, 5, 1 },
264 { DBGBUS_SSPP0, 5, 2 },
265 { DBGBUS_SSPP0, 5, 3 },
266 { DBGBUS_SSPP0, 5, 4 },
267 { DBGBUS_SSPP0, 5, 5 },
268 { DBGBUS_SSPP0, 5, 6 },
269 { DBGBUS_SSPP0, 5, 7 },
270
271 /* vig 2 */
272 { DBGBUS_SSPP0, 20, 0 },
273 { DBGBUS_SSPP0, 20, 1 },
274 { DBGBUS_SSPP0, 20, 2 },
275 { DBGBUS_SSPP0, 20, 3 },
276 { DBGBUS_SSPP0, 20, 4 },
277 { DBGBUS_SSPP0, 20, 5 },
278 { DBGBUS_SSPP0, 20, 6 },
279 { DBGBUS_SSPP0, 20, 7 },
280
281 { DBGBUS_SSPP0, 21, 0 },
282 { DBGBUS_SSPP0, 21, 1 },
283 { DBGBUS_SSPP0, 21, 2 },
284 { DBGBUS_SSPP0, 21, 3 },
285 { DBGBUS_SSPP0, 21, 4 },
286 { DBGBUS_SSPP0, 21, 5 },
287 { DBGBUS_SSPP0, 21, 6 },
288 { DBGBUS_SSPP0, 21, 7 },
289
290 { DBGBUS_SSPP0, 22, 0 },
291 { DBGBUS_SSPP0, 22, 1 },
292 { DBGBUS_SSPP0, 22, 2 },
293 { DBGBUS_SSPP0, 22, 3 },
294 { DBGBUS_SSPP0, 22, 4 },
295 { DBGBUS_SSPP0, 22, 5 },
296 { DBGBUS_SSPP0, 22, 6 },
297 { DBGBUS_SSPP0, 22, 7 },
298
299 { DBGBUS_SSPP0, 24, 0 },
300 { DBGBUS_SSPP0, 24, 1 },
301 { DBGBUS_SSPP0, 24, 2 },
302 { DBGBUS_SSPP0, 24, 3 },
303 { DBGBUS_SSPP0, 24, 4 },
304 { DBGBUS_SSPP0, 24, 5 },
305 { DBGBUS_SSPP0, 24, 6 },
306 { DBGBUS_SSPP0, 24, 7 },
307
308 { DBGBUS_SSPP0, 25, 0 },
309 { DBGBUS_SSPP0, 25, 1 },
310 { DBGBUS_SSPP0, 25, 2 },
311 { DBGBUS_SSPP0, 25, 3 },
312 { DBGBUS_SSPP0, 25, 4 },
313 { DBGBUS_SSPP0, 25, 5 },
314 { DBGBUS_SSPP0, 25, 6 },
315 { DBGBUS_SSPP0, 25, 7 },
316
317 /* dma 2 */
318 { DBGBUS_SSPP0, 30, 0 },
319 { DBGBUS_SSPP0, 30, 1 },
320 { DBGBUS_SSPP0, 30, 2 },
321 { DBGBUS_SSPP0, 30, 3 },
322 { DBGBUS_SSPP0, 30, 4 },
323 { DBGBUS_SSPP0, 30, 5 },
324 { DBGBUS_SSPP0, 30, 6 },
325 { DBGBUS_SSPP0, 30, 7 },
326
327 { DBGBUS_SSPP0, 31, 0 },
328 { DBGBUS_SSPP0, 31, 1 },
329 { DBGBUS_SSPP0, 31, 2 },
330 { DBGBUS_SSPP0, 31, 3 },
331 { DBGBUS_SSPP0, 31, 4 },
332 { DBGBUS_SSPP0, 31, 5 },
333 { DBGBUS_SSPP0, 31, 6 },
334 { DBGBUS_SSPP0, 31, 7 },
335
336 { DBGBUS_SSPP0, 32, 0 },
337 { DBGBUS_SSPP0, 32, 1 },
338 { DBGBUS_SSPP0, 32, 2 },
339 { DBGBUS_SSPP0, 32, 3 },
340 { DBGBUS_SSPP0, 32, 4 },
341 { DBGBUS_SSPP0, 32, 5 },
342 { DBGBUS_SSPP0, 32, 6 },
343 { DBGBUS_SSPP0, 32, 7 },
344
345 { DBGBUS_SSPP0, 33, 0 },
346 { DBGBUS_SSPP0, 33, 1 },
347 { DBGBUS_SSPP0, 33, 2 },
348 { DBGBUS_SSPP0, 33, 3 },
349 { DBGBUS_SSPP0, 33, 4 },
350 { DBGBUS_SSPP0, 33, 5 },
351 { DBGBUS_SSPP0, 33, 6 },
352 { DBGBUS_SSPP0, 33, 7 },
353
354 { DBGBUS_SSPP0, 34, 0 },
355 { DBGBUS_SSPP0, 34, 1 },
356 { DBGBUS_SSPP0, 34, 2 },
357 { DBGBUS_SSPP0, 34, 3 },
358 { DBGBUS_SSPP0, 34, 4 },
359 { DBGBUS_SSPP0, 34, 5 },
360 { DBGBUS_SSPP0, 34, 6 },
361 { DBGBUS_SSPP0, 34, 7 },
362
363 { DBGBUS_SSPP0, 35, 0 },
364 { DBGBUS_SSPP0, 35, 1 },
365 { DBGBUS_SSPP0, 35, 2 },
366 { DBGBUS_SSPP0, 35, 3 },
367
368 /* dma 0 */
369 { DBGBUS_SSPP0, 40, 0 },
370 { DBGBUS_SSPP0, 40, 1 },
371 { DBGBUS_SSPP0, 40, 2 },
372 { DBGBUS_SSPP0, 40, 3 },
373 { DBGBUS_SSPP0, 40, 4 },
374 { DBGBUS_SSPP0, 40, 5 },
375 { DBGBUS_SSPP0, 40, 6 },
376 { DBGBUS_SSPP0, 40, 7 },
377
378 { DBGBUS_SSPP0, 41, 0 },
379 { DBGBUS_SSPP0, 41, 1 },
380 { DBGBUS_SSPP0, 41, 2 },
381 { DBGBUS_SSPP0, 41, 3 },
382 { DBGBUS_SSPP0, 41, 4 },
383 { DBGBUS_SSPP0, 41, 5 },
384 { DBGBUS_SSPP0, 41, 6 },
385 { DBGBUS_SSPP0, 41, 7 },
386
387 { DBGBUS_SSPP0, 42, 0 },
388 { DBGBUS_SSPP0, 42, 1 },
389 { DBGBUS_SSPP0, 42, 2 },
390 { DBGBUS_SSPP0, 42, 3 },
391 { DBGBUS_SSPP0, 42, 4 },
392 { DBGBUS_SSPP0, 42, 5 },
393 { DBGBUS_SSPP0, 42, 6 },
394 { DBGBUS_SSPP0, 42, 7 },
395
396 { DBGBUS_SSPP0, 44, 0 },
397 { DBGBUS_SSPP0, 44, 1 },
398 { DBGBUS_SSPP0, 44, 2 },
399 { DBGBUS_SSPP0, 44, 3 },
400 { DBGBUS_SSPP0, 44, 4 },
401 { DBGBUS_SSPP0, 44, 5 },
402 { DBGBUS_SSPP0, 44, 6 },
403 { DBGBUS_SSPP0, 44, 7 },
404
405 { DBGBUS_SSPP0, 45, 0 },
406 { DBGBUS_SSPP0, 45, 1 },
407 { DBGBUS_SSPP0, 45, 2 },
408 { DBGBUS_SSPP0, 45, 3 },
409 { DBGBUS_SSPP0, 45, 4 },
410 { DBGBUS_SSPP0, 45, 5 },
411 { DBGBUS_SSPP0, 45, 6 },
412 { DBGBUS_SSPP0, 45, 7 },
413
414 /* fetch sspp1 */
415 /* vig 1 */
416 { DBGBUS_SSPP1, 0, 0 },
417 { DBGBUS_SSPP1, 0, 1 },
418 { DBGBUS_SSPP1, 0, 2 },
419 { DBGBUS_SSPP1, 0, 3 },
420 { DBGBUS_SSPP1, 0, 4 },
421 { DBGBUS_SSPP1, 0, 5 },
422 { DBGBUS_SSPP1, 0, 6 },
423 { DBGBUS_SSPP1, 0, 7 },
424
425 { DBGBUS_SSPP1, 1, 0 },
426 { DBGBUS_SSPP1, 1, 1 },
427 { DBGBUS_SSPP1, 1, 2 },
428 { DBGBUS_SSPP1, 1, 3 },
429 { DBGBUS_SSPP1, 1, 4 },
430 { DBGBUS_SSPP1, 1, 5 },
431 { DBGBUS_SSPP1, 1, 6 },
432 { DBGBUS_SSPP1, 1, 7 },
433
434 { DBGBUS_SSPP1, 2, 0 },
435 { DBGBUS_SSPP1, 2, 1 },
436 { DBGBUS_SSPP1, 2, 2 },
437 { DBGBUS_SSPP1, 2, 3 },
438 { DBGBUS_SSPP1, 2, 4 },
439 { DBGBUS_SSPP1, 2, 5 },
440 { DBGBUS_SSPP1, 2, 6 },
441 { DBGBUS_SSPP1, 2, 7 },
442
443 { DBGBUS_SSPP1, 4, 0 },
444 { DBGBUS_SSPP1, 4, 1 },
445 { DBGBUS_SSPP1, 4, 2 },
446 { DBGBUS_SSPP1, 4, 3 },
447 { DBGBUS_SSPP1, 4, 4 },
448 { DBGBUS_SSPP1, 4, 5 },
449 { DBGBUS_SSPP1, 4, 6 },
450 { DBGBUS_SSPP1, 4, 7 },
451
452 { DBGBUS_SSPP1, 5, 0 },
453 { DBGBUS_SSPP1, 5, 1 },
454 { DBGBUS_SSPP1, 5, 2 },
455 { DBGBUS_SSPP1, 5, 3 },
456 { DBGBUS_SSPP1, 5, 4 },
457 { DBGBUS_SSPP1, 5, 5 },
458 { DBGBUS_SSPP1, 5, 6 },
459 { DBGBUS_SSPP1, 5, 7 },
460
461 /* vig 3 */
462 { DBGBUS_SSPP1, 20, 0 },
463 { DBGBUS_SSPP1, 20, 1 },
464 { DBGBUS_SSPP1, 20, 2 },
465 { DBGBUS_SSPP1, 20, 3 },
466 { DBGBUS_SSPP1, 20, 4 },
467 { DBGBUS_SSPP1, 20, 5 },
468 { DBGBUS_SSPP1, 20, 6 },
469 { DBGBUS_SSPP1, 20, 7 },
470
471 { DBGBUS_SSPP1, 21, 0 },
472 { DBGBUS_SSPP1, 21, 1 },
473 { DBGBUS_SSPP1, 21, 2 },
474 { DBGBUS_SSPP1, 21, 3 },
475 { DBGBUS_SSPP1, 21, 4 },
476 { DBGBUS_SSPP1, 21, 5 },
477 { DBGBUS_SSPP1, 21, 6 },
478 { DBGBUS_SSPP1, 21, 7 },
479
480 { DBGBUS_SSPP1, 22, 0 },
481 { DBGBUS_SSPP1, 22, 1 },
482 { DBGBUS_SSPP1, 22, 2 },
483 { DBGBUS_SSPP1, 22, 3 },
484 { DBGBUS_SSPP1, 22, 4 },
485 { DBGBUS_SSPP1, 22, 5 },
486 { DBGBUS_SSPP1, 22, 6 },
487 { DBGBUS_SSPP1, 22, 7 },
488
489 { DBGBUS_SSPP1, 24, 0 },
490 { DBGBUS_SSPP1, 24, 1 },
491 { DBGBUS_SSPP1, 24, 2 },
492 { DBGBUS_SSPP1, 24, 3 },
493 { DBGBUS_SSPP1, 24, 4 },
494 { DBGBUS_SSPP1, 24, 5 },
495 { DBGBUS_SSPP1, 24, 6 },
496 { DBGBUS_SSPP1, 24, 7 },
497
498 { DBGBUS_SSPP1, 25, 0 },
499 { DBGBUS_SSPP1, 25, 1 },
500 { DBGBUS_SSPP1, 25, 2 },
501 { DBGBUS_SSPP1, 25, 3 },
502 { DBGBUS_SSPP1, 25, 4 },
503 { DBGBUS_SSPP1, 25, 5 },
504 { DBGBUS_SSPP1, 25, 6 },
505 { DBGBUS_SSPP1, 25, 7 },
506
507 /* dma 3 */
508 { DBGBUS_SSPP1, 30, 0 },
509 { DBGBUS_SSPP1, 30, 1 },
510 { DBGBUS_SSPP1, 30, 2 },
511 { DBGBUS_SSPP1, 30, 3 },
512 { DBGBUS_SSPP1, 30, 4 },
513 { DBGBUS_SSPP1, 30, 5 },
514 { DBGBUS_SSPP1, 30, 6 },
515 { DBGBUS_SSPP1, 30, 7 },
516
517 { DBGBUS_SSPP1, 31, 0 },
518 { DBGBUS_SSPP1, 31, 1 },
519 { DBGBUS_SSPP1, 31, 2 },
520 { DBGBUS_SSPP1, 31, 3 },
521 { DBGBUS_SSPP1, 31, 4 },
522 { DBGBUS_SSPP1, 31, 5 },
523 { DBGBUS_SSPP1, 31, 6 },
524 { DBGBUS_SSPP1, 31, 7 },
525
526 { DBGBUS_SSPP1, 32, 0 },
527 { DBGBUS_SSPP1, 32, 1 },
528 { DBGBUS_SSPP1, 32, 2 },
529 { DBGBUS_SSPP1, 32, 3 },
530 { DBGBUS_SSPP1, 32, 4 },
531 { DBGBUS_SSPP1, 32, 5 },
532 { DBGBUS_SSPP1, 32, 6 },
533 { DBGBUS_SSPP1, 32, 7 },
534
535 { DBGBUS_SSPP1, 33, 0 },
536 { DBGBUS_SSPP1, 33, 1 },
537 { DBGBUS_SSPP1, 33, 2 },
538 { DBGBUS_SSPP1, 33, 3 },
539 { DBGBUS_SSPP1, 33, 4 },
540 { DBGBUS_SSPP1, 33, 5 },
541 { DBGBUS_SSPP1, 33, 6 },
542 { DBGBUS_SSPP1, 33, 7 },
543
544 { DBGBUS_SSPP1, 34, 0 },
545 { DBGBUS_SSPP1, 34, 1 },
546 { DBGBUS_SSPP1, 34, 2 },
547 { DBGBUS_SSPP1, 34, 3 },
548 { DBGBUS_SSPP1, 34, 4 },
549 { DBGBUS_SSPP1, 34, 5 },
550 { DBGBUS_SSPP1, 34, 6 },
551 { DBGBUS_SSPP1, 34, 7 },
552
553 { DBGBUS_SSPP1, 35, 0 },
554 { DBGBUS_SSPP1, 35, 1 },
555 { DBGBUS_SSPP1, 35, 2 },
556
557 /* dma 1 */
558 { DBGBUS_SSPP1, 40, 0 },
559 { DBGBUS_SSPP1, 40, 1 },
560 { DBGBUS_SSPP1, 40, 2 },
561 { DBGBUS_SSPP1, 40, 3 },
562 { DBGBUS_SSPP1, 40, 4 },
563 { DBGBUS_SSPP1, 40, 5 },
564 { DBGBUS_SSPP1, 40, 6 },
565 { DBGBUS_SSPP1, 40, 7 },
566
567 { DBGBUS_SSPP1, 41, 0 },
568 { DBGBUS_SSPP1, 41, 1 },
569 { DBGBUS_SSPP1, 41, 2 },
570 { DBGBUS_SSPP1, 41, 3 },
571 { DBGBUS_SSPP1, 41, 4 },
572 { DBGBUS_SSPP1, 41, 5 },
573 { DBGBUS_SSPP1, 41, 6 },
574 { DBGBUS_SSPP1, 41, 7 },
575
576 { DBGBUS_SSPP1, 42, 0 },
577 { DBGBUS_SSPP1, 42, 1 },
578 { DBGBUS_SSPP1, 42, 2 },
579 { DBGBUS_SSPP1, 42, 3 },
580 { DBGBUS_SSPP1, 42, 4 },
581 { DBGBUS_SSPP1, 42, 5 },
582 { DBGBUS_SSPP1, 42, 6 },
583 { DBGBUS_SSPP1, 42, 7 },
584
585 { DBGBUS_SSPP1, 44, 0 },
586 { DBGBUS_SSPP1, 44, 1 },
587 { DBGBUS_SSPP1, 44, 2 },
588 { DBGBUS_SSPP1, 44, 3 },
589 { DBGBUS_SSPP1, 44, 4 },
590 { DBGBUS_SSPP1, 44, 5 },
591 { DBGBUS_SSPP1, 44, 6 },
592 { DBGBUS_SSPP1, 44, 7 },
593
594 { DBGBUS_SSPP1, 45, 0 },
595 { DBGBUS_SSPP1, 45, 1 },
596 { DBGBUS_SSPP1, 45, 2 },
597 { DBGBUS_SSPP1, 45, 3 },
598 { DBGBUS_SSPP1, 45, 4 },
599 { DBGBUS_SSPP1, 45, 5 },
600 { DBGBUS_SSPP1, 45, 6 },
601 { DBGBUS_SSPP1, 45, 7 },
602
603 /* cursor 1 */
604 { DBGBUS_SSPP1, 80, 0 },
605 { DBGBUS_SSPP1, 80, 1 },
606 { DBGBUS_SSPP1, 80, 2 },
607 { DBGBUS_SSPP1, 80, 3 },
608 { DBGBUS_SSPP1, 80, 4 },
609 { DBGBUS_SSPP1, 80, 5 },
610 { DBGBUS_SSPP1, 80, 6 },
611 { DBGBUS_SSPP1, 80, 7 },
612
613 { DBGBUS_SSPP1, 81, 0 },
614 { DBGBUS_SSPP1, 81, 1 },
615 { DBGBUS_SSPP1, 81, 2 },
616 { DBGBUS_SSPP1, 81, 3 },
617 { DBGBUS_SSPP1, 81, 4 },
618 { DBGBUS_SSPP1, 81, 5 },
619 { DBGBUS_SSPP1, 81, 6 },
620 { DBGBUS_SSPP1, 81, 7 },
621
622 { DBGBUS_SSPP1, 82, 0 },
623 { DBGBUS_SSPP1, 82, 1 },
624 { DBGBUS_SSPP1, 82, 2 },
625 { DBGBUS_SSPP1, 82, 3 },
626 { DBGBUS_SSPP1, 82, 4 },
627 { DBGBUS_SSPP1, 82, 5 },
628 { DBGBUS_SSPP1, 82, 6 },
629 { DBGBUS_SSPP1, 82, 7 },
630
631 { DBGBUS_SSPP1, 83, 0 },
632 { DBGBUS_SSPP1, 83, 1 },
633 { DBGBUS_SSPP1, 83, 2 },
634 { DBGBUS_SSPP1, 83, 3 },
635 { DBGBUS_SSPP1, 83, 4 },
636 { DBGBUS_SSPP1, 83, 5 },
637 { DBGBUS_SSPP1, 83, 6 },
638 { DBGBUS_SSPP1, 83, 7 },
639
640 { DBGBUS_SSPP1, 84, 0 },
641 { DBGBUS_SSPP1, 84, 1 },
642 { DBGBUS_SSPP1, 84, 2 },
643 { DBGBUS_SSPP1, 84, 3 },
644 { DBGBUS_SSPP1, 84, 4 },
645 { DBGBUS_SSPP1, 84, 5 },
646 { DBGBUS_SSPP1, 84, 6 },
647 { DBGBUS_SSPP1, 84, 7 },
648
649 /* dspp */
650 { DBGBUS_DSPP, 13, 0 },
651 { DBGBUS_DSPP, 19, 0 },
652 { DBGBUS_DSPP, 14, 0 },
653 { DBGBUS_DSPP, 14, 1 },
654 { DBGBUS_DSPP, 14, 3 },
655 { DBGBUS_DSPP, 20, 0 },
656 { DBGBUS_DSPP, 20, 1 },
657 { DBGBUS_DSPP, 20, 3 },
658
659 /* ppb_0 */
660 { DBGBUS_DSPP, 31, 0, _dpu_debug_bus_ppb0_dump },
661 { DBGBUS_DSPP, 33, 0, _dpu_debug_bus_ppb0_dump },
662 { DBGBUS_DSPP, 35, 0, _dpu_debug_bus_ppb0_dump },
663 { DBGBUS_DSPP, 42, 0, _dpu_debug_bus_ppb0_dump },
664
665 /* ppb_1 */
666 { DBGBUS_DSPP, 32, 0, _dpu_debug_bus_ppb1_dump },
667 { DBGBUS_DSPP, 34, 0, _dpu_debug_bus_ppb1_dump },
668 { DBGBUS_DSPP, 36, 0, _dpu_debug_bus_ppb1_dump },
669 { DBGBUS_DSPP, 43, 0, _dpu_debug_bus_ppb1_dump },
670
671 /* lm_lut */
672 { DBGBUS_DSPP, 109, 0 },
673 { DBGBUS_DSPP, 105, 0 },
674 { DBGBUS_DSPP, 103, 0 },
675
676 /* tear-check */
677 { DBGBUS_PERIPH, 63, 0 },
678 { DBGBUS_PERIPH, 64, 0 },
679 { DBGBUS_PERIPH, 65, 0 },
680 { DBGBUS_PERIPH, 73, 0 },
681 { DBGBUS_PERIPH, 74, 0 },
682
683 /* crossbar */
684 { DBGBUS_DSPP, 0, 0, _dpu_debug_bus_xbar_dump },
685
686 /* rotator */
687 { DBGBUS_DSPP, 9, 0},
688
689 /* blend */
690 /* LM0 */
691 { DBGBUS_DSPP, 63, 0},
692 { DBGBUS_DSPP, 63, 1},
693 { DBGBUS_DSPP, 63, 2},
694 { DBGBUS_DSPP, 63, 3},
695 { DBGBUS_DSPP, 63, 4},
696 { DBGBUS_DSPP, 63, 5},
697 { DBGBUS_DSPP, 63, 6},
698 { DBGBUS_DSPP, 63, 7, _dpu_debug_bus_lm_dump },
699
700 { DBGBUS_DSPP, 64, 0},
701 { DBGBUS_DSPP, 64, 1},
702 { DBGBUS_DSPP, 64, 2},
703 { DBGBUS_DSPP, 64, 3},
704 { DBGBUS_DSPP, 64, 4},
705 { DBGBUS_DSPP, 64, 5},
706 { DBGBUS_DSPP, 64, 6},
707 { DBGBUS_DSPP, 64, 7, _dpu_debug_bus_lm_dump },
708
709 { DBGBUS_DSPP, 65, 0},
710 { DBGBUS_DSPP, 65, 1},
711 { DBGBUS_DSPP, 65, 2},
712 { DBGBUS_DSPP, 65, 3},
713 { DBGBUS_DSPP, 65, 4},
714 { DBGBUS_DSPP, 65, 5},
715 { DBGBUS_DSPP, 65, 6},
716 { DBGBUS_DSPP, 65, 7, _dpu_debug_bus_lm_dump },
717
718 { DBGBUS_DSPP, 66, 0},
719 { DBGBUS_DSPP, 66, 1},
720 { DBGBUS_DSPP, 66, 2},
721 { DBGBUS_DSPP, 66, 3},
722 { DBGBUS_DSPP, 66, 4},
723 { DBGBUS_DSPP, 66, 5},
724 { DBGBUS_DSPP, 66, 6},
725 { DBGBUS_DSPP, 66, 7, _dpu_debug_bus_lm_dump },
726
727 { DBGBUS_DSPP, 67, 0},
728 { DBGBUS_DSPP, 67, 1},
729 { DBGBUS_DSPP, 67, 2},
730 { DBGBUS_DSPP, 67, 3},
731 { DBGBUS_DSPP, 67, 4},
732 { DBGBUS_DSPP, 67, 5},
733 { DBGBUS_DSPP, 67, 6},
734 { DBGBUS_DSPP, 67, 7, _dpu_debug_bus_lm_dump },
735
736 { DBGBUS_DSPP, 68, 0},
737 { DBGBUS_DSPP, 68, 1},
738 { DBGBUS_DSPP, 68, 2},
739 { DBGBUS_DSPP, 68, 3},
740 { DBGBUS_DSPP, 68, 4},
741 { DBGBUS_DSPP, 68, 5},
742 { DBGBUS_DSPP, 68, 6},
743 { DBGBUS_DSPP, 68, 7, _dpu_debug_bus_lm_dump },
744
745 { DBGBUS_DSPP, 69, 0},
746 { DBGBUS_DSPP, 69, 1},
747 { DBGBUS_DSPP, 69, 2},
748 { DBGBUS_DSPP, 69, 3},
749 { DBGBUS_DSPP, 69, 4},
750 { DBGBUS_DSPP, 69, 5},
751 { DBGBUS_DSPP, 69, 6},
752 { DBGBUS_DSPP, 69, 7, _dpu_debug_bus_lm_dump },
753
754 /* LM1 */
755 { DBGBUS_DSPP, 70, 0},
756 { DBGBUS_DSPP, 70, 1},
757 { DBGBUS_DSPP, 70, 2},
758 { DBGBUS_DSPP, 70, 3},
759 { DBGBUS_DSPP, 70, 4},
760 { DBGBUS_DSPP, 70, 5},
761 { DBGBUS_DSPP, 70, 6},
762 { DBGBUS_DSPP, 70, 7, _dpu_debug_bus_lm_dump },
763
764 { DBGBUS_DSPP, 71, 0},
765 { DBGBUS_DSPP, 71, 1},
766 { DBGBUS_DSPP, 71, 2},
767 { DBGBUS_DSPP, 71, 3},
768 { DBGBUS_DSPP, 71, 4},
769 { DBGBUS_DSPP, 71, 5},
770 { DBGBUS_DSPP, 71, 6},
771 { DBGBUS_DSPP, 71, 7, _dpu_debug_bus_lm_dump },
772
773 { DBGBUS_DSPP, 72, 0},
774 { DBGBUS_DSPP, 72, 1},
775 { DBGBUS_DSPP, 72, 2},
776 { DBGBUS_DSPP, 72, 3},
777 { DBGBUS_DSPP, 72, 4},
778 { DBGBUS_DSPP, 72, 5},
779 { DBGBUS_DSPP, 72, 6},
780 { DBGBUS_DSPP, 72, 7, _dpu_debug_bus_lm_dump },
781
782 { DBGBUS_DSPP, 73, 0},
783 { DBGBUS_DSPP, 73, 1},
784 { DBGBUS_DSPP, 73, 2},
785 { DBGBUS_DSPP, 73, 3},
786 { DBGBUS_DSPP, 73, 4},
787 { DBGBUS_DSPP, 73, 5},
788 { DBGBUS_DSPP, 73, 6},
789 { DBGBUS_DSPP, 73, 7, _dpu_debug_bus_lm_dump },
790
791 { DBGBUS_DSPP, 74, 0},
792 { DBGBUS_DSPP, 74, 1},
793 { DBGBUS_DSPP, 74, 2},
794 { DBGBUS_DSPP, 74, 3},
795 { DBGBUS_DSPP, 74, 4},
796 { DBGBUS_DSPP, 74, 5},
797 { DBGBUS_DSPP, 74, 6},
798 { DBGBUS_DSPP, 74, 7, _dpu_debug_bus_lm_dump },
799
800 { DBGBUS_DSPP, 75, 0},
801 { DBGBUS_DSPP, 75, 1},
802 { DBGBUS_DSPP, 75, 2},
803 { DBGBUS_DSPP, 75, 3},
804 { DBGBUS_DSPP, 75, 4},
805 { DBGBUS_DSPP, 75, 5},
806 { DBGBUS_DSPP, 75, 6},
807 { DBGBUS_DSPP, 75, 7, _dpu_debug_bus_lm_dump },
808
809 { DBGBUS_DSPP, 76, 0},
810 { DBGBUS_DSPP, 76, 1},
811 { DBGBUS_DSPP, 76, 2},
812 { DBGBUS_DSPP, 76, 3},
813 { DBGBUS_DSPP, 76, 4},
814 { DBGBUS_DSPP, 76, 5},
815 { DBGBUS_DSPP, 76, 6},
816 { DBGBUS_DSPP, 76, 7, _dpu_debug_bus_lm_dump },
817
818 /* LM2 */
819 { DBGBUS_DSPP, 77, 0},
820 { DBGBUS_DSPP, 77, 1},
821 { DBGBUS_DSPP, 77, 2},
822 { DBGBUS_DSPP, 77, 3},
823 { DBGBUS_DSPP, 77, 4},
824 { DBGBUS_DSPP, 77, 5},
825 { DBGBUS_DSPP, 77, 6},
826 { DBGBUS_DSPP, 77, 7, _dpu_debug_bus_lm_dump },
827
828 { DBGBUS_DSPP, 78, 0},
829 { DBGBUS_DSPP, 78, 1},
830 { DBGBUS_DSPP, 78, 2},
831 { DBGBUS_DSPP, 78, 3},
832 { DBGBUS_DSPP, 78, 4},
833 { DBGBUS_DSPP, 78, 5},
834 { DBGBUS_DSPP, 78, 6},
835 { DBGBUS_DSPP, 78, 7, _dpu_debug_bus_lm_dump },
836
837 { DBGBUS_DSPP, 79, 0},
838 { DBGBUS_DSPP, 79, 1},
839 { DBGBUS_DSPP, 79, 2},
840 { DBGBUS_DSPP, 79, 3},
841 { DBGBUS_DSPP, 79, 4},
842 { DBGBUS_DSPP, 79, 5},
843 { DBGBUS_DSPP, 79, 6},
844 { DBGBUS_DSPP, 79, 7, _dpu_debug_bus_lm_dump },
845
846 { DBGBUS_DSPP, 80, 0},
847 { DBGBUS_DSPP, 80, 1},
848 { DBGBUS_DSPP, 80, 2},
849 { DBGBUS_DSPP, 80, 3},
850 { DBGBUS_DSPP, 80, 4},
851 { DBGBUS_DSPP, 80, 5},
852 { DBGBUS_DSPP, 80, 6},
853 { DBGBUS_DSPP, 80, 7, _dpu_debug_bus_lm_dump },
854
855 { DBGBUS_DSPP, 81, 0},
856 { DBGBUS_DSPP, 81, 1},
857 { DBGBUS_DSPP, 81, 2},
858 { DBGBUS_DSPP, 81, 3},
859 { DBGBUS_DSPP, 81, 4},
860 { DBGBUS_DSPP, 81, 5},
861 { DBGBUS_DSPP, 81, 6},
862 { DBGBUS_DSPP, 81, 7, _dpu_debug_bus_lm_dump },
863
864 { DBGBUS_DSPP, 82, 0},
865 { DBGBUS_DSPP, 82, 1},
866 { DBGBUS_DSPP, 82, 2},
867 { DBGBUS_DSPP, 82, 3},
868 { DBGBUS_DSPP, 82, 4},
869 { DBGBUS_DSPP, 82, 5},
870 { DBGBUS_DSPP, 82, 6},
871 { DBGBUS_DSPP, 82, 7, _dpu_debug_bus_lm_dump },
872
873 { DBGBUS_DSPP, 83, 0},
874 { DBGBUS_DSPP, 83, 1},
875 { DBGBUS_DSPP, 83, 2},
876 { DBGBUS_DSPP, 83, 3},
877 { DBGBUS_DSPP, 83, 4},
878 { DBGBUS_DSPP, 83, 5},
879 { DBGBUS_DSPP, 83, 6},
880 { DBGBUS_DSPP, 83, 7, _dpu_debug_bus_lm_dump },
881
882 /* csc */
883 { DBGBUS_SSPP0, 7, 0},
884 { DBGBUS_SSPP0, 7, 1},
885 { DBGBUS_SSPP0, 27, 0},
886 { DBGBUS_SSPP0, 27, 1},
887 { DBGBUS_SSPP1, 7, 0},
888 { DBGBUS_SSPP1, 7, 1},
889 { DBGBUS_SSPP1, 27, 0},
890 { DBGBUS_SSPP1, 27, 1},
891
892 /* pcc */
893 { DBGBUS_SSPP0, 3, 3},
894 { DBGBUS_SSPP0, 23, 3},
895 { DBGBUS_SSPP0, 33, 3},
896 { DBGBUS_SSPP0, 43, 3},
897 { DBGBUS_SSPP1, 3, 3},
898 { DBGBUS_SSPP1, 23, 3},
899 { DBGBUS_SSPP1, 33, 3},
900 { DBGBUS_SSPP1, 43, 3},
901
902 /* spa */
903 { DBGBUS_SSPP0, 8, 0},
904 { DBGBUS_SSPP0, 28, 0},
905 { DBGBUS_SSPP1, 8, 0},
906 { DBGBUS_SSPP1, 28, 0},
907 { DBGBUS_DSPP, 13, 0},
908 { DBGBUS_DSPP, 19, 0},
909
910 /* igc */
911 { DBGBUS_SSPP0, 9, 0},
912 { DBGBUS_SSPP0, 9, 1},
913 { DBGBUS_SSPP0, 9, 3},
914 { DBGBUS_SSPP0, 29, 0},
915 { DBGBUS_SSPP0, 29, 1},
916 { DBGBUS_SSPP0, 29, 3},
917 { DBGBUS_SSPP0, 17, 0},
918 { DBGBUS_SSPP0, 17, 1},
919 { DBGBUS_SSPP0, 17, 3},
920 { DBGBUS_SSPP0, 37, 0},
921 { DBGBUS_SSPP0, 37, 1},
922 { DBGBUS_SSPP0, 37, 3},
923 { DBGBUS_SSPP0, 46, 0},
924 { DBGBUS_SSPP0, 46, 1},
925 { DBGBUS_SSPP0, 46, 3},
926
927 { DBGBUS_SSPP1, 9, 0},
928 { DBGBUS_SSPP1, 9, 1},
929 { DBGBUS_SSPP1, 9, 3},
930 { DBGBUS_SSPP1, 29, 0},
931 { DBGBUS_SSPP1, 29, 1},
932 { DBGBUS_SSPP1, 29, 3},
933 { DBGBUS_SSPP1, 17, 0},
934 { DBGBUS_SSPP1, 17, 1},
935 { DBGBUS_SSPP1, 17, 3},
936 { DBGBUS_SSPP1, 37, 0},
937 { DBGBUS_SSPP1, 37, 1},
938 { DBGBUS_SSPP1, 37, 3},
939 { DBGBUS_SSPP1, 46, 0},
940 { DBGBUS_SSPP1, 46, 1},
941 { DBGBUS_SSPP1, 46, 3},
942
943 { DBGBUS_DSPP, 14, 0},
944 { DBGBUS_DSPP, 14, 1},
945 { DBGBUS_DSPP, 14, 3},
946 { DBGBUS_DSPP, 20, 0},
947 { DBGBUS_DSPP, 20, 1},
948 { DBGBUS_DSPP, 20, 3},
949
950 { DBGBUS_PERIPH, 60, 0},
951 };
952
953 static struct dpu_debug_bus_entry dbg_bus_dpu_sdm845[] = {
954
955 /* Unpack 0 sspp 0*/
956 { DBGBUS_SSPP0, 50, 2 },
957 { DBGBUS_SSPP0, 60, 2 },
958 { DBGBUS_SSPP0, 70, 2 },
959
960 /* Upack 0 sspp 1*/
961 { DBGBUS_SSPP1, 50, 2 },
962 { DBGBUS_SSPP1, 60, 2 },
963 { DBGBUS_SSPP1, 70, 2 },
964
965 /* scheduler */
966 { DBGBUS_DSPP, 130, 0 },
967 { DBGBUS_DSPP, 130, 1 },
968 { DBGBUS_DSPP, 130, 2 },
969 { DBGBUS_DSPP, 130, 3 },
970 { DBGBUS_DSPP, 130, 4 },
971 { DBGBUS_DSPP, 130, 5 },
972
973 /* qseed */
974 { DBGBUS_SSPP0, 6, 0},
975 { DBGBUS_SSPP0, 6, 1},
976 { DBGBUS_SSPP0, 26, 0},
977 { DBGBUS_SSPP0, 26, 1},
978 { DBGBUS_SSPP1, 6, 0},
979 { DBGBUS_SSPP1, 6, 1},
980 { DBGBUS_SSPP1, 26, 0},
981 { DBGBUS_SSPP1, 26, 1},
982
983 /* scale */
984 { DBGBUS_SSPP0, 16, 0},
985 { DBGBUS_SSPP0, 16, 1},
986 { DBGBUS_SSPP0, 36, 0},
987 { DBGBUS_SSPP0, 36, 1},
988 { DBGBUS_SSPP1, 16, 0},
989 { DBGBUS_SSPP1, 16, 1},
990 { DBGBUS_SSPP1, 36, 0},
991 { DBGBUS_SSPP1, 36, 1},
992
993 /* fetch sspp0 */
994
995 /* vig 0 */
996 { DBGBUS_SSPP0, 0, 0 },
997 { DBGBUS_SSPP0, 0, 1 },
998 { DBGBUS_SSPP0, 0, 2 },
999 { DBGBUS_SSPP0, 0, 3 },
1000 { DBGBUS_SSPP0, 0, 4 },
1001 { DBGBUS_SSPP0, 0, 5 },
1002 { DBGBUS_SSPP0, 0, 6 },
1003 { DBGBUS_SSPP0, 0, 7 },
1004
1005 { DBGBUS_SSPP0, 1, 0 },
1006 { DBGBUS_SSPP0, 1, 1 },
1007 { DBGBUS_SSPP0, 1, 2 },
1008 { DBGBUS_SSPP0, 1, 3 },
1009 { DBGBUS_SSPP0, 1, 4 },
1010 { DBGBUS_SSPP0, 1, 5 },
1011 { DBGBUS_SSPP0, 1, 6 },
1012 { DBGBUS_SSPP0, 1, 7 },
1013
1014 { DBGBUS_SSPP0, 2, 0 },
1015 { DBGBUS_SSPP0, 2, 1 },
1016 { DBGBUS_SSPP0, 2, 2 },
1017 { DBGBUS_SSPP0, 2, 3 },
1018 { DBGBUS_SSPP0, 2, 4 },
1019 { DBGBUS_SSPP0, 2, 5 },
1020 { DBGBUS_SSPP0, 2, 6 },
1021 { DBGBUS_SSPP0, 2, 7 },
1022
1023 { DBGBUS_SSPP0, 4, 0 },
1024 { DBGBUS_SSPP0, 4, 1 },
1025 { DBGBUS_SSPP0, 4, 2 },
1026 { DBGBUS_SSPP0, 4, 3 },
1027 { DBGBUS_SSPP0, 4, 4 },
1028 { DBGBUS_SSPP0, 4, 5 },
1029 { DBGBUS_SSPP0, 4, 6 },
1030 { DBGBUS_SSPP0, 4, 7 },
1031
1032 { DBGBUS_SSPP0, 5, 0 },
1033 { DBGBUS_SSPP0, 5, 1 },
1034 { DBGBUS_SSPP0, 5, 2 },
1035 { DBGBUS_SSPP0, 5, 3 },
1036 { DBGBUS_SSPP0, 5, 4 },
1037 { DBGBUS_SSPP0, 5, 5 },
1038 { DBGBUS_SSPP0, 5, 6 },
1039 { DBGBUS_SSPP0, 5, 7 },
1040
1041 /* vig 2 */
1042 { DBGBUS_SSPP0, 20, 0 },
1043 { DBGBUS_SSPP0, 20, 1 },
1044 { DBGBUS_SSPP0, 20, 2 },
1045 { DBGBUS_SSPP0, 20, 3 },
1046 { DBGBUS_SSPP0, 20, 4 },
1047 { DBGBUS_SSPP0, 20, 5 },
1048 { DBGBUS_SSPP0, 20, 6 },
1049 { DBGBUS_SSPP0, 20, 7 },
1050
1051 { DBGBUS_SSPP0, 21, 0 },
1052 { DBGBUS_SSPP0, 21, 1 },
1053 { DBGBUS_SSPP0, 21, 2 },
1054 { DBGBUS_SSPP0, 21, 3 },
1055 { DBGBUS_SSPP0, 21, 4 },
1056 { DBGBUS_SSPP0, 21, 5 },
1057 { DBGBUS_SSPP0, 21, 6 },
1058 { DBGBUS_SSPP0, 21, 7 },
1059
1060 { DBGBUS_SSPP0, 22, 0 },
1061 { DBGBUS_SSPP0, 22, 1 },
1062 { DBGBUS_SSPP0, 22, 2 },
1063 { DBGBUS_SSPP0, 22, 3 },
1064 { DBGBUS_SSPP0, 22, 4 },
1065 { DBGBUS_SSPP0, 22, 5 },
1066 { DBGBUS_SSPP0, 22, 6 },
1067 { DBGBUS_SSPP0, 22, 7 },
1068
1069 { DBGBUS_SSPP0, 24, 0 },
1070 { DBGBUS_SSPP0, 24, 1 },
1071 { DBGBUS_SSPP0, 24, 2 },
1072 { DBGBUS_SSPP0, 24, 3 },
1073 { DBGBUS_SSPP0, 24, 4 },
1074 { DBGBUS_SSPP0, 24, 5 },
1075 { DBGBUS_SSPP0, 24, 6 },
1076 { DBGBUS_SSPP0, 24, 7 },
1077
1078 { DBGBUS_SSPP0, 25, 0 },
1079 { DBGBUS_SSPP0, 25, 1 },
1080 { DBGBUS_SSPP0, 25, 2 },
1081 { DBGBUS_SSPP0, 25, 3 },
1082 { DBGBUS_SSPP0, 25, 4 },
1083 { DBGBUS_SSPP0, 25, 5 },
1084 { DBGBUS_SSPP0, 25, 6 },
1085 { DBGBUS_SSPP0, 25, 7 },
1086
1087 /* dma 2 */
1088 { DBGBUS_SSPP0, 30, 0 },
1089 { DBGBUS_SSPP0, 30, 1 },
1090 { DBGBUS_SSPP0, 30, 2 },
1091 { DBGBUS_SSPP0, 30, 3 },
1092 { DBGBUS_SSPP0, 30, 4 },
1093 { DBGBUS_SSPP0, 30, 5 },
1094 { DBGBUS_SSPP0, 30, 6 },
1095 { DBGBUS_SSPP0, 30, 7 },
1096
1097 { DBGBUS_SSPP0, 31, 0 },
1098 { DBGBUS_SSPP0, 31, 1 },
1099 { DBGBUS_SSPP0, 31, 2 },
1100 { DBGBUS_SSPP0, 31, 3 },
1101 { DBGBUS_SSPP0, 31, 4 },
1102 { DBGBUS_SSPP0, 31, 5 },
1103 { DBGBUS_SSPP0, 31, 6 },
1104 { DBGBUS_SSPP0, 31, 7 },
1105
1106 { DBGBUS_SSPP0, 32, 0 },
1107 { DBGBUS_SSPP0, 32, 1 },
1108 { DBGBUS_SSPP0, 32, 2 },
1109 { DBGBUS_SSPP0, 32, 3 },
1110 { DBGBUS_SSPP0, 32, 4 },
1111 { DBGBUS_SSPP0, 32, 5 },
1112 { DBGBUS_SSPP0, 32, 6 },
1113 { DBGBUS_SSPP0, 32, 7 },
1114
1115 { DBGBUS_SSPP0, 33, 0 },
1116 { DBGBUS_SSPP0, 33, 1 },
1117 { DBGBUS_SSPP0, 33, 2 },
1118 { DBGBUS_SSPP0, 33, 3 },
1119 { DBGBUS_SSPP0, 33, 4 },
1120 { DBGBUS_SSPP0, 33, 5 },
1121 { DBGBUS_SSPP0, 33, 6 },
1122 { DBGBUS_SSPP0, 33, 7 },
1123
1124 { DBGBUS_SSPP0, 34, 0 },
1125 { DBGBUS_SSPP0, 34, 1 },
1126 { DBGBUS_SSPP0, 34, 2 },
1127 { DBGBUS_SSPP0, 34, 3 },
1128 { DBGBUS_SSPP0, 34, 4 },
1129 { DBGBUS_SSPP0, 34, 5 },
1130 { DBGBUS_SSPP0, 34, 6 },
1131 { DBGBUS_SSPP0, 34, 7 },
1132
1133 { DBGBUS_SSPP0, 35, 0 },
1134 { DBGBUS_SSPP0, 35, 1 },
1135 { DBGBUS_SSPP0, 35, 2 },
1136 { DBGBUS_SSPP0, 35, 3 },
1137
1138 /* dma 0 */
1139 { DBGBUS_SSPP0, 40, 0 },
1140 { DBGBUS_SSPP0, 40, 1 },
1141 { DBGBUS_SSPP0, 40, 2 },
1142 { DBGBUS_SSPP0, 40, 3 },
1143 { DBGBUS_SSPP0, 40, 4 },
1144 { DBGBUS_SSPP0, 40, 5 },
1145 { DBGBUS_SSPP0, 40, 6 },
1146 { DBGBUS_SSPP0, 40, 7 },
1147
1148 { DBGBUS_SSPP0, 41, 0 },
1149 { DBGBUS_SSPP0, 41, 1 },
1150 { DBGBUS_SSPP0, 41, 2 },
1151 { DBGBUS_SSPP0, 41, 3 },
1152 { DBGBUS_SSPP0, 41, 4 },
1153 { DBGBUS_SSPP0, 41, 5 },
1154 { DBGBUS_SSPP0, 41, 6 },
1155 { DBGBUS_SSPP0, 41, 7 },
1156
1157 { DBGBUS_SSPP0, 42, 0 },
1158 { DBGBUS_SSPP0, 42, 1 },
1159 { DBGBUS_SSPP0, 42, 2 },
1160 { DBGBUS_SSPP0, 42, 3 },
1161 { DBGBUS_SSPP0, 42, 4 },
1162 { DBGBUS_SSPP0, 42, 5 },
1163 { DBGBUS_SSPP0, 42, 6 },
1164 { DBGBUS_SSPP0, 42, 7 },
1165
1166 { DBGBUS_SSPP0, 44, 0 },
1167 { DBGBUS_SSPP0, 44, 1 },
1168 { DBGBUS_SSPP0, 44, 2 },
1169 { DBGBUS_SSPP0, 44, 3 },
1170 { DBGBUS_SSPP0, 44, 4 },
1171 { DBGBUS_SSPP0, 44, 5 },
1172 { DBGBUS_SSPP0, 44, 6 },
1173 { DBGBUS_SSPP0, 44, 7 },
1174
1175 { DBGBUS_SSPP0, 45, 0 },
1176 { DBGBUS_SSPP0, 45, 1 },
1177 { DBGBUS_SSPP0, 45, 2 },
1178 { DBGBUS_SSPP0, 45, 3 },
1179 { DBGBUS_SSPP0, 45, 4 },
1180 { DBGBUS_SSPP0, 45, 5 },
1181 { DBGBUS_SSPP0, 45, 6 },
1182 { DBGBUS_SSPP0, 45, 7 },
1183
1184 /* fetch sspp1 */
1185 /* vig 1 */
1186 { DBGBUS_SSPP1, 0, 0 },
1187 { DBGBUS_SSPP1, 0, 1 },
1188 { DBGBUS_SSPP1, 0, 2 },
1189 { DBGBUS_SSPP1, 0, 3 },
1190 { DBGBUS_SSPP1, 0, 4 },
1191 { DBGBUS_SSPP1, 0, 5 },
1192 { DBGBUS_SSPP1, 0, 6 },
1193 { DBGBUS_SSPP1, 0, 7 },
1194
1195 { DBGBUS_SSPP1, 1, 0 },
1196 { DBGBUS_SSPP1, 1, 1 },
1197 { DBGBUS_SSPP1, 1, 2 },
1198 { DBGBUS_SSPP1, 1, 3 },
1199 { DBGBUS_SSPP1, 1, 4 },
1200 { DBGBUS_SSPP1, 1, 5 },
1201 { DBGBUS_SSPP1, 1, 6 },
1202 { DBGBUS_SSPP1, 1, 7 },
1203
1204 { DBGBUS_SSPP1, 2, 0 },
1205 { DBGBUS_SSPP1, 2, 1 },
1206 { DBGBUS_SSPP1, 2, 2 },
1207 { DBGBUS_SSPP1, 2, 3 },
1208 { DBGBUS_SSPP1, 2, 4 },
1209 { DBGBUS_SSPP1, 2, 5 },
1210 { DBGBUS_SSPP1, 2, 6 },
1211 { DBGBUS_SSPP1, 2, 7 },
1212
1213 { DBGBUS_SSPP1, 4, 0 },
1214 { DBGBUS_SSPP1, 4, 1 },
1215 { DBGBUS_SSPP1, 4, 2 },
1216 { DBGBUS_SSPP1, 4, 3 },
1217 { DBGBUS_SSPP1, 4, 4 },
1218 { DBGBUS_SSPP1, 4, 5 },
1219 { DBGBUS_SSPP1, 4, 6 },
1220 { DBGBUS_SSPP1, 4, 7 },
1221
1222 { DBGBUS_SSPP1, 5, 0 },
1223 { DBGBUS_SSPP1, 5, 1 },
1224 { DBGBUS_SSPP1, 5, 2 },
1225 { DBGBUS_SSPP1, 5, 3 },
1226 { DBGBUS_SSPP1, 5, 4 },
1227 { DBGBUS_SSPP1, 5, 5 },
1228 { DBGBUS_SSPP1, 5, 6 },
1229 { DBGBUS_SSPP1, 5, 7 },
1230
1231 /* vig 3 */
1232 { DBGBUS_SSPP1, 20, 0 },
1233 { DBGBUS_SSPP1, 20, 1 },
1234 { DBGBUS_SSPP1, 20, 2 },
1235 { DBGBUS_SSPP1, 20, 3 },
1236 { DBGBUS_SSPP1, 20, 4 },
1237 { DBGBUS_SSPP1, 20, 5 },
1238 { DBGBUS_SSPP1, 20, 6 },
1239 { DBGBUS_SSPP1, 20, 7 },
1240
1241 { DBGBUS_SSPP1, 21, 0 },
1242 { DBGBUS_SSPP1, 21, 1 },
1243 { DBGBUS_SSPP1, 21, 2 },
1244 { DBGBUS_SSPP1, 21, 3 },
1245 { DBGBUS_SSPP1, 21, 4 },
1246 { DBGBUS_SSPP1, 21, 5 },
1247 { DBGBUS_SSPP1, 21, 6 },
1248 { DBGBUS_SSPP1, 21, 7 },
1249
1250 { DBGBUS_SSPP1, 22, 0 },
1251 { DBGBUS_SSPP1, 22, 1 },
1252 { DBGBUS_SSPP1, 22, 2 },
1253 { DBGBUS_SSPP1, 22, 3 },
1254 { DBGBUS_SSPP1, 22, 4 },
1255 { DBGBUS_SSPP1, 22, 5 },
1256 { DBGBUS_SSPP1, 22, 6 },
1257 { DBGBUS_SSPP1, 22, 7 },
1258
1259 { DBGBUS_SSPP1, 24, 0 },
1260 { DBGBUS_SSPP1, 24, 1 },
1261 { DBGBUS_SSPP1, 24, 2 },
1262 { DBGBUS_SSPP1, 24, 3 },
1263 { DBGBUS_SSPP1, 24, 4 },
1264 { DBGBUS_SSPP1, 24, 5 },
1265 { DBGBUS_SSPP1, 24, 6 },
1266 { DBGBUS_SSPP1, 24, 7 },
1267
1268 { DBGBUS_SSPP1, 25, 0 },
1269 { DBGBUS_SSPP1, 25, 1 },
1270 { DBGBUS_SSPP1, 25, 2 },
1271 { DBGBUS_SSPP1, 25, 3 },
1272 { DBGBUS_SSPP1, 25, 4 },
1273 { DBGBUS_SSPP1, 25, 5 },
1274 { DBGBUS_SSPP1, 25, 6 },
1275 { DBGBUS_SSPP1, 25, 7 },
1276
1277 /* dma 3 */
1278 { DBGBUS_SSPP1, 30, 0 },
1279 { DBGBUS_SSPP1, 30, 1 },
1280 { DBGBUS_SSPP1, 30, 2 },
1281 { DBGBUS_SSPP1, 30, 3 },
1282 { DBGBUS_SSPP1, 30, 4 },
1283 { DBGBUS_SSPP1, 30, 5 },
1284 { DBGBUS_SSPP1, 30, 6 },
1285 { DBGBUS_SSPP1, 30, 7 },
1286
1287 { DBGBUS_SSPP1, 31, 0 },
1288 { DBGBUS_SSPP1, 31, 1 },
1289 { DBGBUS_SSPP1, 31, 2 },
1290 { DBGBUS_SSPP1, 31, 3 },
1291 { DBGBUS_SSPP1, 31, 4 },
1292 { DBGBUS_SSPP1, 31, 5 },
1293 { DBGBUS_SSPP1, 31, 6 },
1294 { DBGBUS_SSPP1, 31, 7 },
1295
1296 { DBGBUS_SSPP1, 32, 0 },
1297 { DBGBUS_SSPP1, 32, 1 },
1298 { DBGBUS_SSPP1, 32, 2 },
1299 { DBGBUS_SSPP1, 32, 3 },
1300 { DBGBUS_SSPP1, 32, 4 },
1301 { DBGBUS_SSPP1, 32, 5 },
1302 { DBGBUS_SSPP1, 32, 6 },
1303 { DBGBUS_SSPP1, 32, 7 },
1304
1305 { DBGBUS_SSPP1, 33, 0 },
1306 { DBGBUS_SSPP1, 33, 1 },
1307 { DBGBUS_SSPP1, 33, 2 },
1308 { DBGBUS_SSPP1, 33, 3 },
1309 { DBGBUS_SSPP1, 33, 4 },
1310 { DBGBUS_SSPP1, 33, 5 },
1311 { DBGBUS_SSPP1, 33, 6 },
1312 { DBGBUS_SSPP1, 33, 7 },
1313
1314 { DBGBUS_SSPP1, 34, 0 },
1315 { DBGBUS_SSPP1, 34, 1 },
1316 { DBGBUS_SSPP1, 34, 2 },
1317 { DBGBUS_SSPP1, 34, 3 },
1318 { DBGBUS_SSPP1, 34, 4 },
1319 { DBGBUS_SSPP1, 34, 5 },
1320 { DBGBUS_SSPP1, 34, 6 },
1321 { DBGBUS_SSPP1, 34, 7 },
1322
1323 { DBGBUS_SSPP1, 35, 0 },
1324 { DBGBUS_SSPP1, 35, 1 },
1325 { DBGBUS_SSPP1, 35, 2 },
1326
1327 /* dma 1 */
1328 { DBGBUS_SSPP1, 40, 0 },
1329 { DBGBUS_SSPP1, 40, 1 },
1330 { DBGBUS_SSPP1, 40, 2 },
1331 { DBGBUS_SSPP1, 40, 3 },
1332 { DBGBUS_SSPP1, 40, 4 },
1333 { DBGBUS_SSPP1, 40, 5 },
1334 { DBGBUS_SSPP1, 40, 6 },
1335 { DBGBUS_SSPP1, 40, 7 },
1336
1337 { DBGBUS_SSPP1, 41, 0 },
1338 { DBGBUS_SSPP1, 41, 1 },
1339 { DBGBUS_SSPP1, 41, 2 },
1340 { DBGBUS_SSPP1, 41, 3 },
1341 { DBGBUS_SSPP1, 41, 4 },
1342 { DBGBUS_SSPP1, 41, 5 },
1343 { DBGBUS_SSPP1, 41, 6 },
1344 { DBGBUS_SSPP1, 41, 7 },
1345
1346 { DBGBUS_SSPP1, 42, 0 },
1347 { DBGBUS_SSPP1, 42, 1 },
1348 { DBGBUS_SSPP1, 42, 2 },
1349 { DBGBUS_SSPP1, 42, 3 },
1350 { DBGBUS_SSPP1, 42, 4 },
1351 { DBGBUS_SSPP1, 42, 5 },
1352 { DBGBUS_SSPP1, 42, 6 },
1353 { DBGBUS_SSPP1, 42, 7 },
1354
1355 { DBGBUS_SSPP1, 44, 0 },
1356 { DBGBUS_SSPP1, 44, 1 },
1357 { DBGBUS_SSPP1, 44, 2 },
1358 { DBGBUS_SSPP1, 44, 3 },
1359 { DBGBUS_SSPP1, 44, 4 },
1360 { DBGBUS_SSPP1, 44, 5 },
1361 { DBGBUS_SSPP1, 44, 6 },
1362 { DBGBUS_SSPP1, 44, 7 },
1363
1364 { DBGBUS_SSPP1, 45, 0 },
1365 { DBGBUS_SSPP1, 45, 1 },
1366 { DBGBUS_SSPP1, 45, 2 },
1367 { DBGBUS_SSPP1, 45, 3 },
1368 { DBGBUS_SSPP1, 45, 4 },
1369 { DBGBUS_SSPP1, 45, 5 },
1370 { DBGBUS_SSPP1, 45, 6 },
1371 { DBGBUS_SSPP1, 45, 7 },
1372
1373 /* dspp */
1374 { DBGBUS_DSPP, 13, 0 },
1375 { DBGBUS_DSPP, 19, 0 },
1376 { DBGBUS_DSPP, 14, 0 },
1377 { DBGBUS_DSPP, 14, 1 },
1378 { DBGBUS_DSPP, 14, 3 },
1379 { DBGBUS_DSPP, 20, 0 },
1380 { DBGBUS_DSPP, 20, 1 },
1381 { DBGBUS_DSPP, 20, 3 },
1382
1383 /* ppb_0 */
1384 { DBGBUS_DSPP, 31, 0, _dpu_debug_bus_ppb0_dump },
1385 { DBGBUS_DSPP, 33, 0, _dpu_debug_bus_ppb0_dump },
1386 { DBGBUS_DSPP, 35, 0, _dpu_debug_bus_ppb0_dump },
1387 { DBGBUS_DSPP, 42, 0, _dpu_debug_bus_ppb0_dump },
1388
1389 /* ppb_1 */
1390 { DBGBUS_DSPP, 32, 0, _dpu_debug_bus_ppb1_dump },
1391 { DBGBUS_DSPP, 34, 0, _dpu_debug_bus_ppb1_dump },
1392 { DBGBUS_DSPP, 36, 0, _dpu_debug_bus_ppb1_dump },
1393 { DBGBUS_DSPP, 43, 0, _dpu_debug_bus_ppb1_dump },
1394
1395 /* lm_lut */
1396 { DBGBUS_DSPP, 109, 0 },
1397 { DBGBUS_DSPP, 105, 0 },
1398 { DBGBUS_DSPP, 103, 0 },
1399
1400 /* crossbar */
1401 { DBGBUS_DSPP, 0, 0, _dpu_debug_bus_xbar_dump },
1402
1403 /* rotator */
1404 { DBGBUS_DSPP, 9, 0},
1405
1406 /* blend */
1407 /* LM0 */
1408 { DBGBUS_DSPP, 63, 1},
1409 { DBGBUS_DSPP, 63, 2},
1410 { DBGBUS_DSPP, 63, 3},
1411 { DBGBUS_DSPP, 63, 4},
1412 { DBGBUS_DSPP, 63, 5},
1413 { DBGBUS_DSPP, 63, 6},
1414 { DBGBUS_DSPP, 63, 7, _dpu_debug_bus_lm_dump },
1415
1416 { DBGBUS_DSPP, 64, 1},
1417 { DBGBUS_DSPP, 64, 2},
1418 { DBGBUS_DSPP, 64, 3},
1419 { DBGBUS_DSPP, 64, 4},
1420 { DBGBUS_DSPP, 64, 5},
1421 { DBGBUS_DSPP, 64, 6},
1422 { DBGBUS_DSPP, 64, 7, _dpu_debug_bus_lm_dump },
1423
1424 { DBGBUS_DSPP, 65, 1},
1425 { DBGBUS_DSPP, 65, 2},
1426 { DBGBUS_DSPP, 65, 3},
1427 { DBGBUS_DSPP, 65, 4},
1428 { DBGBUS_DSPP, 65, 5},
1429 { DBGBUS_DSPP, 65, 6},
1430 { DBGBUS_DSPP, 65, 7, _dpu_debug_bus_lm_dump },
1431
1432 { DBGBUS_DSPP, 66, 1},
1433 { DBGBUS_DSPP, 66, 2},
1434 { DBGBUS_DSPP, 66, 3},
1435 { DBGBUS_DSPP, 66, 4},
1436 { DBGBUS_DSPP, 66, 5},
1437 { DBGBUS_DSPP, 66, 6},
1438 { DBGBUS_DSPP, 66, 7, _dpu_debug_bus_lm_dump },
1439
1440 { DBGBUS_DSPP, 67, 1},
1441 { DBGBUS_DSPP, 67, 2},
1442 { DBGBUS_DSPP, 67, 3},
1443 { DBGBUS_DSPP, 67, 4},
1444 { DBGBUS_DSPP, 67, 5},
1445 { DBGBUS_DSPP, 67, 6},
1446 { DBGBUS_DSPP, 67, 7, _dpu_debug_bus_lm_dump },
1447
1448 { DBGBUS_DSPP, 68, 1},
1449 { DBGBUS_DSPP, 68, 2},
1450 { DBGBUS_DSPP, 68, 3},
1451 { DBGBUS_DSPP, 68, 4},
1452 { DBGBUS_DSPP, 68, 5},
1453 { DBGBUS_DSPP, 68, 6},
1454 { DBGBUS_DSPP, 68, 7, _dpu_debug_bus_lm_dump },
1455
1456 { DBGBUS_DSPP, 69, 1},
1457 { DBGBUS_DSPP, 69, 2},
1458 { DBGBUS_DSPP, 69, 3},
1459 { DBGBUS_DSPP, 69, 4},
1460 { DBGBUS_DSPP, 69, 5},
1461 { DBGBUS_DSPP, 69, 6},
1462 { DBGBUS_DSPP, 69, 7, _dpu_debug_bus_lm_dump },
1463
1464 { DBGBUS_DSPP, 84, 1},
1465 { DBGBUS_DSPP, 84, 2},
1466 { DBGBUS_DSPP, 84, 3},
1467 { DBGBUS_DSPP, 84, 4},
1468 { DBGBUS_DSPP, 84, 5},
1469 { DBGBUS_DSPP, 84, 6},
1470 { DBGBUS_DSPP, 84, 7, _dpu_debug_bus_lm_dump },
1471
1472
1473 { DBGBUS_DSPP, 85, 1},
1474 { DBGBUS_DSPP, 85, 2},
1475 { DBGBUS_DSPP, 85, 3},
1476 { DBGBUS_DSPP, 85, 4},
1477 { DBGBUS_DSPP, 85, 5},
1478 { DBGBUS_DSPP, 85, 6},
1479 { DBGBUS_DSPP, 85, 7, _dpu_debug_bus_lm_dump },
1480
1481
1482 { DBGBUS_DSPP, 86, 1},
1483 { DBGBUS_DSPP, 86, 2},
1484 { DBGBUS_DSPP, 86, 3},
1485 { DBGBUS_DSPP, 86, 4},
1486 { DBGBUS_DSPP, 86, 5},
1487 { DBGBUS_DSPP, 86, 6},
1488 { DBGBUS_DSPP, 86, 7, _dpu_debug_bus_lm_dump },
1489
1490
1491 { DBGBUS_DSPP, 87, 1},
1492 { DBGBUS_DSPP, 87, 2},
1493 { DBGBUS_DSPP, 87, 3},
1494 { DBGBUS_DSPP, 87, 4},
1495 { DBGBUS_DSPP, 87, 5},
1496 { DBGBUS_DSPP, 87, 6},
1497 { DBGBUS_DSPP, 87, 7, _dpu_debug_bus_lm_dump },
1498
1499 /* LM1 */
1500 { DBGBUS_DSPP, 70, 1},
1501 { DBGBUS_DSPP, 70, 2},
1502 { DBGBUS_DSPP, 70, 3},
1503 { DBGBUS_DSPP, 70, 4},
1504 { DBGBUS_DSPP, 70, 5},
1505 { DBGBUS_DSPP, 70, 6},
1506 { DBGBUS_DSPP, 70, 7, _dpu_debug_bus_lm_dump },
1507
1508 { DBGBUS_DSPP, 71, 1},
1509 { DBGBUS_DSPP, 71, 2},
1510 { DBGBUS_DSPP, 71, 3},
1511 { DBGBUS_DSPP, 71, 4},
1512 { DBGBUS_DSPP, 71, 5},
1513 { DBGBUS_DSPP, 71, 6},
1514 { DBGBUS_DSPP, 71, 7, _dpu_debug_bus_lm_dump },
1515
1516 { DBGBUS_DSPP, 72, 1},
1517 { DBGBUS_DSPP, 72, 2},
1518 { DBGBUS_DSPP, 72, 3},
1519 { DBGBUS_DSPP, 72, 4},
1520 { DBGBUS_DSPP, 72, 5},
1521 { DBGBUS_DSPP, 72, 6},
1522 { DBGBUS_DSPP, 72, 7, _dpu_debug_bus_lm_dump },
1523
1524 { DBGBUS_DSPP, 73, 1},
1525 { DBGBUS_DSPP, 73, 2},
1526 { DBGBUS_DSPP, 73, 3},
1527 { DBGBUS_DSPP, 73, 4},
1528 { DBGBUS_DSPP, 73, 5},
1529 { DBGBUS_DSPP, 73, 6},
1530 { DBGBUS_DSPP, 73, 7, _dpu_debug_bus_lm_dump },
1531
1532 { DBGBUS_DSPP, 74, 1},
1533 { DBGBUS_DSPP, 74, 2},
1534 { DBGBUS_DSPP, 74, 3},
1535 { DBGBUS_DSPP, 74, 4},
1536 { DBGBUS_DSPP, 74, 5},
1537 { DBGBUS_DSPP, 74, 6},
1538 { DBGBUS_DSPP, 74, 7, _dpu_debug_bus_lm_dump },
1539
1540 { DBGBUS_DSPP, 75, 1},
1541 { DBGBUS_DSPP, 75, 2},
1542 { DBGBUS_DSPP, 75, 3},
1543 { DBGBUS_DSPP, 75, 4},
1544 { DBGBUS_DSPP, 75, 5},
1545 { DBGBUS_DSPP, 75, 6},
1546 { DBGBUS_DSPP, 75, 7, _dpu_debug_bus_lm_dump },
1547
1548 { DBGBUS_DSPP, 76, 1},
1549 { DBGBUS_DSPP, 76, 2},
1550 { DBGBUS_DSPP, 76, 3},
1551 { DBGBUS_DSPP, 76, 4},
1552 { DBGBUS_DSPP, 76, 5},
1553 { DBGBUS_DSPP, 76, 6},
1554 { DBGBUS_DSPP, 76, 7, _dpu_debug_bus_lm_dump },
1555
1556 { DBGBUS_DSPP, 88, 1},
1557 { DBGBUS_DSPP, 88, 2},
1558 { DBGBUS_DSPP, 88, 3},
1559 { DBGBUS_DSPP, 88, 4},
1560 { DBGBUS_DSPP, 88, 5},
1561 { DBGBUS_DSPP, 88, 6},
1562 { DBGBUS_DSPP, 88, 7, _dpu_debug_bus_lm_dump },
1563
1564 { DBGBUS_DSPP, 89, 1},
1565 { DBGBUS_DSPP, 89, 2},
1566 { DBGBUS_DSPP, 89, 3},
1567 { DBGBUS_DSPP, 89, 4},
1568 { DBGBUS_DSPP, 89, 5},
1569 { DBGBUS_DSPP, 89, 6},
1570 { DBGBUS_DSPP, 89, 7, _dpu_debug_bus_lm_dump },
1571
1572 { DBGBUS_DSPP, 90, 1},
1573 { DBGBUS_DSPP, 90, 2},
1574 { DBGBUS_DSPP, 90, 3},
1575 { DBGBUS_DSPP, 90, 4},
1576 { DBGBUS_DSPP, 90, 5},
1577 { DBGBUS_DSPP, 90, 6},
1578 { DBGBUS_DSPP, 90, 7, _dpu_debug_bus_lm_dump },
1579
1580 { DBGBUS_DSPP, 91, 1},
1581 { DBGBUS_DSPP, 91, 2},
1582 { DBGBUS_DSPP, 91, 3},
1583 { DBGBUS_DSPP, 91, 4},
1584 { DBGBUS_DSPP, 91, 5},
1585 { DBGBUS_DSPP, 91, 6},
1586 { DBGBUS_DSPP, 91, 7, _dpu_debug_bus_lm_dump },
1587
1588 /* LM2 */
1589 { DBGBUS_DSPP, 77, 0},
1590 { DBGBUS_DSPP, 77, 1},
1591 { DBGBUS_DSPP, 77, 2},
1592 { DBGBUS_DSPP, 77, 3},
1593 { DBGBUS_DSPP, 77, 4},
1594 { DBGBUS_DSPP, 77, 5},
1595 { DBGBUS_DSPP, 77, 6},
1596 { DBGBUS_DSPP, 77, 7, _dpu_debug_bus_lm_dump },
1597
1598 { DBGBUS_DSPP, 78, 0},
1599 { DBGBUS_DSPP, 78, 1},
1600 { DBGBUS_DSPP, 78, 2},
1601 { DBGBUS_DSPP, 78, 3},
1602 { DBGBUS_DSPP, 78, 4},
1603 { DBGBUS_DSPP, 78, 5},
1604 { DBGBUS_DSPP, 78, 6},
1605 { DBGBUS_DSPP, 78, 7, _dpu_debug_bus_lm_dump },
1606
1607 { DBGBUS_DSPP, 79, 0},
1608 { DBGBUS_DSPP, 79, 1},
1609 { DBGBUS_DSPP, 79, 2},
1610 { DBGBUS_DSPP, 79, 3},
1611 { DBGBUS_DSPP, 79, 4},
1612 { DBGBUS_DSPP, 79, 5},
1613 { DBGBUS_DSPP, 79, 6},
1614 { DBGBUS_DSPP, 79, 7, _dpu_debug_bus_lm_dump },
1615
1616 { DBGBUS_DSPP, 80, 0},
1617 { DBGBUS_DSPP, 80, 1},
1618 { DBGBUS_DSPP, 80, 2},
1619 { DBGBUS_DSPP, 80, 3},
1620 { DBGBUS_DSPP, 80, 4},
1621 { DBGBUS_DSPP, 80, 5},
1622 { DBGBUS_DSPP, 80, 6},
1623 { DBGBUS_DSPP, 80, 7, _dpu_debug_bus_lm_dump },
1624
1625 { DBGBUS_DSPP, 81, 0},
1626 { DBGBUS_DSPP, 81, 1},
1627 { DBGBUS_DSPP, 81, 2},
1628 { DBGBUS_DSPP, 81, 3},
1629 { DBGBUS_DSPP, 81, 4},
1630 { DBGBUS_DSPP, 81, 5},
1631 { DBGBUS_DSPP, 81, 6},
1632 { DBGBUS_DSPP, 81, 7, _dpu_debug_bus_lm_dump },
1633
1634 { DBGBUS_DSPP, 82, 0},
1635 { DBGBUS_DSPP, 82, 1},
1636 { DBGBUS_DSPP, 82, 2},
1637 { DBGBUS_DSPP, 82, 3},
1638 { DBGBUS_DSPP, 82, 4},
1639 { DBGBUS_DSPP, 82, 5},
1640 { DBGBUS_DSPP, 82, 6},
1641 { DBGBUS_DSPP, 82, 7, _dpu_debug_bus_lm_dump },
1642
1643 { DBGBUS_DSPP, 83, 0},
1644 { DBGBUS_DSPP, 83, 1},
1645 { DBGBUS_DSPP, 83, 2},
1646 { DBGBUS_DSPP, 83, 3},
1647 { DBGBUS_DSPP, 83, 4},
1648 { DBGBUS_DSPP, 83, 5},
1649 { DBGBUS_DSPP, 83, 6},
1650 { DBGBUS_DSPP, 83, 7, _dpu_debug_bus_lm_dump },
1651
1652 { DBGBUS_DSPP, 92, 1},
1653 { DBGBUS_DSPP, 92, 2},
1654 { DBGBUS_DSPP, 92, 3},
1655 { DBGBUS_DSPP, 92, 4},
1656 { DBGBUS_DSPP, 92, 5},
1657 { DBGBUS_DSPP, 92, 6},
1658 { DBGBUS_DSPP, 92, 7, _dpu_debug_bus_lm_dump },
1659
1660 { DBGBUS_DSPP, 93, 1},
1661 { DBGBUS_DSPP, 93, 2},
1662 { DBGBUS_DSPP, 93, 3},
1663 { DBGBUS_DSPP, 93, 4},
1664 { DBGBUS_DSPP, 93, 5},
1665 { DBGBUS_DSPP, 93, 6},
1666 { DBGBUS_DSPP, 93, 7, _dpu_debug_bus_lm_dump },
1667
1668 { DBGBUS_DSPP, 94, 1},
1669 { DBGBUS_DSPP, 94, 2},
1670 { DBGBUS_DSPP, 94, 3},
1671 { DBGBUS_DSPP, 94, 4},
1672 { DBGBUS_DSPP, 94, 5},
1673 { DBGBUS_DSPP, 94, 6},
1674 { DBGBUS_DSPP, 94, 7, _dpu_debug_bus_lm_dump },
1675
1676 { DBGBUS_DSPP, 95, 1},
1677 { DBGBUS_DSPP, 95, 2},
1678 { DBGBUS_DSPP, 95, 3},
1679 { DBGBUS_DSPP, 95, 4},
1680 { DBGBUS_DSPP, 95, 5},
1681 { DBGBUS_DSPP, 95, 6},
1682 { DBGBUS_DSPP, 95, 7, _dpu_debug_bus_lm_dump },
1683
1684 /* LM5 */
1685 { DBGBUS_DSPP, 110, 1},
1686 { DBGBUS_DSPP, 110, 2},
1687 { DBGBUS_DSPP, 110, 3},
1688 { DBGBUS_DSPP, 110, 4},
1689 { DBGBUS_DSPP, 110, 5},
1690 { DBGBUS_DSPP, 110, 6},
1691 { DBGBUS_DSPP, 110, 7, _dpu_debug_bus_lm_dump },
1692
1693 { DBGBUS_DSPP, 111, 1},
1694 { DBGBUS_DSPP, 111, 2},
1695 { DBGBUS_DSPP, 111, 3},
1696 { DBGBUS_DSPP, 111, 4},
1697 { DBGBUS_DSPP, 111, 5},
1698 { DBGBUS_DSPP, 111, 6},
1699 { DBGBUS_DSPP, 111, 7, _dpu_debug_bus_lm_dump },
1700
1701 { DBGBUS_DSPP, 112, 1},
1702 { DBGBUS_DSPP, 112, 2},
1703 { DBGBUS_DSPP, 112, 3},
1704 { DBGBUS_DSPP, 112, 4},
1705 { DBGBUS_DSPP, 112, 5},
1706 { DBGBUS_DSPP, 112, 6},
1707 { DBGBUS_DSPP, 112, 7, _dpu_debug_bus_lm_dump },
1708
1709 { DBGBUS_DSPP, 113, 1},
1710 { DBGBUS_DSPP, 113, 2},
1711 { DBGBUS_DSPP, 113, 3},
1712 { DBGBUS_DSPP, 113, 4},
1713 { DBGBUS_DSPP, 113, 5},
1714 { DBGBUS_DSPP, 113, 6},
1715 { DBGBUS_DSPP, 113, 7, _dpu_debug_bus_lm_dump },
1716
1717 { DBGBUS_DSPP, 114, 1},
1718 { DBGBUS_DSPP, 114, 2},
1719 { DBGBUS_DSPP, 114, 3},
1720 { DBGBUS_DSPP, 114, 4},
1721 { DBGBUS_DSPP, 114, 5},
1722 { DBGBUS_DSPP, 114, 6},
1723 { DBGBUS_DSPP, 114, 7, _dpu_debug_bus_lm_dump },
1724
1725 { DBGBUS_DSPP, 115, 1},
1726 { DBGBUS_DSPP, 115, 2},
1727 { DBGBUS_DSPP, 115, 3},
1728 { DBGBUS_DSPP, 115, 4},
1729 { DBGBUS_DSPP, 115, 5},
1730 { DBGBUS_DSPP, 115, 6},
1731 { DBGBUS_DSPP, 115, 7, _dpu_debug_bus_lm_dump },
1732
1733 { DBGBUS_DSPP, 116, 1},
1734 { DBGBUS_DSPP, 116, 2},
1735 { DBGBUS_DSPP, 116, 3},
1736 { DBGBUS_DSPP, 116, 4},
1737 { DBGBUS_DSPP, 116, 5},
1738 { DBGBUS_DSPP, 116, 6},
1739 { DBGBUS_DSPP, 116, 7, _dpu_debug_bus_lm_dump },
1740
1741 { DBGBUS_DSPP, 117, 1},
1742 { DBGBUS_DSPP, 117, 2},
1743 { DBGBUS_DSPP, 117, 3},
1744 { DBGBUS_DSPP, 117, 4},
1745 { DBGBUS_DSPP, 117, 5},
1746 { DBGBUS_DSPP, 117, 6},
1747 { DBGBUS_DSPP, 117, 7, _dpu_debug_bus_lm_dump },
1748
1749 { DBGBUS_DSPP, 118, 1},
1750 { DBGBUS_DSPP, 118, 2},
1751 { DBGBUS_DSPP, 118, 3},
1752 { DBGBUS_DSPP, 118, 4},
1753 { DBGBUS_DSPP, 118, 5},
1754 { DBGBUS_DSPP, 118, 6},
1755 { DBGBUS_DSPP, 118, 7, _dpu_debug_bus_lm_dump },
1756
1757 { DBGBUS_DSPP, 119, 1},
1758 { DBGBUS_DSPP, 119, 2},
1759 { DBGBUS_DSPP, 119, 3},
1760 { DBGBUS_DSPP, 119, 4},
1761 { DBGBUS_DSPP, 119, 5},
1762 { DBGBUS_DSPP, 119, 6},
1763 { DBGBUS_DSPP, 119, 7, _dpu_debug_bus_lm_dump },
1764
1765 { DBGBUS_DSPP, 120, 1},
1766 { DBGBUS_DSPP, 120, 2},
1767 { DBGBUS_DSPP, 120, 3},
1768 { DBGBUS_DSPP, 120, 4},
1769 { DBGBUS_DSPP, 120, 5},
1770 { DBGBUS_DSPP, 120, 6},
1771 { DBGBUS_DSPP, 120, 7, _dpu_debug_bus_lm_dump },
1772
1773 /* csc */
1774 { DBGBUS_SSPP0, 7, 0},
1775 { DBGBUS_SSPP0, 7, 1},
1776 { DBGBUS_SSPP0, 27, 0},
1777 { DBGBUS_SSPP0, 27, 1},
1778 { DBGBUS_SSPP1, 7, 0},
1779 { DBGBUS_SSPP1, 7, 1},
1780 { DBGBUS_SSPP1, 27, 0},
1781 { DBGBUS_SSPP1, 27, 1},
1782
1783 /* pcc */
1784 { DBGBUS_SSPP0, 3, 3},
1785 { DBGBUS_SSPP0, 23, 3},
1786 { DBGBUS_SSPP0, 33, 3},
1787 { DBGBUS_SSPP0, 43, 3},
1788 { DBGBUS_SSPP1, 3, 3},
1789 { DBGBUS_SSPP1, 23, 3},
1790 { DBGBUS_SSPP1, 33, 3},
1791 { DBGBUS_SSPP1, 43, 3},
1792
1793 /* spa */
1794 { DBGBUS_SSPP0, 8, 0},
1795 { DBGBUS_SSPP0, 28, 0},
1796 { DBGBUS_SSPP1, 8, 0},
1797 { DBGBUS_SSPP1, 28, 0},
1798 { DBGBUS_DSPP, 13, 0},
1799 { DBGBUS_DSPP, 19, 0},
1800
1801 /* igc */
1802 { DBGBUS_SSPP0, 17, 0},
1803 { DBGBUS_SSPP0, 17, 1},
1804 { DBGBUS_SSPP0, 17, 3},
1805 { DBGBUS_SSPP0, 37, 0},
1806 { DBGBUS_SSPP0, 37, 1},
1807 { DBGBUS_SSPP0, 37, 3},
1808 { DBGBUS_SSPP0, 46, 0},
1809 { DBGBUS_SSPP0, 46, 1},
1810 { DBGBUS_SSPP0, 46, 3},
1811
1812 { DBGBUS_SSPP1, 17, 0},
1813 { DBGBUS_SSPP1, 17, 1},
1814 { DBGBUS_SSPP1, 17, 3},
1815 { DBGBUS_SSPP1, 37, 0},
1816 { DBGBUS_SSPP1, 37, 1},
1817 { DBGBUS_SSPP1, 37, 3},
1818 { DBGBUS_SSPP1, 46, 0},
1819 { DBGBUS_SSPP1, 46, 1},
1820 { DBGBUS_SSPP1, 46, 3},
1821
1822 { DBGBUS_DSPP, 14, 0},
1823 { DBGBUS_DSPP, 14, 1},
1824 { DBGBUS_DSPP, 14, 3},
1825 { DBGBUS_DSPP, 20, 0},
1826 { DBGBUS_DSPP, 20, 1},
1827 { DBGBUS_DSPP, 20, 3},
1828
1829 /* intf0-3 */
1830 { DBGBUS_PERIPH, 0, 0},
1831 { DBGBUS_PERIPH, 1, 0},
1832 { DBGBUS_PERIPH, 2, 0},
1833 { DBGBUS_PERIPH, 3, 0},
1834
1835 /* te counter wrapper */
1836 { DBGBUS_PERIPH, 60, 0},
1837
1838 /* dsc0 */
1839 { DBGBUS_PERIPH, 47, 0},
1840 { DBGBUS_PERIPH, 47, 1},
1841 { DBGBUS_PERIPH, 47, 2},
1842 { DBGBUS_PERIPH, 47, 3},
1843 { DBGBUS_PERIPH, 47, 4},
1844 { DBGBUS_PERIPH, 47, 5},
1845 { DBGBUS_PERIPH, 47, 6},
1846 { DBGBUS_PERIPH, 47, 7},
1847
1848 /* dsc1 */
1849 { DBGBUS_PERIPH, 48, 0},
1850 { DBGBUS_PERIPH, 48, 1},
1851 { DBGBUS_PERIPH, 48, 2},
1852 { DBGBUS_PERIPH, 48, 3},
1853 { DBGBUS_PERIPH, 48, 4},
1854 { DBGBUS_PERIPH, 48, 5},
1855 { DBGBUS_PERIPH, 48, 6},
1856 { DBGBUS_PERIPH, 48, 7},
1857
1858 /* dsc2 */
1859 { DBGBUS_PERIPH, 51, 0},
1860 { DBGBUS_PERIPH, 51, 1},
1861 { DBGBUS_PERIPH, 51, 2},
1862 { DBGBUS_PERIPH, 51, 3},
1863 { DBGBUS_PERIPH, 51, 4},
1864 { DBGBUS_PERIPH, 51, 5},
1865 { DBGBUS_PERIPH, 51, 6},
1866 { DBGBUS_PERIPH, 51, 7},
1867
1868 /* dsc3 */
1869 { DBGBUS_PERIPH, 52, 0},
1870 { DBGBUS_PERIPH, 52, 1},
1871 { DBGBUS_PERIPH, 52, 2},
1872 { DBGBUS_PERIPH, 52, 3},
1873 { DBGBUS_PERIPH, 52, 4},
1874 { DBGBUS_PERIPH, 52, 5},
1875 { DBGBUS_PERIPH, 52, 6},
1876 { DBGBUS_PERIPH, 52, 7},
1877
1878 /* tear-check */
1879 { DBGBUS_PERIPH, 63, 0 },
1880 { DBGBUS_PERIPH, 64, 0 },
1881 { DBGBUS_PERIPH, 65, 0 },
1882 { DBGBUS_PERIPH, 73, 0 },
1883 { DBGBUS_PERIPH, 74, 0 },
1884
1885 /* cdwn */
1886 { DBGBUS_PERIPH, 80, 0},
1887 { DBGBUS_PERIPH, 80, 1},
1888 { DBGBUS_PERIPH, 80, 2},
1889
1890 { DBGBUS_PERIPH, 81, 0},
1891 { DBGBUS_PERIPH, 81, 1},
1892 { DBGBUS_PERIPH, 81, 2},
1893
1894 { DBGBUS_PERIPH, 82, 0},
1895 { DBGBUS_PERIPH, 82, 1},
1896 { DBGBUS_PERIPH, 82, 2},
1897 { DBGBUS_PERIPH, 82, 3},
1898 { DBGBUS_PERIPH, 82, 4},
1899 { DBGBUS_PERIPH, 82, 5},
1900 { DBGBUS_PERIPH, 82, 6},
1901 { DBGBUS_PERIPH, 82, 7},
1902
1903 /* hdmi */
1904 { DBGBUS_PERIPH, 68, 0},
1905 { DBGBUS_PERIPH, 68, 1},
1906 { DBGBUS_PERIPH, 68, 2},
1907 { DBGBUS_PERIPH, 68, 3},
1908 { DBGBUS_PERIPH, 68, 4},
1909 { DBGBUS_PERIPH, 68, 5},
1910
1911 /* edp */
1912 { DBGBUS_PERIPH, 69, 0},
1913 { DBGBUS_PERIPH, 69, 1},
1914 { DBGBUS_PERIPH, 69, 2},
1915 { DBGBUS_PERIPH, 69, 3},
1916 { DBGBUS_PERIPH, 69, 4},
1917 { DBGBUS_PERIPH, 69, 5},
1918
1919 /* dsi0 */
1920 { DBGBUS_PERIPH, 70, 0},
1921 { DBGBUS_PERIPH, 70, 1},
1922 { DBGBUS_PERIPH, 70, 2},
1923 { DBGBUS_PERIPH, 70, 3},
1924 { DBGBUS_PERIPH, 70, 4},
1925 { DBGBUS_PERIPH, 70, 5},
1926
1927 /* dsi1 */
1928 { DBGBUS_PERIPH, 71, 0},
1929 { DBGBUS_PERIPH, 71, 1},
1930 { DBGBUS_PERIPH, 71, 2},
1931 { DBGBUS_PERIPH, 71, 3},
1932 { DBGBUS_PERIPH, 71, 4},
1933 { DBGBUS_PERIPH, 71, 5},
1934 };
1935
1936 static struct vbif_debug_bus_entry vbif_dbg_bus_msm8998[] = {
1937 {0x214, 0x21c, 16, 2, 0x0, 0xd}, /* arb clients */
1938 {0x214, 0x21c, 16, 2, 0x80, 0xc0}, /* arb clients */
1939 {0x214, 0x21c, 16, 2, 0x100, 0x140}, /* arb clients */
1940 {0x214, 0x21c, 0, 16, 0x0, 0xf}, /* xin blocks - axi side */
1941 {0x214, 0x21c, 0, 16, 0x80, 0xa4}, /* xin blocks - axi side */
1942 {0x214, 0x21c, 0, 15, 0x100, 0x124}, /* xin blocks - axi side */
1943 {0x21c, 0x214, 0, 14, 0, 0xc}, /* xin blocks - clock side */
1944 };
1945
1946 /**
1947 * _dpu_dbg_enable_power - use callback to turn power on for hw register access
1948 * @enable: whether to turn power on or off
1949 */
_dpu_dbg_enable_power(int enable)1950 static inline void _dpu_dbg_enable_power(int enable)
1951 {
1952 if (enable)
1953 pm_runtime_get_sync(dpu_dbg_base.dev);
1954 else
1955 pm_runtime_put_sync(dpu_dbg_base.dev);
1956 }
1957
_dpu_dbg_dump_dpu_dbg_bus(struct dpu_dbg_dpu_debug_bus * bus)1958 static void _dpu_dbg_dump_dpu_dbg_bus(struct dpu_dbg_dpu_debug_bus *bus)
1959 {
1960 bool in_log, in_mem;
1961 u32 **dump_mem = NULL;
1962 u32 *dump_addr = NULL;
1963 u32 status = 0;
1964 struct dpu_debug_bus_entry *head;
1965 phys_addr_t phys = 0;
1966 int list_size;
1967 int i;
1968 u32 offset;
1969 void __iomem *mem_base = NULL;
1970 struct dpu_dbg_reg_base *reg_base;
1971
1972 if (!bus || !bus->cmn.entries_size)
1973 return;
1974
1975 list_for_each_entry(reg_base, &dpu_dbg_base.reg_base_list,
1976 reg_base_head)
1977 if (strlen(reg_base->name) &&
1978 !strcmp(reg_base->name, bus->cmn.name))
1979 mem_base = reg_base->base + bus->top_blk_off;
1980
1981 if (!mem_base) {
1982 pr_err("unable to find mem_base for %s\n", bus->cmn.name);
1983 return;
1984 }
1985
1986 dump_mem = &bus->cmn.dumped_content;
1987
1988 /* will keep in memory 4 entries of 4 bytes each */
1989 list_size = (bus->cmn.entries_size * 4 * 4);
1990
1991 in_log = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_LOG);
1992 in_mem = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_MEM);
1993
1994 if (!in_log && !in_mem)
1995 return;
1996
1997 dev_info(dpu_dbg_base.dev, "======== start %s dump =========\n",
1998 bus->cmn.name);
1999
2000 if (in_mem) {
2001 if (!(*dump_mem))
2002 *dump_mem = dma_alloc_coherent(dpu_dbg_base.dev,
2003 list_size, &phys, GFP_KERNEL);
2004
2005 if (*dump_mem) {
2006 dump_addr = *dump_mem;
2007 dev_info(dpu_dbg_base.dev,
2008 "%s: start_addr:0x%pK len:0x%x\n",
2009 __func__, dump_addr, list_size);
2010 } else {
2011 in_mem = false;
2012 pr_err("dump_mem: allocation fails\n");
2013 }
2014 }
2015
2016 _dpu_dbg_enable_power(true);
2017 for (i = 0; i < bus->cmn.entries_size; i++) {
2018 head = bus->entries + i;
2019 writel_relaxed(TEST_MASK(head->block_id, head->test_id),
2020 mem_base + head->wr_addr);
2021 wmb(); /* make sure test bits were written */
2022
2023 if (bus->cmn.flags & DBGBUS_FLAGS_DSPP) {
2024 offset = DBGBUS_DSPP_STATUS;
2025 /* keep DSPP test point enabled */
2026 if (head->wr_addr != DBGBUS_DSPP)
2027 writel_relaxed(0xF, mem_base + DBGBUS_DSPP);
2028 } else {
2029 offset = head->wr_addr + 0x4;
2030 }
2031
2032 status = readl_relaxed(mem_base + offset);
2033
2034 if (in_log)
2035 dev_info(dpu_dbg_base.dev,
2036 "waddr=0x%x blk=%d tst=%d val=0x%x\n",
2037 head->wr_addr, head->block_id,
2038 head->test_id, status);
2039
2040 if (dump_addr && in_mem) {
2041 dump_addr[i*4] = head->wr_addr;
2042 dump_addr[i*4 + 1] = head->block_id;
2043 dump_addr[i*4 + 2] = head->test_id;
2044 dump_addr[i*4 + 3] = status;
2045 }
2046
2047 if (head->analyzer)
2048 head->analyzer(mem_base, head, status);
2049
2050 /* Disable debug bus once we are done */
2051 writel_relaxed(0, mem_base + head->wr_addr);
2052 if (bus->cmn.flags & DBGBUS_FLAGS_DSPP &&
2053 head->wr_addr != DBGBUS_DSPP)
2054 writel_relaxed(0x0, mem_base + DBGBUS_DSPP);
2055 }
2056 _dpu_dbg_enable_power(false);
2057
2058 dev_info(dpu_dbg_base.dev, "======== end %s dump =========\n",
2059 bus->cmn.name);
2060 }
2061
_dpu_dbg_dump_vbif_debug_bus_entry(struct vbif_debug_bus_entry * head,void __iomem * mem_base,u32 * dump_addr,bool in_log)2062 static void _dpu_dbg_dump_vbif_debug_bus_entry(
2063 struct vbif_debug_bus_entry *head, void __iomem *mem_base,
2064 u32 *dump_addr, bool in_log)
2065 {
2066 int i, j;
2067 u32 val;
2068
2069 if (!dump_addr && !in_log)
2070 return;
2071
2072 for (i = 0; i < head->block_cnt; i++) {
2073 writel_relaxed(1 << (i + head->bit_offset),
2074 mem_base + head->block_bus_addr);
2075 /* make sure that current bus blcok enable */
2076 wmb();
2077 for (j = head->test_pnt_start; j < head->test_pnt_cnt; j++) {
2078 writel_relaxed(j, mem_base + head->block_bus_addr + 4);
2079 /* make sure that test point is enabled */
2080 wmb();
2081 val = readl_relaxed(mem_base + MMSS_VBIF_TEST_BUS_OUT);
2082 if (dump_addr) {
2083 *dump_addr++ = head->block_bus_addr;
2084 *dump_addr++ = i;
2085 *dump_addr++ = j;
2086 *dump_addr++ = val;
2087 }
2088 if (in_log)
2089 dev_info(dpu_dbg_base.dev,
2090 "testpoint:%x arb/xin id=%d index=%d val=0x%x\n",
2091 head->block_bus_addr, i, j, val);
2092 }
2093 }
2094 }
2095
_dpu_dbg_dump_vbif_dbg_bus(struct dpu_dbg_vbif_debug_bus * bus)2096 static void _dpu_dbg_dump_vbif_dbg_bus(struct dpu_dbg_vbif_debug_bus *bus)
2097 {
2098 bool in_log, in_mem;
2099 u32 **dump_mem = NULL;
2100 u32 *dump_addr = NULL;
2101 u32 value, d0, d1;
2102 unsigned long reg, reg1, reg2;
2103 struct vbif_debug_bus_entry *head;
2104 phys_addr_t phys = 0;
2105 int i, list_size = 0;
2106 void __iomem *mem_base = NULL;
2107 struct vbif_debug_bus_entry *dbg_bus;
2108 u32 bus_size;
2109 struct dpu_dbg_reg_base *reg_base;
2110
2111 if (!bus || !bus->cmn.entries_size)
2112 return;
2113
2114 list_for_each_entry(reg_base, &dpu_dbg_base.reg_base_list,
2115 reg_base_head)
2116 if (strlen(reg_base->name) &&
2117 !strcmp(reg_base->name, bus->cmn.name))
2118 mem_base = reg_base->base;
2119
2120 if (!mem_base) {
2121 pr_err("unable to find mem_base for %s\n", bus->cmn.name);
2122 return;
2123 }
2124
2125 dbg_bus = bus->entries;
2126 bus_size = bus->cmn.entries_size;
2127 list_size = bus->cmn.entries_size;
2128 dump_mem = &bus->cmn.dumped_content;
2129
2130 dev_info(dpu_dbg_base.dev, "======== start %s dump =========\n",
2131 bus->cmn.name);
2132
2133 if (!dump_mem || !dbg_bus || !bus_size || !list_size)
2134 return;
2135
2136 /* allocate memory for each test point */
2137 for (i = 0; i < bus_size; i++) {
2138 head = dbg_bus + i;
2139 list_size += (head->block_cnt * head->test_pnt_cnt);
2140 }
2141
2142 /* 4 bytes * 4 entries for each test point*/
2143 list_size *= 16;
2144
2145 in_log = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_LOG);
2146 in_mem = (bus->cmn.enable_mask & DPU_DBG_DUMP_IN_MEM);
2147
2148 if (!in_log && !in_mem)
2149 return;
2150
2151 if (in_mem) {
2152 if (!(*dump_mem))
2153 *dump_mem = dma_alloc_coherent(dpu_dbg_base.dev,
2154 list_size, &phys, GFP_KERNEL);
2155
2156 if (*dump_mem) {
2157 dump_addr = *dump_mem;
2158 dev_info(dpu_dbg_base.dev,
2159 "%s: start_addr:0x%pK len:0x%x\n",
2160 __func__, dump_addr, list_size);
2161 } else {
2162 in_mem = false;
2163 pr_err("dump_mem: allocation fails\n");
2164 }
2165 }
2166
2167 _dpu_dbg_enable_power(true);
2168
2169 value = readl_relaxed(mem_base + MMSS_VBIF_CLKON);
2170 writel_relaxed(value | BIT(1), mem_base + MMSS_VBIF_CLKON);
2171
2172 /* make sure that vbif core is on */
2173 wmb();
2174
2175 /**
2176 * Extract VBIF error info based on XIN halt and error status.
2177 * If the XIN client is not in HALT state, or an error is detected,
2178 * then retrieve the VBIF error info for it.
2179 */
2180 reg = readl_relaxed(mem_base + MMSS_VBIF_XIN_HALT_CTRL1);
2181 reg1 = readl_relaxed(mem_base + MMSS_VBIF_PND_ERR);
2182 reg2 = readl_relaxed(mem_base + MMSS_VBIF_SRC_ERR);
2183 dev_err(dpu_dbg_base.dev,
2184 "XIN HALT:0x%lX, PND ERR:0x%lX, SRC ERR:0x%lX\n",
2185 reg, reg1, reg2);
2186 reg >>= 16;
2187 reg &= ~(reg1 | reg2);
2188 for (i = 0; i < MMSS_VBIF_CLIENT_NUM; i++) {
2189 if (!test_bit(0, ®)) {
2190 writel_relaxed(i, mem_base + MMSS_VBIF_ERR_INFO);
2191 /* make sure reg write goes through */
2192 wmb();
2193
2194 d0 = readl_relaxed(mem_base + MMSS_VBIF_ERR_INFO);
2195 d1 = readl_relaxed(mem_base + MMSS_VBIF_ERR_INFO_1);
2196
2197 dev_err(dpu_dbg_base.dev,
2198 "Client:%d, errinfo=0x%X, errinfo1=0x%X\n",
2199 i, d0, d1);
2200 }
2201 reg >>= 1;
2202 }
2203
2204 for (i = 0; i < bus_size; i++) {
2205 head = dbg_bus + i;
2206
2207 writel_relaxed(0, mem_base + head->disable_bus_addr);
2208 writel_relaxed(BIT(0), mem_base + MMSS_VBIF_TEST_BUS_OUT_CTRL);
2209 /* make sure that other bus is off */
2210 wmb();
2211
2212 _dpu_dbg_dump_vbif_debug_bus_entry(head, mem_base, dump_addr,
2213 in_log);
2214 if (dump_addr)
2215 dump_addr += (head->block_cnt * head->test_pnt_cnt * 4);
2216 }
2217
2218 _dpu_dbg_enable_power(false);
2219
2220 dev_info(dpu_dbg_base.dev, "======== end %s dump =========\n",
2221 bus->cmn.name);
2222 }
2223
2224 /**
2225 * _dpu_dump_array - dump array of register bases
2226 * @name: string indicating origin of dump
2227 * @dump_dbgbus_dpu: whether to dump the dpu debug bus
2228 * @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus
2229 */
_dpu_dump_array(const char * name,bool dump_dbgbus_dpu,bool dump_dbgbus_vbif_rt)2230 static void _dpu_dump_array(const char *name, bool dump_dbgbus_dpu,
2231 bool dump_dbgbus_vbif_rt)
2232 {
2233 if (dump_dbgbus_dpu)
2234 _dpu_dbg_dump_dpu_dbg_bus(&dpu_dbg_base.dbgbus_dpu);
2235
2236 if (dump_dbgbus_vbif_rt)
2237 _dpu_dbg_dump_vbif_dbg_bus(&dpu_dbg_base.dbgbus_vbif_rt);
2238 }
2239
2240 /**
2241 * _dpu_dump_work - deferred dump work function
2242 * @work: work structure
2243 */
_dpu_dump_work(struct work_struct * work)2244 static void _dpu_dump_work(struct work_struct *work)
2245 {
2246 _dpu_dump_array("dpudump_workitem",
2247 dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work,
2248 dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
2249 }
2250
dpu_dbg_dump(bool queue_work,const char * name,bool dump_dbgbus_dpu,bool dump_dbgbus_vbif_rt)2251 void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
2252 bool dump_dbgbus_vbif_rt)
2253 {
2254 if (queue_work && work_pending(&dpu_dbg_base.dump_work))
2255 return;
2256
2257 if (!queue_work) {
2258 _dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
2259 return;
2260 }
2261
2262 /* schedule work to dump later */
2263 dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = dump_dbgbus_dpu;
2264 dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
2265 dump_dbgbus_vbif_rt;
2266 schedule_work(&dpu_dbg_base.dump_work);
2267 }
2268
2269 /*
2270 * dpu_dbg_debugfs_open - debugfs open handler for debug dump
2271 * @inode: debugfs inode
2272 * @file: file handle
2273 */
dpu_dbg_debugfs_open(struct inode * inode,struct file * file)2274 static int dpu_dbg_debugfs_open(struct inode *inode, struct file *file)
2275 {
2276 /* non-seekable */
2277 file->f_mode &= ~(FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE);
2278 file->private_data = inode->i_private;
2279 return 0;
2280 }
2281
2282 /**
2283 * dpu_dbg_dump_write - debugfs write handler for debug dump
2284 * @file: file handler
2285 * @user_buf: user buffer content from debugfs
2286 * @count: size of user buffer
2287 * @ppos: position offset of user buffer
2288 */
dpu_dbg_dump_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2289 static ssize_t dpu_dbg_dump_write(struct file *file,
2290 const char __user *user_buf, size_t count, loff_t *ppos)
2291 {
2292 _dpu_dump_array("dump_debugfs", true, true);
2293 return count;
2294 }
2295
2296 static const struct file_operations dpu_dbg_dump_fops = {
2297 .open = dpu_dbg_debugfs_open,
2298 .write = dpu_dbg_dump_write,
2299 };
2300
dpu_dbg_debugfs_register(struct dentry * debugfs_root)2301 int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
2302 {
2303 static struct dpu_dbg_base *dbg = &dpu_dbg_base;
2304 char debug_name[80] = "";
2305
2306 if (!debugfs_root)
2307 return -EINVAL;
2308
2309 debugfs_create_file("dump", 0600, debugfs_root, NULL,
2310 &dpu_dbg_dump_fops);
2311
2312 if (dbg->dbgbus_dpu.entries) {
2313 dbg->dbgbus_dpu.cmn.name = DBGBUS_NAME_DPU;
2314 snprintf(debug_name, sizeof(debug_name), "%s_dbgbus",
2315 dbg->dbgbus_dpu.cmn.name);
2316 dbg->dbgbus_dpu.cmn.enable_mask = DEFAULT_DBGBUS_DPU;
2317 debugfs_create_u32(debug_name, 0600, debugfs_root,
2318 &dbg->dbgbus_dpu.cmn.enable_mask);
2319 }
2320
2321 if (dbg->dbgbus_vbif_rt.entries) {
2322 dbg->dbgbus_vbif_rt.cmn.name = DBGBUS_NAME_VBIF_RT;
2323 snprintf(debug_name, sizeof(debug_name), "%s_dbgbus",
2324 dbg->dbgbus_vbif_rt.cmn.name);
2325 dbg->dbgbus_vbif_rt.cmn.enable_mask = DEFAULT_DBGBUS_VBIFRT;
2326 debugfs_create_u32(debug_name, 0600, debugfs_root,
2327 &dbg->dbgbus_vbif_rt.cmn.enable_mask);
2328 }
2329
2330 return 0;
2331 }
2332
_dpu_dbg_debugfs_destroy(void)2333 static void _dpu_dbg_debugfs_destroy(void)
2334 {
2335 }
2336
dpu_dbg_init_dbg_buses(u32 hwversion)2337 void dpu_dbg_init_dbg_buses(u32 hwversion)
2338 {
2339 static struct dpu_dbg_base *dbg = &dpu_dbg_base;
2340
2341 memset(&dbg->dbgbus_dpu, 0, sizeof(dbg->dbgbus_dpu));
2342 memset(&dbg->dbgbus_vbif_rt, 0, sizeof(dbg->dbgbus_vbif_rt));
2343
2344 if (IS_MSM8998_TARGET(hwversion)) {
2345 dbg->dbgbus_dpu.entries = dbg_bus_dpu_8998;
2346 dbg->dbgbus_dpu.cmn.entries_size = ARRAY_SIZE(dbg_bus_dpu_8998);
2347 dbg->dbgbus_dpu.cmn.flags = DBGBUS_FLAGS_DSPP;
2348
2349 dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998;
2350 dbg->dbgbus_vbif_rt.cmn.entries_size =
2351 ARRAY_SIZE(vbif_dbg_bus_msm8998);
2352 } else if (IS_SDM845_TARGET(hwversion) || IS_SDM670_TARGET(hwversion)) {
2353 dbg->dbgbus_dpu.entries = dbg_bus_dpu_sdm845;
2354 dbg->dbgbus_dpu.cmn.entries_size =
2355 ARRAY_SIZE(dbg_bus_dpu_sdm845);
2356 dbg->dbgbus_dpu.cmn.flags = DBGBUS_FLAGS_DSPP;
2357
2358 /* vbif is unchanged vs 8998 */
2359 dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998;
2360 dbg->dbgbus_vbif_rt.cmn.entries_size =
2361 ARRAY_SIZE(vbif_dbg_bus_msm8998);
2362 } else {
2363 pr_err("unsupported chipset id %X\n", hwversion);
2364 }
2365 }
2366
dpu_dbg_init(struct device * dev)2367 int dpu_dbg_init(struct device *dev)
2368 {
2369 if (!dev) {
2370 pr_err("invalid params\n");
2371 return -EINVAL;
2372 }
2373
2374 INIT_LIST_HEAD(&dpu_dbg_base.reg_base_list);
2375 dpu_dbg_base.dev = dev;
2376
2377 INIT_WORK(&dpu_dbg_base.dump_work, _dpu_dump_work);
2378
2379 return 0;
2380 }
2381
2382 /**
2383 * dpu_dbg_destroy - destroy dpu debug facilities
2384 */
dpu_dbg_destroy(void)2385 void dpu_dbg_destroy(void)
2386 {
2387 _dpu_dbg_debugfs_destroy();
2388 }
2389
dpu_dbg_set_dpu_top_offset(u32 blk_off)2390 void dpu_dbg_set_dpu_top_offset(u32 blk_off)
2391 {
2392 dpu_dbg_base.dbgbus_dpu.top_blk_off = blk_off;
2393 }
2394
