1 /*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_GUC_H_
26 #define _INTEL_GUC_H_
27
28 #include "intel_uncore.h"
29 #include "intel_guc_fw.h"
30 #include "intel_guc_fwif.h"
31 #include "intel_guc_ct.h"
32 #include "intel_guc_log.h"
33 #include "intel_guc_reg.h"
34 #include "intel_uc_fw.h"
35 #include "i915_vma.h"
36
37 struct guc_preempt_work {
38 struct work_struct work;
39 struct intel_engine_cs *engine;
40 };
41
42 /*
43 * Top level structure of GuC. It handles firmware loading and manages client
44 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
45 * ExecList submission.
46 */
47 struct intel_guc {
48 struct intel_uc_fw fw;
49 struct intel_guc_log log;
50 struct intel_guc_ct ct;
51
52 /* Offset where Non-WOPCM memory starts. */
53 u32 ggtt_pin_bias;
54
55 /* Log snapshot if GuC errors during load */
56 struct drm_i915_gem_object *load_err_log;
57
58 /* intel_guc_recv interrupt related state */
59 spinlock_t irq_lock;
60 bool interrupts_enabled;
61 unsigned int msg_enabled_mask;
62
63 struct i915_vma *ads_vma;
64 struct i915_vma *stage_desc_pool;
65 void *stage_desc_pool_vaddr;
66 struct ida stage_ids;
67 struct i915_vma *shared_data;
68 void *shared_data_vaddr;
69
70 struct intel_guc_client *execbuf_client;
71 struct intel_guc_client *preempt_client;
72
73 struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
74 struct workqueue_struct *preempt_wq;
75
76 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
77 /* Cyclic counter mod pagesize */
78 u32 db_cacheline;
79
80 /* GuC's FW specific registers used in MMIO send */
81 struct {
82 u32 base;
83 unsigned int count;
84 enum forcewake_domains fw_domains;
85 } send_regs;
86
87 /* To serialize the intel_guc_send actions */
88 struct mutex send_mutex;
89
90 /* GuC's FW specific send function */
91 int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
92 u32 *response_buf, u32 response_buf_size);
93
94 /* GuC's FW specific event handler function */
95 void (*handler)(struct intel_guc *guc);
96
97 /* GuC's FW specific notify function */
98 void (*notify)(struct intel_guc *guc);
99 };
100
101 static
intel_guc_send(struct intel_guc * guc,const u32 * action,u32 len)102 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
103 {
104 return guc->send(guc, action, len, NULL, 0);
105 }
106
107 static inline int
intel_guc_send_and_receive(struct intel_guc * guc,const u32 * action,u32 len,u32 * response_buf,u32 response_buf_size)108 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
109 u32 *response_buf, u32 response_buf_size)
110 {
111 return guc->send(guc, action, len, response_buf, response_buf_size);
112 }
113
intel_guc_notify(struct intel_guc * guc)114 static inline void intel_guc_notify(struct intel_guc *guc)
115 {
116 guc->notify(guc);
117 }
118
intel_guc_to_host_event_handler(struct intel_guc * guc)119 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
120 {
121 guc->handler(guc);
122 }
123
124 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
125 #define GUC_GGTT_TOP 0xFEE00000
126
127 /**
128 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
129 * @guc: intel_guc structure.
130 * @vma: i915 graphics virtual memory area.
131 *
132 * GuC does not allow any gfx GGTT address that falls into range
133 * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
134 * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
135 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
136 * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
137 *
138 * Return: GGTT offset of the @vma.
139 */
intel_guc_ggtt_offset(struct intel_guc * guc,struct i915_vma * vma)140 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
141 struct i915_vma *vma)
142 {
143 u32 offset = i915_ggtt_offset(vma);
144
145 GEM_BUG_ON(offset < guc->ggtt_pin_bias);
146 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
147
148 return offset;
149 }
150
151 void intel_guc_init_early(struct intel_guc *guc);
152 void intel_guc_init_send_regs(struct intel_guc *guc);
153 void intel_guc_init_params(struct intel_guc *guc);
154 int intel_guc_init_misc(struct intel_guc *guc);
155 int intel_guc_init(struct intel_guc *guc);
156 void intel_guc_fini(struct intel_guc *guc);
157 void intel_guc_fini_misc(struct intel_guc *guc);
158 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
159 u32 *response_buf, u32 response_buf_size);
160 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
161 u32 *response_buf, u32 response_buf_size);
162 void intel_guc_to_host_event_handler(struct intel_guc *guc);
163 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
164 void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
165 void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg);
166 int intel_guc_sample_forcewake(struct intel_guc *guc);
167 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
168 int intel_guc_suspend(struct intel_guc *guc);
169 int intel_guc_resume(struct intel_guc *guc);
170 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
171
intel_guc_sanitize(struct intel_guc * guc)172 static inline int intel_guc_sanitize(struct intel_guc *guc)
173 {
174 intel_uc_fw_sanitize(&guc->fw);
175 return 0;
176 }
177
intel_guc_enable_msg(struct intel_guc * guc,u32 mask)178 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
179 {
180 spin_lock_irq(&guc->irq_lock);
181 guc->msg_enabled_mask |= mask;
182 spin_unlock_irq(&guc->irq_lock);
183 }
184
intel_guc_disable_msg(struct intel_guc * guc,u32 mask)185 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
186 {
187 spin_lock_irq(&guc->irq_lock);
188 guc->msg_enabled_mask &= ~mask;
189 spin_unlock_irq(&guc->irq_lock);
190 }
191
192 #endif
193
