1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // drivers/dma/imx-sdma.c
4 //
5 // This file contains a driver for the Freescale Smart DMA engine
6 //
7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 //
9 // Based on code from Freescale:
10 //
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12
13 #include <linux/init.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/bitops.h>
18 #include <linux/mm.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmapool.h>
28 #include <linux/firmware.h>
29 #include <linux/slab.h>
30 #include <linux/platform_device.h>
31 #include <linux/dmaengine.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_device.h>
35 #include <linux/of_dma.h>
36
37 #include <asm/irq.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
43
44 #include "dmaengine.h"
45 #include "virt-dma.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * p_2_p watermark_level description
128 * Bits Name Description
129 * 0-7 Lower WML Lower watermark level
130 * 8 PS 1: Pad Swallowing
131 * 0: No Pad Swallowing
132 * 9 PA 1: Pad Adding
133 * 0: No Pad Adding
134 * 10 SPDIF If this bit is set both source
135 * and destination are on SPBA
136 * 11 Source Bit(SP) 1: Source on SPBA
137 * 0: Source on AIPS
138 * 12 Destination Bit(DP) 1: Destination on SPBA
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
143 * which Pad adding/Swallowing
144 * must be done. It must be odd.
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
146 * LWML event mask
147 * 0: LWE in EVENTS register
148 * 1: LWE in EVENTS2 register
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
150 * HWML event mask
151 * 0: HWE in EVENTS register
152 * 1: HWE in EVENTS2 register
153 * 30 --------- MUST BE 0
154 * 31 CONT 1: Amount of samples to be
155 * transferred is unknown and
156 * script will keep on
157 * transferring samples as long as
158 * both events are detected and
159 * script must be manually stopped
160 * by the application
161 * 0: The amount of samples to be
162 * transferred is equal to the
163 * count field of mode word
164 */
165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
166 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
167 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
169 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
170 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
175
176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
179
180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
181 BIT(DMA_MEM_TO_DEV) | \
182 BIT(DMA_DEV_TO_DEV))
183
184 /*
185 * Mode/Count of data node descriptors - IPCv2
186 */
187 struct sdma_mode_count {
188 #define SDMA_BD_MAX_CNT 0xffff
189 u32 count : 16; /* size of the buffer pointed by this BD */
190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
191 u32 command : 8; /* command mostly used for channel 0 */
192 };
193
194 /*
195 * Buffer descriptor
196 */
197 struct sdma_buffer_descriptor {
198 struct sdma_mode_count mode;
199 u32 buffer_addr; /* address of the buffer described */
200 u32 ext_buffer_addr; /* extended buffer address */
201 } __attribute__ ((packed));
202
203 /**
204 * struct sdma_channel_control - Channel control Block
205 *
206 * @current_bd_ptr: current buffer descriptor processed
207 * @base_bd_ptr: first element of buffer descriptor array
208 * @unused: padding. The SDMA engine expects an array of 128 byte
209 * control blocks
210 */
211 struct sdma_channel_control {
212 u32 current_bd_ptr;
213 u32 base_bd_ptr;
214 u32 unused[2];
215 } __attribute__ ((packed));
216
217 /**
218 * struct sdma_state_registers - SDMA context for a channel
219 *
220 * @pc: program counter
221 * @unused1: unused
222 * @t: test bit: status of arithmetic & test instruction
223 * @rpc: return program counter
224 * @unused0: unused
225 * @sf: source fault while loading data
226 * @spc: loop start program counter
227 * @unused2: unused
228 * @df: destination fault while storing data
229 * @epc: loop end program counter
230 * @lm: loop mode
231 */
232 struct sdma_state_registers {
233 u32 pc :14;
234 u32 unused1: 1;
235 u32 t : 1;
236 u32 rpc :14;
237 u32 unused0: 1;
238 u32 sf : 1;
239 u32 spc :14;
240 u32 unused2: 1;
241 u32 df : 1;
242 u32 epc :14;
243 u32 lm : 2;
244 } __attribute__ ((packed));
245
246 /**
247 * struct sdma_context_data - sdma context specific to a channel
248 *
249 * @channel_state: channel state bits
250 * @gReg: general registers
251 * @mda: burst dma destination address register
252 * @msa: burst dma source address register
253 * @ms: burst dma status register
254 * @md: burst dma data register
255 * @pda: peripheral dma destination address register
256 * @psa: peripheral dma source address register
257 * @ps: peripheral dma status register
258 * @pd: peripheral dma data register
259 * @ca: CRC polynomial register
260 * @cs: CRC accumulator register
261 * @dda: dedicated core destination address register
262 * @dsa: dedicated core source address register
263 * @ds: dedicated core status register
264 * @dd: dedicated core data register
265 * @scratch0: 1st word of dedicated ram for context switch
266 * @scratch1: 2nd word of dedicated ram for context switch
267 * @scratch2: 3rd word of dedicated ram for context switch
268 * @scratch3: 4th word of dedicated ram for context switch
269 * @scratch4: 5th word of dedicated ram for context switch
270 * @scratch5: 6th word of dedicated ram for context switch
271 * @scratch6: 7th word of dedicated ram for context switch
272 * @scratch7: 8th word of dedicated ram for context switch
273 */
274 struct sdma_context_data {
275 struct sdma_state_registers channel_state;
276 u32 gReg[8];
277 u32 mda;
278 u32 msa;
279 u32 ms;
280 u32 md;
281 u32 pda;
282 u32 psa;
283 u32 ps;
284 u32 pd;
285 u32 ca;
286 u32 cs;
287 u32 dda;
288 u32 dsa;
289 u32 ds;
290 u32 dd;
291 u32 scratch0;
292 u32 scratch1;
293 u32 scratch2;
294 u32 scratch3;
295 u32 scratch4;
296 u32 scratch5;
297 u32 scratch6;
298 u32 scratch7;
299 } __attribute__ ((packed));
300
301
302 struct sdma_engine;
303
304 /**
305 * struct sdma_desc - descriptor structor for one transfer
306 * @vd: descriptor for virt dma
307 * @num_bd: number of descriptors currently handling
308 * @bd_phys: physical address of bd
309 * @buf_tail: ID of the buffer that was processed
310 * @buf_ptail: ID of the previous buffer that was processed
311 * @period_len: period length, used in cyclic.
312 * @chn_real_count: the real count updated from bd->mode.count
313 * @chn_count: the transfer count set
314 * @sdmac: sdma_channel pointer
315 * @bd: pointer of allocate bd
316 */
317 struct sdma_desc {
318 struct virt_dma_desc vd;
319 unsigned int num_bd;
320 dma_addr_t bd_phys;
321 unsigned int buf_tail;
322 unsigned int buf_ptail;
323 unsigned int period_len;
324 unsigned int chn_real_count;
325 unsigned int chn_count;
326 struct sdma_channel *sdmac;
327 struct sdma_buffer_descriptor *bd;
328 };
329
330 /**
331 * struct sdma_channel - housekeeping for a SDMA channel
332 *
333 * @vc: virt_dma base structure
334 * @desc: sdma description including vd and other special member
335 * @sdma: pointer to the SDMA engine for this channel
336 * @channel: the channel number, matches dmaengine chan_id + 1
337 * @direction: transfer type. Needed for setting SDMA script
338 * @peripheral_type: Peripheral type. Needed for setting SDMA script
339 * @event_id0: aka dma request line
340 * @event_id1: for channels that use 2 events
341 * @word_size: peripheral access size
342 * @pc_from_device: script address for those device_2_memory
343 * @pc_to_device: script address for those memory_2_device
344 * @device_to_device: script address for those device_2_device
345 * @pc_to_pc: script address for those memory_2_memory
346 * @flags: loop mode or not
347 * @per_address: peripheral source or destination address in common case
348 * destination address in p_2_p case
349 * @per_address2: peripheral source address in p_2_p case
350 * @event_mask: event mask used in p_2_p script
351 * @watermark_level: value for gReg[7], some script will extend it from
352 * basic watermark such as p_2_p
353 * @shp_addr: value for gReg[6]
354 * @per_addr: value for gReg[2]
355 * @status: status of dma channel
356 * @data: specific sdma interface structure
357 * @bd_pool: dma_pool for bd
358 */
359 struct sdma_channel {
360 struct virt_dma_chan vc;
361 struct sdma_desc *desc;
362 struct sdma_engine *sdma;
363 unsigned int channel;
364 enum dma_transfer_direction direction;
365 enum sdma_peripheral_type peripheral_type;
366 unsigned int event_id0;
367 unsigned int event_id1;
368 enum dma_slave_buswidth word_size;
369 unsigned int pc_from_device, pc_to_device;
370 unsigned int device_to_device;
371 unsigned int pc_to_pc;
372 unsigned long flags;
373 dma_addr_t per_address, per_address2;
374 unsigned long event_mask[2];
375 unsigned long watermark_level;
376 u32 shp_addr, per_addr;
377 enum dma_status status;
378 struct imx_dma_data data;
379 struct dma_pool *bd_pool;
380 };
381
382 #define IMX_DMA_SG_LOOP BIT(0)
383
384 #define MAX_DMA_CHANNELS 32
385 #define MXC_SDMA_DEFAULT_PRIORITY 1
386 #define MXC_SDMA_MIN_PRIORITY 1
387 #define MXC_SDMA_MAX_PRIORITY 7
388
389 #define SDMA_FIRMWARE_MAGIC 0x414d4453
390
391 /**
392 * struct sdma_firmware_header - Layout of the firmware image
393 *
394 * @magic: "SDMA"
395 * @version_major: increased whenever layout of struct
396 * sdma_script_start_addrs changes.
397 * @version_minor: firmware minor version (for binary compatible changes)
398 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
399 * @num_script_addrs: Number of script addresses in this image
400 * @ram_code_start: offset of SDMA ram image in this firmware image
401 * @ram_code_size: size of SDMA ram image
402 * @script_addrs: Stores the start address of the SDMA scripts
403 * (in SDMA memory space)
404 */
405 struct sdma_firmware_header {
406 u32 magic;
407 u32 version_major;
408 u32 version_minor;
409 u32 script_addrs_start;
410 u32 num_script_addrs;
411 u32 ram_code_start;
412 u32 ram_code_size;
413 };
414
415 struct sdma_driver_data {
416 int chnenbl0;
417 int num_events;
418 struct sdma_script_start_addrs *script_addrs;
419 };
420
421 struct sdma_engine {
422 struct device *dev;
423 struct device_dma_parameters dma_parms;
424 struct sdma_channel channel[MAX_DMA_CHANNELS];
425 struct sdma_channel_control *channel_control;
426 void __iomem *regs;
427 struct sdma_context_data *context;
428 dma_addr_t context_phys;
429 struct dma_device dma_device;
430 struct clk *clk_ipg;
431 struct clk *clk_ahb;
432 spinlock_t channel_0_lock;
433 u32 script_number;
434 struct sdma_script_start_addrs *script_addrs;
435 const struct sdma_driver_data *drvdata;
436 u32 spba_start_addr;
437 u32 spba_end_addr;
438 unsigned int irq;
439 dma_addr_t bd0_phys;
440 struct sdma_buffer_descriptor *bd0;
441 };
442
443 static struct sdma_driver_data sdma_imx31 = {
444 .chnenbl0 = SDMA_CHNENBL0_IMX31,
445 .num_events = 32,
446 };
447
448 static struct sdma_script_start_addrs sdma_script_imx25 = {
449 .ap_2_ap_addr = 729,
450 .uart_2_mcu_addr = 904,
451 .per_2_app_addr = 1255,
452 .mcu_2_app_addr = 834,
453 .uartsh_2_mcu_addr = 1120,
454 .per_2_shp_addr = 1329,
455 .mcu_2_shp_addr = 1048,
456 .ata_2_mcu_addr = 1560,
457 .mcu_2_ata_addr = 1479,
458 .app_2_per_addr = 1189,
459 .app_2_mcu_addr = 770,
460 .shp_2_per_addr = 1407,
461 .shp_2_mcu_addr = 979,
462 };
463
464 static struct sdma_driver_data sdma_imx25 = {
465 .chnenbl0 = SDMA_CHNENBL0_IMX35,
466 .num_events = 48,
467 .script_addrs = &sdma_script_imx25,
468 };
469
470 static struct sdma_driver_data sdma_imx35 = {
471 .chnenbl0 = SDMA_CHNENBL0_IMX35,
472 .num_events = 48,
473 };
474
475 static struct sdma_script_start_addrs sdma_script_imx51 = {
476 .ap_2_ap_addr = 642,
477 .uart_2_mcu_addr = 817,
478 .mcu_2_app_addr = 747,
479 .mcu_2_shp_addr = 961,
480 .ata_2_mcu_addr = 1473,
481 .mcu_2_ata_addr = 1392,
482 .app_2_per_addr = 1033,
483 .app_2_mcu_addr = 683,
484 .shp_2_per_addr = 1251,
485 .shp_2_mcu_addr = 892,
486 };
487
488 static struct sdma_driver_data sdma_imx51 = {
489 .chnenbl0 = SDMA_CHNENBL0_IMX35,
490 .num_events = 48,
491 .script_addrs = &sdma_script_imx51,
492 };
493
494 static struct sdma_script_start_addrs sdma_script_imx53 = {
495 .ap_2_ap_addr = 642,
496 .app_2_mcu_addr = 683,
497 .mcu_2_app_addr = 747,
498 .uart_2_mcu_addr = 817,
499 .shp_2_mcu_addr = 891,
500 .mcu_2_shp_addr = 960,
501 .uartsh_2_mcu_addr = 1032,
502 .spdif_2_mcu_addr = 1100,
503 .mcu_2_spdif_addr = 1134,
504 .firi_2_mcu_addr = 1193,
505 .mcu_2_firi_addr = 1290,
506 };
507
508 static struct sdma_driver_data sdma_imx53 = {
509 .chnenbl0 = SDMA_CHNENBL0_IMX35,
510 .num_events = 48,
511 .script_addrs = &sdma_script_imx53,
512 };
513
514 static struct sdma_script_start_addrs sdma_script_imx6q = {
515 .ap_2_ap_addr = 642,
516 .uart_2_mcu_addr = 817,
517 .mcu_2_app_addr = 747,
518 .per_2_per_addr = 6331,
519 .uartsh_2_mcu_addr = 1032,
520 .mcu_2_shp_addr = 960,
521 .app_2_mcu_addr = 683,
522 .shp_2_mcu_addr = 891,
523 .spdif_2_mcu_addr = 1100,
524 .mcu_2_spdif_addr = 1134,
525 };
526
527 static struct sdma_driver_data sdma_imx6q = {
528 .chnenbl0 = SDMA_CHNENBL0_IMX35,
529 .num_events = 48,
530 .script_addrs = &sdma_script_imx6q,
531 };
532
533 static struct sdma_script_start_addrs sdma_script_imx7d = {
534 .ap_2_ap_addr = 644,
535 .uart_2_mcu_addr = 819,
536 .mcu_2_app_addr = 749,
537 .uartsh_2_mcu_addr = 1034,
538 .mcu_2_shp_addr = 962,
539 .app_2_mcu_addr = 685,
540 .shp_2_mcu_addr = 893,
541 .spdif_2_mcu_addr = 1102,
542 .mcu_2_spdif_addr = 1136,
543 };
544
545 static struct sdma_driver_data sdma_imx7d = {
546 .chnenbl0 = SDMA_CHNENBL0_IMX35,
547 .num_events = 48,
548 .script_addrs = &sdma_script_imx7d,
549 };
550
551 static const struct platform_device_id sdma_devtypes[] = {
552 {
553 .name = "imx25-sdma",
554 .driver_data = (unsigned long)&sdma_imx25,
555 }, {
556 .name = "imx31-sdma",
557 .driver_data = (unsigned long)&sdma_imx31,
558 }, {
559 .name = "imx35-sdma",
560 .driver_data = (unsigned long)&sdma_imx35,
561 }, {
562 .name = "imx51-sdma",
563 .driver_data = (unsigned long)&sdma_imx51,
564 }, {
565 .name = "imx53-sdma",
566 .driver_data = (unsigned long)&sdma_imx53,
567 }, {
568 .name = "imx6q-sdma",
569 .driver_data = (unsigned long)&sdma_imx6q,
570 }, {
571 .name = "imx7d-sdma",
572 .driver_data = (unsigned long)&sdma_imx7d,
573 }, {
574 /* sentinel */
575 }
576 };
577 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
578
579 static const struct of_device_id sdma_dt_ids[] = {
580 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
581 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
582 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
583 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
584 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
585 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
586 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
587 { /* sentinel */ }
588 };
589 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
590
591 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
592 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
593 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
594 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
595
chnenbl_ofs(struct sdma_engine * sdma,unsigned int event)596 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
597 {
598 u32 chnenbl0 = sdma->drvdata->chnenbl0;
599 return chnenbl0 + event * 4;
600 }
601
sdma_config_ownership(struct sdma_channel * sdmac,bool event_override,bool mcu_override,bool dsp_override)602 static int sdma_config_ownership(struct sdma_channel *sdmac,
603 bool event_override, bool mcu_override, bool dsp_override)
604 {
605 struct sdma_engine *sdma = sdmac->sdma;
606 int channel = sdmac->channel;
607 unsigned long evt, mcu, dsp;
608
609 if (event_override && mcu_override && dsp_override)
610 return -EINVAL;
611
612 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
613 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
614 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
615
616 if (dsp_override)
617 __clear_bit(channel, &dsp);
618 else
619 __set_bit(channel, &dsp);
620
621 if (event_override)
622 __clear_bit(channel, &evt);
623 else
624 __set_bit(channel, &evt);
625
626 if (mcu_override)
627 __clear_bit(channel, &mcu);
628 else
629 __set_bit(channel, &mcu);
630
631 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
632 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
633 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
634
635 return 0;
636 }
637
sdma_enable_channel(struct sdma_engine * sdma,int channel)638 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
639 {
640 writel(BIT(channel), sdma->regs + SDMA_H_START);
641 }
642
643 /*
644 * sdma_run_channel0 - run a channel and wait till it's done
645 */
sdma_run_channel0(struct sdma_engine * sdma)646 static int sdma_run_channel0(struct sdma_engine *sdma)
647 {
648 int ret;
649 u32 reg;
650
651 sdma_enable_channel(sdma, 0);
652
653 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
654 reg, !(reg & 1), 1, 500);
655 if (ret)
656 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
657
658 /* Set bits of CONFIG register with dynamic context switching */
659 if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
660 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
661
662 return ret;
663 }
664
sdma_load_script(struct sdma_engine * sdma,void * buf,int size,u32 address)665 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
666 u32 address)
667 {
668 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
669 void *buf_virt;
670 dma_addr_t buf_phys;
671 int ret;
672 unsigned long flags;
673
674 buf_virt = dma_alloc_coherent(NULL,
675 size,
676 &buf_phys, GFP_KERNEL);
677 if (!buf_virt) {
678 return -ENOMEM;
679 }
680
681 spin_lock_irqsave(&sdma->channel_0_lock, flags);
682
683 bd0->mode.command = C0_SETPM;
684 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
685 bd0->mode.count = size / 2;
686 bd0->buffer_addr = buf_phys;
687 bd0->ext_buffer_addr = address;
688
689 memcpy(buf_virt, buf, size);
690
691 ret = sdma_run_channel0(sdma);
692
693 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
694
695 dma_free_coherent(NULL, size, buf_virt, buf_phys);
696
697 return ret;
698 }
699
sdma_event_enable(struct sdma_channel * sdmac,unsigned int event)700 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
701 {
702 struct sdma_engine *sdma = sdmac->sdma;
703 int channel = sdmac->channel;
704 unsigned long val;
705 u32 chnenbl = chnenbl_ofs(sdma, event);
706
707 val = readl_relaxed(sdma->regs + chnenbl);
708 __set_bit(channel, &val);
709 writel_relaxed(val, sdma->regs + chnenbl);
710 }
711
sdma_event_disable(struct sdma_channel * sdmac,unsigned int event)712 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
713 {
714 struct sdma_engine *sdma = sdmac->sdma;
715 int channel = sdmac->channel;
716 u32 chnenbl = chnenbl_ofs(sdma, event);
717 unsigned long val;
718
719 val = readl_relaxed(sdma->regs + chnenbl);
720 __clear_bit(channel, &val);
721 writel_relaxed(val, sdma->regs + chnenbl);
722 }
723
to_sdma_desc(struct dma_async_tx_descriptor * t)724 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
725 {
726 return container_of(t, struct sdma_desc, vd.tx);
727 }
728
sdma_start_desc(struct sdma_channel * sdmac)729 static void sdma_start_desc(struct sdma_channel *sdmac)
730 {
731 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
732 struct sdma_desc *desc;
733 struct sdma_engine *sdma = sdmac->sdma;
734 int channel = sdmac->channel;
735
736 if (!vd) {
737 sdmac->desc = NULL;
738 return;
739 }
740 sdmac->desc = desc = to_sdma_desc(&vd->tx);
741 /*
742 * Do not delete the node in desc_issued list in cyclic mode, otherwise
743 * the desc allocated will never be freed in vchan_dma_desc_free_list
744 */
745 if (!(sdmac->flags & IMX_DMA_SG_LOOP))
746 list_del(&vd->node);
747
748 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
749 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
750 sdma_enable_channel(sdma, sdmac->channel);
751 }
752
sdma_update_channel_loop(struct sdma_channel * sdmac)753 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
754 {
755 struct sdma_buffer_descriptor *bd;
756 int error = 0;
757 enum dma_status old_status = sdmac->status;
758
759 /*
760 * loop mode. Iterate over descriptors, re-setup them and
761 * call callback function.
762 */
763 while (sdmac->desc) {
764 struct sdma_desc *desc = sdmac->desc;
765
766 bd = &desc->bd[desc->buf_tail];
767
768 if (bd->mode.status & BD_DONE)
769 break;
770
771 if (bd->mode.status & BD_RROR) {
772 bd->mode.status &= ~BD_RROR;
773 sdmac->status = DMA_ERROR;
774 error = -EIO;
775 }
776
777 /*
778 * We use bd->mode.count to calculate the residue, since contains
779 * the number of bytes present in the current buffer descriptor.
780 */
781
782 desc->chn_real_count = bd->mode.count;
783 bd->mode.status |= BD_DONE;
784 bd->mode.count = desc->period_len;
785 desc->buf_ptail = desc->buf_tail;
786 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
787
788 /*
789 * The callback is called from the interrupt context in order
790 * to reduce latency and to avoid the risk of altering the
791 * SDMA transaction status by the time the client tasklet is
792 * executed.
793 */
794 spin_unlock(&sdmac->vc.lock);
795 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
796 spin_lock(&sdmac->vc.lock);
797
798 if (error)
799 sdmac->status = old_status;
800 }
801 }
802
mxc_sdma_handle_channel_normal(struct sdma_channel * data)803 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
804 {
805 struct sdma_channel *sdmac = (struct sdma_channel *) data;
806 struct sdma_buffer_descriptor *bd;
807 int i, error = 0;
808
809 sdmac->desc->chn_real_count = 0;
810 /*
811 * non loop mode. Iterate over all descriptors, collect
812 * errors and call callback function
813 */
814 for (i = 0; i < sdmac->desc->num_bd; i++) {
815 bd = &sdmac->desc->bd[i];
816
817 if (bd->mode.status & (BD_DONE | BD_RROR))
818 error = -EIO;
819 sdmac->desc->chn_real_count += bd->mode.count;
820 }
821
822 if (error)
823 sdmac->status = DMA_ERROR;
824 else
825 sdmac->status = DMA_COMPLETE;
826 }
827
sdma_int_handler(int irq,void * dev_id)828 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
829 {
830 struct sdma_engine *sdma = dev_id;
831 unsigned long stat;
832
833 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
834 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
835 /* channel 0 is special and not handled here, see run_channel0() */
836 stat &= ~1;
837
838 while (stat) {
839 int channel = fls(stat) - 1;
840 struct sdma_channel *sdmac = &sdma->channel[channel];
841 struct sdma_desc *desc;
842
843 spin_lock(&sdmac->vc.lock);
844 desc = sdmac->desc;
845 if (desc) {
846 if (sdmac->flags & IMX_DMA_SG_LOOP) {
847 sdma_update_channel_loop(sdmac);
848 } else {
849 mxc_sdma_handle_channel_normal(sdmac);
850 vchan_cookie_complete(&desc->vd);
851 sdma_start_desc(sdmac);
852 }
853 }
854
855 spin_unlock(&sdmac->vc.lock);
856 __clear_bit(channel, &stat);
857 }
858
859 return IRQ_HANDLED;
860 }
861
862 /*
863 * sets the pc of SDMA script according to the peripheral type
864 */
sdma_get_pc(struct sdma_channel * sdmac,enum sdma_peripheral_type peripheral_type)865 static void sdma_get_pc(struct sdma_channel *sdmac,
866 enum sdma_peripheral_type peripheral_type)
867 {
868 struct sdma_engine *sdma = sdmac->sdma;
869 int per_2_emi = 0, emi_2_per = 0;
870 /*
871 * These are needed once we start to support transfers between
872 * two peripherals or memory-to-memory transfers
873 */
874 int per_2_per = 0, emi_2_emi = 0;
875
876 sdmac->pc_from_device = 0;
877 sdmac->pc_to_device = 0;
878 sdmac->device_to_device = 0;
879 sdmac->pc_to_pc = 0;
880
881 switch (peripheral_type) {
882 case IMX_DMATYPE_MEMORY:
883 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
884 break;
885 case IMX_DMATYPE_DSP:
886 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
887 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
888 break;
889 case IMX_DMATYPE_FIRI:
890 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
891 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
892 break;
893 case IMX_DMATYPE_UART:
894 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
895 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
896 break;
897 case IMX_DMATYPE_UART_SP:
898 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
899 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
900 break;
901 case IMX_DMATYPE_ATA:
902 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
903 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
904 break;
905 case IMX_DMATYPE_CSPI:
906 case IMX_DMATYPE_EXT:
907 case IMX_DMATYPE_SSI:
908 case IMX_DMATYPE_SAI:
909 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
910 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
911 break;
912 case IMX_DMATYPE_SSI_DUAL:
913 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
914 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
915 break;
916 case IMX_DMATYPE_SSI_SP:
917 case IMX_DMATYPE_MMC:
918 case IMX_DMATYPE_SDHC:
919 case IMX_DMATYPE_CSPI_SP:
920 case IMX_DMATYPE_ESAI:
921 case IMX_DMATYPE_MSHC_SP:
922 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
923 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
924 break;
925 case IMX_DMATYPE_ASRC:
926 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
927 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
928 per_2_per = sdma->script_addrs->per_2_per_addr;
929 break;
930 case IMX_DMATYPE_ASRC_SP:
931 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
932 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
933 per_2_per = sdma->script_addrs->per_2_per_addr;
934 break;
935 case IMX_DMATYPE_MSHC:
936 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
937 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
938 break;
939 case IMX_DMATYPE_CCM:
940 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
941 break;
942 case IMX_DMATYPE_SPDIF:
943 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
944 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
945 break;
946 case IMX_DMATYPE_IPU_MEMORY:
947 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
948 break;
949 default:
950 break;
951 }
952
953 sdmac->pc_from_device = per_2_emi;
954 sdmac->pc_to_device = emi_2_per;
955 sdmac->device_to_device = per_2_per;
956 sdmac->pc_to_pc = emi_2_emi;
957 }
958
sdma_load_context(struct sdma_channel * sdmac)959 static int sdma_load_context(struct sdma_channel *sdmac)
960 {
961 struct sdma_engine *sdma = sdmac->sdma;
962 int channel = sdmac->channel;
963 int load_address;
964 struct sdma_context_data *context = sdma->context;
965 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
966 int ret;
967 unsigned long flags;
968
969 if (sdmac->direction == DMA_DEV_TO_MEM)
970 load_address = sdmac->pc_from_device;
971 else if (sdmac->direction == DMA_DEV_TO_DEV)
972 load_address = sdmac->device_to_device;
973 else if (sdmac->direction == DMA_MEM_TO_MEM)
974 load_address = sdmac->pc_to_pc;
975 else
976 load_address = sdmac->pc_to_device;
977
978 if (load_address < 0)
979 return load_address;
980
981 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
982 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
983 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
984 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
985 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
986 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
987
988 spin_lock_irqsave(&sdma->channel_0_lock, flags);
989
990 memset(context, 0, sizeof(*context));
991 context->channel_state.pc = load_address;
992
993 /* Send by context the event mask,base address for peripheral
994 * and watermark level
995 */
996 context->gReg[0] = sdmac->event_mask[1];
997 context->gReg[1] = sdmac->event_mask[0];
998 context->gReg[2] = sdmac->per_addr;
999 context->gReg[6] = sdmac->shp_addr;
1000 context->gReg[7] = sdmac->watermark_level;
1001
1002 bd0->mode.command = C0_SETDM;
1003 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
1004 bd0->mode.count = sizeof(*context) / 4;
1005 bd0->buffer_addr = sdma->context_phys;
1006 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1007 ret = sdma_run_channel0(sdma);
1008
1009 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1010
1011 return ret;
1012 }
1013
to_sdma_chan(struct dma_chan * chan)1014 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1015 {
1016 return container_of(chan, struct sdma_channel, vc.chan);
1017 }
1018
sdma_disable_channel(struct dma_chan * chan)1019 static int sdma_disable_channel(struct dma_chan *chan)
1020 {
1021 struct sdma_channel *sdmac = to_sdma_chan(chan);
1022 struct sdma_engine *sdma = sdmac->sdma;
1023 int channel = sdmac->channel;
1024
1025 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1026 sdmac->status = DMA_ERROR;
1027
1028 return 0;
1029 }
1030
sdma_disable_channel_with_delay(struct dma_chan * chan)1031 static int sdma_disable_channel_with_delay(struct dma_chan *chan)
1032 {
1033 struct sdma_channel *sdmac = to_sdma_chan(chan);
1034 unsigned long flags;
1035 LIST_HEAD(head);
1036
1037 sdma_disable_channel(chan);
1038 spin_lock_irqsave(&sdmac->vc.lock, flags);
1039 vchan_get_all_descriptors(&sdmac->vc, &head);
1040 sdmac->desc = NULL;
1041 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1042 vchan_dma_desc_free_list(&sdmac->vc, &head);
1043
1044 /*
1045 * According to NXP R&D team a delay of one BD SDMA cost time
1046 * (maximum is 1ms) should be added after disable of the channel
1047 * bit, to ensure SDMA core has really been stopped after SDMA
1048 * clients call .device_terminate_all.
1049 */
1050 mdelay(1);
1051
1052 return 0;
1053 }
1054
sdma_set_watermarklevel_for_p2p(struct sdma_channel * sdmac)1055 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1056 {
1057 struct sdma_engine *sdma = sdmac->sdma;
1058
1059 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1060 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1061
1062 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1063 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1064
1065 if (sdmac->event_id0 > 31)
1066 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1067
1068 if (sdmac->event_id1 > 31)
1069 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1070
1071 /*
1072 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1073 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1074 * r0(event_mask[1]) and r1(event_mask[0]).
1075 */
1076 if (lwml > hwml) {
1077 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1078 SDMA_WATERMARK_LEVEL_HWML);
1079 sdmac->watermark_level |= hwml;
1080 sdmac->watermark_level |= lwml << 16;
1081 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1082 }
1083
1084 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1085 sdmac->per_address2 <= sdma->spba_end_addr)
1086 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1087
1088 if (sdmac->per_address >= sdma->spba_start_addr &&
1089 sdmac->per_address <= sdma->spba_end_addr)
1090 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1091
1092 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1093 }
1094
sdma_config_channel(struct dma_chan * chan)1095 static int sdma_config_channel(struct dma_chan *chan)
1096 {
1097 struct sdma_channel *sdmac = to_sdma_chan(chan);
1098 int ret;
1099
1100 sdma_disable_channel(chan);
1101
1102 sdmac->event_mask[0] = 0;
1103 sdmac->event_mask[1] = 0;
1104 sdmac->shp_addr = 0;
1105 sdmac->per_addr = 0;
1106
1107 if (sdmac->event_id0) {
1108 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1109 return -EINVAL;
1110 sdma_event_enable(sdmac, sdmac->event_id0);
1111 }
1112
1113 if (sdmac->event_id1) {
1114 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1115 return -EINVAL;
1116 sdma_event_enable(sdmac, sdmac->event_id1);
1117 }
1118
1119 switch (sdmac->peripheral_type) {
1120 case IMX_DMATYPE_DSP:
1121 sdma_config_ownership(sdmac, false, true, true);
1122 break;
1123 case IMX_DMATYPE_MEMORY:
1124 sdma_config_ownership(sdmac, false, true, false);
1125 break;
1126 default:
1127 sdma_config_ownership(sdmac, true, true, false);
1128 break;
1129 }
1130
1131 sdma_get_pc(sdmac, sdmac->peripheral_type);
1132
1133 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1134 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1135 /* Handle multiple event channels differently */
1136 if (sdmac->event_id1) {
1137 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1138 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1139 sdma_set_watermarklevel_for_p2p(sdmac);
1140 } else
1141 __set_bit(sdmac->event_id0, sdmac->event_mask);
1142
1143 /* Address */
1144 sdmac->shp_addr = sdmac->per_address;
1145 sdmac->per_addr = sdmac->per_address2;
1146 } else {
1147 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1148 }
1149
1150 ret = sdma_load_context(sdmac);
1151
1152 return ret;
1153 }
1154
sdma_set_channel_priority(struct sdma_channel * sdmac,unsigned int priority)1155 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1156 unsigned int priority)
1157 {
1158 struct sdma_engine *sdma = sdmac->sdma;
1159 int channel = sdmac->channel;
1160
1161 if (priority < MXC_SDMA_MIN_PRIORITY
1162 || priority > MXC_SDMA_MAX_PRIORITY) {
1163 return -EINVAL;
1164 }
1165
1166 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1167
1168 return 0;
1169 }
1170
sdma_request_channel0(struct sdma_engine * sdma)1171 static int sdma_request_channel0(struct sdma_engine *sdma)
1172 {
1173 int ret = -EBUSY;
1174
1175 sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
1176 GFP_NOWAIT);
1177 if (!sdma->bd0) {
1178 ret = -ENOMEM;
1179 goto out;
1180 }
1181
1182 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1183 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1184
1185 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1186 return 0;
1187 out:
1188
1189 return ret;
1190 }
1191
1192
sdma_alloc_bd(struct sdma_desc * desc)1193 static int sdma_alloc_bd(struct sdma_desc *desc)
1194 {
1195 int ret = 0;
1196
1197 desc->bd = dma_pool_alloc(desc->sdmac->bd_pool, GFP_NOWAIT,
1198 &desc->bd_phys);
1199 if (!desc->bd) {
1200 ret = -ENOMEM;
1201 goto out;
1202 }
1203 out:
1204 return ret;
1205 }
1206
sdma_free_bd(struct sdma_desc * desc)1207 static void sdma_free_bd(struct sdma_desc *desc)
1208 {
1209 dma_pool_free(desc->sdmac->bd_pool, desc->bd, desc->bd_phys);
1210 }
1211
sdma_desc_free(struct virt_dma_desc * vd)1212 static void sdma_desc_free(struct virt_dma_desc *vd)
1213 {
1214 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1215
1216 sdma_free_bd(desc);
1217 kfree(desc);
1218 }
1219
sdma_alloc_chan_resources(struct dma_chan * chan)1220 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1221 {
1222 struct sdma_channel *sdmac = to_sdma_chan(chan);
1223 struct imx_dma_data *data = chan->private;
1224 struct imx_dma_data mem_data;
1225 int prio, ret;
1226
1227 /*
1228 * MEMCPY may never setup chan->private by filter function such as
1229 * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1230 * Please note in any other slave case, you have to setup chan->private
1231 * with 'struct imx_dma_data' in your own filter function if you want to
1232 * request dma channel by dma_request_channel() rather than
1233 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1234 * to warn you to correct your filter function.
1235 */
1236 if (!data) {
1237 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1238 mem_data.priority = 2;
1239 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1240 mem_data.dma_request = 0;
1241 mem_data.dma_request2 = 0;
1242 data = &mem_data;
1243
1244 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1245 }
1246
1247 switch (data->priority) {
1248 case DMA_PRIO_HIGH:
1249 prio = 3;
1250 break;
1251 case DMA_PRIO_MEDIUM:
1252 prio = 2;
1253 break;
1254 case DMA_PRIO_LOW:
1255 default:
1256 prio = 1;
1257 break;
1258 }
1259
1260 sdmac->peripheral_type = data->peripheral_type;
1261 sdmac->event_id0 = data->dma_request;
1262 sdmac->event_id1 = data->dma_request2;
1263
1264 ret = clk_enable(sdmac->sdma->clk_ipg);
1265 if (ret)
1266 return ret;
1267 ret = clk_enable(sdmac->sdma->clk_ahb);
1268 if (ret)
1269 goto disable_clk_ipg;
1270
1271 ret = sdma_set_channel_priority(sdmac, prio);
1272 if (ret)
1273 goto disable_clk_ahb;
1274
1275 sdmac->bd_pool = dma_pool_create("bd_pool", chan->device->dev,
1276 sizeof(struct sdma_buffer_descriptor),
1277 32, 0);
1278
1279 return 0;
1280
1281 disable_clk_ahb:
1282 clk_disable(sdmac->sdma->clk_ahb);
1283 disable_clk_ipg:
1284 clk_disable(sdmac->sdma->clk_ipg);
1285 return ret;
1286 }
1287
sdma_free_chan_resources(struct dma_chan * chan)1288 static void sdma_free_chan_resources(struct dma_chan *chan)
1289 {
1290 struct sdma_channel *sdmac = to_sdma_chan(chan);
1291 struct sdma_engine *sdma = sdmac->sdma;
1292
1293 sdma_disable_channel_with_delay(chan);
1294
1295 if (sdmac->event_id0)
1296 sdma_event_disable(sdmac, sdmac->event_id0);
1297 if (sdmac->event_id1)
1298 sdma_event_disable(sdmac, sdmac->event_id1);
1299
1300 sdmac->event_id0 = 0;
1301 sdmac->event_id1 = 0;
1302
1303 sdma_set_channel_priority(sdmac, 0);
1304
1305 clk_disable(sdma->clk_ipg);
1306 clk_disable(sdma->clk_ahb);
1307
1308 dma_pool_destroy(sdmac->bd_pool);
1309 sdmac->bd_pool = NULL;
1310 }
1311
sdma_transfer_init(struct sdma_channel * sdmac,enum dma_transfer_direction direction,u32 bds)1312 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1313 enum dma_transfer_direction direction, u32 bds)
1314 {
1315 struct sdma_desc *desc;
1316
1317 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1318 if (!desc)
1319 goto err_out;
1320
1321 sdmac->status = DMA_IN_PROGRESS;
1322 sdmac->direction = direction;
1323 sdmac->flags = 0;
1324
1325 desc->chn_count = 0;
1326 desc->chn_real_count = 0;
1327 desc->buf_tail = 0;
1328 desc->buf_ptail = 0;
1329 desc->sdmac = sdmac;
1330 desc->num_bd = bds;
1331
1332 if (sdma_alloc_bd(desc))
1333 goto err_desc_out;
1334
1335 /* No slave_config called in MEMCPY case, so do here */
1336 if (direction == DMA_MEM_TO_MEM)
1337 sdma_config_ownership(sdmac, false, true, false);
1338
1339 if (sdma_load_context(sdmac))
1340 goto err_desc_out;
1341
1342 return desc;
1343
1344 err_desc_out:
1345 kfree(desc);
1346 err_out:
1347 return NULL;
1348 }
1349
sdma_prep_memcpy(struct dma_chan * chan,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len,unsigned long flags)1350 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1351 struct dma_chan *chan, dma_addr_t dma_dst,
1352 dma_addr_t dma_src, size_t len, unsigned long flags)
1353 {
1354 struct sdma_channel *sdmac = to_sdma_chan(chan);
1355 struct sdma_engine *sdma = sdmac->sdma;
1356 int channel = sdmac->channel;
1357 size_t count;
1358 int i = 0, param;
1359 struct sdma_buffer_descriptor *bd;
1360 struct sdma_desc *desc;
1361
1362 if (!chan || !len)
1363 return NULL;
1364
1365 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1366 &dma_src, &dma_dst, len, channel);
1367
1368 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1369 len / SDMA_BD_MAX_CNT + 1);
1370 if (!desc)
1371 return NULL;
1372
1373 do {
1374 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1375 bd = &desc->bd[i];
1376 bd->buffer_addr = dma_src;
1377 bd->ext_buffer_addr = dma_dst;
1378 bd->mode.count = count;
1379 desc->chn_count += count;
1380 bd->mode.command = 0;
1381
1382 dma_src += count;
1383 dma_dst += count;
1384 len -= count;
1385 i++;
1386
1387 param = BD_DONE | BD_EXTD | BD_CONT;
1388 /* last bd */
1389 if (!len) {
1390 param |= BD_INTR;
1391 param |= BD_LAST;
1392 param &= ~BD_CONT;
1393 }
1394
1395 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1396 i, count, bd->buffer_addr,
1397 param & BD_WRAP ? "wrap" : "",
1398 param & BD_INTR ? " intr" : "");
1399
1400 bd->mode.status = param;
1401 } while (len);
1402
1403 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1404 }
1405
sdma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)1406 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1407 struct dma_chan *chan, struct scatterlist *sgl,
1408 unsigned int sg_len, enum dma_transfer_direction direction,
1409 unsigned long flags, void *context)
1410 {
1411 struct sdma_channel *sdmac = to_sdma_chan(chan);
1412 struct sdma_engine *sdma = sdmac->sdma;
1413 int i, count;
1414 int channel = sdmac->channel;
1415 struct scatterlist *sg;
1416 struct sdma_desc *desc;
1417
1418 desc = sdma_transfer_init(sdmac, direction, sg_len);
1419 if (!desc)
1420 goto err_out;
1421
1422 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1423 sg_len, channel);
1424
1425 for_each_sg(sgl, sg, sg_len, i) {
1426 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1427 int param;
1428
1429 bd->buffer_addr = sg->dma_address;
1430
1431 count = sg_dma_len(sg);
1432
1433 if (count > SDMA_BD_MAX_CNT) {
1434 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1435 channel, count, SDMA_BD_MAX_CNT);
1436 goto err_bd_out;
1437 }
1438
1439 bd->mode.count = count;
1440 desc->chn_count += count;
1441
1442 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1443 goto err_bd_out;
1444
1445 switch (sdmac->word_size) {
1446 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1447 bd->mode.command = 0;
1448 if (count & 3 || sg->dma_address & 3)
1449 goto err_bd_out;
1450 break;
1451 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1452 bd->mode.command = 2;
1453 if (count & 1 || sg->dma_address & 1)
1454 goto err_bd_out;
1455 break;
1456 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1457 bd->mode.command = 1;
1458 break;
1459 default:
1460 goto err_bd_out;
1461 }
1462
1463 param = BD_DONE | BD_EXTD | BD_CONT;
1464
1465 if (i + 1 == sg_len) {
1466 param |= BD_INTR;
1467 param |= BD_LAST;
1468 param &= ~BD_CONT;
1469 }
1470
1471 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1472 i, count, (u64)sg->dma_address,
1473 param & BD_WRAP ? "wrap" : "",
1474 param & BD_INTR ? " intr" : "");
1475
1476 bd->mode.status = param;
1477 }
1478
1479 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1480 err_bd_out:
1481 sdma_free_bd(desc);
1482 kfree(desc);
1483 err_out:
1484 sdmac->status = DMA_ERROR;
1485 return NULL;
1486 }
1487
sdma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t dma_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1488 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1489 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1490 size_t period_len, enum dma_transfer_direction direction,
1491 unsigned long flags)
1492 {
1493 struct sdma_channel *sdmac = to_sdma_chan(chan);
1494 struct sdma_engine *sdma = sdmac->sdma;
1495 int num_periods = buf_len / period_len;
1496 int channel = sdmac->channel;
1497 int i = 0, buf = 0;
1498 struct sdma_desc *desc;
1499
1500 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1501
1502 desc = sdma_transfer_init(sdmac, direction, num_periods);
1503 if (!desc)
1504 goto err_out;
1505
1506 desc->period_len = period_len;
1507
1508 sdmac->flags |= IMX_DMA_SG_LOOP;
1509
1510 if (period_len > SDMA_BD_MAX_CNT) {
1511 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1512 channel, period_len, SDMA_BD_MAX_CNT);
1513 goto err_bd_out;
1514 }
1515
1516 while (buf < buf_len) {
1517 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1518 int param;
1519
1520 bd->buffer_addr = dma_addr;
1521
1522 bd->mode.count = period_len;
1523
1524 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1525 goto err_bd_out;
1526 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1527 bd->mode.command = 0;
1528 else
1529 bd->mode.command = sdmac->word_size;
1530
1531 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1532 if (i + 1 == num_periods)
1533 param |= BD_WRAP;
1534
1535 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1536 i, period_len, (u64)dma_addr,
1537 param & BD_WRAP ? "wrap" : "",
1538 param & BD_INTR ? " intr" : "");
1539
1540 bd->mode.status = param;
1541
1542 dma_addr += period_len;
1543 buf += period_len;
1544
1545 i++;
1546 }
1547
1548 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1549 err_bd_out:
1550 sdma_free_bd(desc);
1551 kfree(desc);
1552 err_out:
1553 sdmac->status = DMA_ERROR;
1554 return NULL;
1555 }
1556
sdma_config(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg)1557 static int sdma_config(struct dma_chan *chan,
1558 struct dma_slave_config *dmaengine_cfg)
1559 {
1560 struct sdma_channel *sdmac = to_sdma_chan(chan);
1561
1562 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1563 sdmac->per_address = dmaengine_cfg->src_addr;
1564 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1565 dmaengine_cfg->src_addr_width;
1566 sdmac->word_size = dmaengine_cfg->src_addr_width;
1567 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1568 sdmac->per_address2 = dmaengine_cfg->src_addr;
1569 sdmac->per_address = dmaengine_cfg->dst_addr;
1570 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1571 SDMA_WATERMARK_LEVEL_LWML;
1572 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1573 SDMA_WATERMARK_LEVEL_HWML;
1574 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1575 } else {
1576 sdmac->per_address = dmaengine_cfg->dst_addr;
1577 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1578 dmaengine_cfg->dst_addr_width;
1579 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1580 }
1581 sdmac->direction = dmaengine_cfg->direction;
1582 return sdma_config_channel(chan);
1583 }
1584
sdma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1585 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1586 dma_cookie_t cookie,
1587 struct dma_tx_state *txstate)
1588 {
1589 struct sdma_channel *sdmac = to_sdma_chan(chan);
1590 struct sdma_desc *desc;
1591 u32 residue;
1592 struct virt_dma_desc *vd;
1593 enum dma_status ret;
1594 unsigned long flags;
1595
1596 ret = dma_cookie_status(chan, cookie, txstate);
1597 if (ret == DMA_COMPLETE || !txstate)
1598 return ret;
1599
1600 spin_lock_irqsave(&sdmac->vc.lock, flags);
1601 vd = vchan_find_desc(&sdmac->vc, cookie);
1602 if (vd) {
1603 desc = to_sdma_desc(&vd->tx);
1604 if (sdmac->flags & IMX_DMA_SG_LOOP)
1605 residue = (desc->num_bd - desc->buf_ptail) *
1606 desc->period_len - desc->chn_real_count;
1607 else
1608 residue = desc->chn_count - desc->chn_real_count;
1609 } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1610 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1611 } else {
1612 residue = 0;
1613 }
1614 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1615
1616 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1617 residue);
1618
1619 return sdmac->status;
1620 }
1621
sdma_issue_pending(struct dma_chan * chan)1622 static void sdma_issue_pending(struct dma_chan *chan)
1623 {
1624 struct sdma_channel *sdmac = to_sdma_chan(chan);
1625 unsigned long flags;
1626
1627 spin_lock_irqsave(&sdmac->vc.lock, flags);
1628 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1629 sdma_start_desc(sdmac);
1630 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1631 }
1632
1633 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1634 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1635 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1636 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1637
sdma_add_scripts(struct sdma_engine * sdma,const struct sdma_script_start_addrs * addr)1638 static void sdma_add_scripts(struct sdma_engine *sdma,
1639 const struct sdma_script_start_addrs *addr)
1640 {
1641 s32 *addr_arr = (u32 *)addr;
1642 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1643 int i;
1644
1645 /* use the default firmware in ROM if missing external firmware */
1646 if (!sdma->script_number)
1647 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1648
1649 for (i = 0; i < sdma->script_number; i++)
1650 if (addr_arr[i] > 0)
1651 saddr_arr[i] = addr_arr[i];
1652 }
1653
sdma_load_firmware(const struct firmware * fw,void * context)1654 static void sdma_load_firmware(const struct firmware *fw, void *context)
1655 {
1656 struct sdma_engine *sdma = context;
1657 const struct sdma_firmware_header *header;
1658 const struct sdma_script_start_addrs *addr;
1659 unsigned short *ram_code;
1660
1661 if (!fw) {
1662 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1663 /* In this case we just use the ROM firmware. */
1664 return;
1665 }
1666
1667 if (fw->size < sizeof(*header))
1668 goto err_firmware;
1669
1670 header = (struct sdma_firmware_header *)fw->data;
1671
1672 if (header->magic != SDMA_FIRMWARE_MAGIC)
1673 goto err_firmware;
1674 if (header->ram_code_start + header->ram_code_size > fw->size)
1675 goto err_firmware;
1676 switch (header->version_major) {
1677 case 1:
1678 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1679 break;
1680 case 2:
1681 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1682 break;
1683 case 3:
1684 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1685 break;
1686 case 4:
1687 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1688 break;
1689 default:
1690 dev_err(sdma->dev, "unknown firmware version\n");
1691 goto err_firmware;
1692 }
1693
1694 addr = (void *)header + header->script_addrs_start;
1695 ram_code = (void *)header + header->ram_code_start;
1696
1697 clk_enable(sdma->clk_ipg);
1698 clk_enable(sdma->clk_ahb);
1699 /* download the RAM image for SDMA */
1700 sdma_load_script(sdma, ram_code,
1701 header->ram_code_size,
1702 addr->ram_code_start_addr);
1703 clk_disable(sdma->clk_ipg);
1704 clk_disable(sdma->clk_ahb);
1705
1706 sdma_add_scripts(sdma, addr);
1707
1708 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1709 header->version_major,
1710 header->version_minor);
1711
1712 err_firmware:
1713 release_firmware(fw);
1714 }
1715
1716 #define EVENT_REMAP_CELLS 3
1717
sdma_event_remap(struct sdma_engine * sdma)1718 static int sdma_event_remap(struct sdma_engine *sdma)
1719 {
1720 struct device_node *np = sdma->dev->of_node;
1721 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1722 struct property *event_remap;
1723 struct regmap *gpr;
1724 char propname[] = "fsl,sdma-event-remap";
1725 u32 reg, val, shift, num_map, i;
1726 int ret = 0;
1727
1728 if (IS_ERR(np) || IS_ERR(gpr_np))
1729 goto out;
1730
1731 event_remap = of_find_property(np, propname, NULL);
1732 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1733 if (!num_map) {
1734 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1735 goto out;
1736 } else if (num_map % EVENT_REMAP_CELLS) {
1737 dev_err(sdma->dev, "the property %s must modulo %d\n",
1738 propname, EVENT_REMAP_CELLS);
1739 ret = -EINVAL;
1740 goto out;
1741 }
1742
1743 gpr = syscon_node_to_regmap(gpr_np);
1744 if (IS_ERR(gpr)) {
1745 dev_err(sdma->dev, "failed to get gpr regmap\n");
1746 ret = PTR_ERR(gpr);
1747 goto out;
1748 }
1749
1750 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1751 ret = of_property_read_u32_index(np, propname, i, ®);
1752 if (ret) {
1753 dev_err(sdma->dev, "failed to read property %s index %d\n",
1754 propname, i);
1755 goto out;
1756 }
1757
1758 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1759 if (ret) {
1760 dev_err(sdma->dev, "failed to read property %s index %d\n",
1761 propname, i + 1);
1762 goto out;
1763 }
1764
1765 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1766 if (ret) {
1767 dev_err(sdma->dev, "failed to read property %s index %d\n",
1768 propname, i + 2);
1769 goto out;
1770 }
1771
1772 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1773 }
1774
1775 out:
1776 if (!IS_ERR(gpr_np))
1777 of_node_put(gpr_np);
1778
1779 return ret;
1780 }
1781
sdma_get_firmware(struct sdma_engine * sdma,const char * fw_name)1782 static int sdma_get_firmware(struct sdma_engine *sdma,
1783 const char *fw_name)
1784 {
1785 int ret;
1786
1787 ret = request_firmware_nowait(THIS_MODULE,
1788 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1789 GFP_KERNEL, sdma, sdma_load_firmware);
1790
1791 return ret;
1792 }
1793
sdma_init(struct sdma_engine * sdma)1794 static int sdma_init(struct sdma_engine *sdma)
1795 {
1796 int i, ret;
1797 dma_addr_t ccb_phys;
1798
1799 ret = clk_enable(sdma->clk_ipg);
1800 if (ret)
1801 return ret;
1802 ret = clk_enable(sdma->clk_ahb);
1803 if (ret)
1804 goto disable_clk_ipg;
1805
1806 /* Be sure SDMA has not started yet */
1807 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1808
1809 sdma->channel_control = dma_alloc_coherent(NULL,
1810 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1811 sizeof(struct sdma_context_data),
1812 &ccb_phys, GFP_KERNEL);
1813
1814 if (!sdma->channel_control) {
1815 ret = -ENOMEM;
1816 goto err_dma_alloc;
1817 }
1818
1819 sdma->context = (void *)sdma->channel_control +
1820 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1821 sdma->context_phys = ccb_phys +
1822 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1823
1824 /* Zero-out the CCB structures array just allocated */
1825 memset(sdma->channel_control, 0,
1826 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1827
1828 /* disable all channels */
1829 for (i = 0; i < sdma->drvdata->num_events; i++)
1830 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1831
1832 /* All channels have priority 0 */
1833 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1834 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1835
1836 ret = sdma_request_channel0(sdma);
1837 if (ret)
1838 goto err_dma_alloc;
1839
1840 sdma_config_ownership(&sdma->channel[0], false, true, false);
1841
1842 /* Set Command Channel (Channel Zero) */
1843 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1844
1845 /* Set bits of CONFIG register but with static context switching */
1846 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1847 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1848
1849 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1850
1851 /* Initializes channel's priorities */
1852 sdma_set_channel_priority(&sdma->channel[0], 7);
1853
1854 clk_disable(sdma->clk_ipg);
1855 clk_disable(sdma->clk_ahb);
1856
1857 return 0;
1858
1859 err_dma_alloc:
1860 clk_disable(sdma->clk_ahb);
1861 disable_clk_ipg:
1862 clk_disable(sdma->clk_ipg);
1863 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1864 return ret;
1865 }
1866
sdma_filter_fn(struct dma_chan * chan,void * fn_param)1867 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1868 {
1869 struct sdma_channel *sdmac = to_sdma_chan(chan);
1870 struct imx_dma_data *data = fn_param;
1871
1872 if (!imx_dma_is_general_purpose(chan))
1873 return false;
1874
1875 sdmac->data = *data;
1876 chan->private = &sdmac->data;
1877
1878 return true;
1879 }
1880
sdma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1881 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1882 struct of_dma *ofdma)
1883 {
1884 struct sdma_engine *sdma = ofdma->of_dma_data;
1885 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1886 struct imx_dma_data data;
1887
1888 if (dma_spec->args_count != 3)
1889 return NULL;
1890
1891 data.dma_request = dma_spec->args[0];
1892 data.peripheral_type = dma_spec->args[1];
1893 data.priority = dma_spec->args[2];
1894 /*
1895 * init dma_request2 to zero, which is not used by the dts.
1896 * For P2P, dma_request2 is init from dma_request_channel(),
1897 * chan->private will point to the imx_dma_data, and in
1898 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1899 * be set to sdmac->event_id1.
1900 */
1901 data.dma_request2 = 0;
1902
1903 return dma_request_channel(mask, sdma_filter_fn, &data);
1904 }
1905
sdma_probe(struct platform_device * pdev)1906 static int sdma_probe(struct platform_device *pdev)
1907 {
1908 const struct of_device_id *of_id =
1909 of_match_device(sdma_dt_ids, &pdev->dev);
1910 struct device_node *np = pdev->dev.of_node;
1911 struct device_node *spba_bus;
1912 const char *fw_name;
1913 int ret;
1914 int irq;
1915 struct resource *iores;
1916 struct resource spba_res;
1917 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1918 int i;
1919 struct sdma_engine *sdma;
1920 s32 *saddr_arr;
1921 const struct sdma_driver_data *drvdata = NULL;
1922
1923 if (of_id)
1924 drvdata = of_id->data;
1925 else if (pdev->id_entry)
1926 drvdata = (void *)pdev->id_entry->driver_data;
1927
1928 if (!drvdata) {
1929 dev_err(&pdev->dev, "unable to find driver data\n");
1930 return -EINVAL;
1931 }
1932
1933 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1934 if (ret)
1935 return ret;
1936
1937 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1938 if (!sdma)
1939 return -ENOMEM;
1940
1941 spin_lock_init(&sdma->channel_0_lock);
1942
1943 sdma->dev = &pdev->dev;
1944 sdma->drvdata = drvdata;
1945
1946 irq = platform_get_irq(pdev, 0);
1947 if (irq < 0)
1948 return irq;
1949
1950 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1951 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1952 if (IS_ERR(sdma->regs))
1953 return PTR_ERR(sdma->regs);
1954
1955 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1956 if (IS_ERR(sdma->clk_ipg))
1957 return PTR_ERR(sdma->clk_ipg);
1958
1959 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1960 if (IS_ERR(sdma->clk_ahb))
1961 return PTR_ERR(sdma->clk_ahb);
1962
1963 ret = clk_prepare(sdma->clk_ipg);
1964 if (ret)
1965 return ret;
1966
1967 ret = clk_prepare(sdma->clk_ahb);
1968 if (ret)
1969 goto err_clk;
1970
1971 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1972 sdma);
1973 if (ret)
1974 goto err_irq;
1975
1976 sdma->irq = irq;
1977
1978 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1979 if (!sdma->script_addrs) {
1980 ret = -ENOMEM;
1981 goto err_irq;
1982 }
1983
1984 /* initially no scripts available */
1985 saddr_arr = (s32 *)sdma->script_addrs;
1986 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1987 saddr_arr[i] = -EINVAL;
1988
1989 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1990 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1991 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
1992
1993 INIT_LIST_HEAD(&sdma->dma_device.channels);
1994 /* Initialize channel parameters */
1995 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1996 struct sdma_channel *sdmac = &sdma->channel[i];
1997
1998 sdmac->sdma = sdma;
1999
2000 sdmac->channel = i;
2001 sdmac->vc.desc_free = sdma_desc_free;
2002 /*
2003 * Add the channel to the DMAC list. Do not add channel 0 though
2004 * because we need it internally in the SDMA driver. This also means
2005 * that channel 0 in dmaengine counting matches sdma channel 1.
2006 */
2007 if (i)
2008 vchan_init(&sdmac->vc, &sdma->dma_device);
2009 }
2010
2011 ret = sdma_init(sdma);
2012 if (ret)
2013 goto err_init;
2014
2015 ret = sdma_event_remap(sdma);
2016 if (ret)
2017 goto err_init;
2018
2019 if (sdma->drvdata->script_addrs)
2020 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2021 if (pdata && pdata->script_addrs)
2022 sdma_add_scripts(sdma, pdata->script_addrs);
2023
2024 if (pdata) {
2025 ret = sdma_get_firmware(sdma, pdata->fw_name);
2026 if (ret)
2027 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2028 } else {
2029 /*
2030 * Because that device tree does not encode ROM script address,
2031 * the RAM script in firmware is mandatory for device tree
2032 * probe, otherwise it fails.
2033 */
2034 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2035 &fw_name);
2036 if (ret)
2037 dev_warn(&pdev->dev, "failed to get firmware name\n");
2038 else {
2039 ret = sdma_get_firmware(sdma, fw_name);
2040 if (ret)
2041 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2042 }
2043 }
2044
2045 sdma->dma_device.dev = &pdev->dev;
2046
2047 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2048 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2049 sdma->dma_device.device_tx_status = sdma_tx_status;
2050 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2051 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2052 sdma->dma_device.device_config = sdma_config;
2053 sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
2054 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2055 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2056 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2057 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2058 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2059 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2060 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
2061 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2062
2063 platform_set_drvdata(pdev, sdma);
2064
2065 ret = dma_async_device_register(&sdma->dma_device);
2066 if (ret) {
2067 dev_err(&pdev->dev, "unable to register\n");
2068 goto err_init;
2069 }
2070
2071 if (np) {
2072 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2073 if (ret) {
2074 dev_err(&pdev->dev, "failed to register controller\n");
2075 goto err_register;
2076 }
2077
2078 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2079 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2080 if (!ret) {
2081 sdma->spba_start_addr = spba_res.start;
2082 sdma->spba_end_addr = spba_res.end;
2083 }
2084 of_node_put(spba_bus);
2085 }
2086
2087 return 0;
2088
2089 err_register:
2090 dma_async_device_unregister(&sdma->dma_device);
2091 err_init:
2092 kfree(sdma->script_addrs);
2093 err_irq:
2094 clk_unprepare(sdma->clk_ahb);
2095 err_clk:
2096 clk_unprepare(sdma->clk_ipg);
2097 return ret;
2098 }
2099
sdma_remove(struct platform_device * pdev)2100 static int sdma_remove(struct platform_device *pdev)
2101 {
2102 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2103 int i;
2104
2105 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2106 dma_async_device_unregister(&sdma->dma_device);
2107 kfree(sdma->script_addrs);
2108 clk_unprepare(sdma->clk_ahb);
2109 clk_unprepare(sdma->clk_ipg);
2110 /* Kill the tasklet */
2111 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2112 struct sdma_channel *sdmac = &sdma->channel[i];
2113
2114 tasklet_kill(&sdmac->vc.task);
2115 sdma_free_chan_resources(&sdmac->vc.chan);
2116 }
2117
2118 platform_set_drvdata(pdev, NULL);
2119 return 0;
2120 }
2121
2122 static struct platform_driver sdma_driver = {
2123 .driver = {
2124 .name = "imx-sdma",
2125 .of_match_table = sdma_dt_ids,
2126 },
2127 .id_table = sdma_devtypes,
2128 .remove = sdma_remove,
2129 .probe = sdma_probe,
2130 };
2131
2132 module_platform_driver(sdma_driver);
2133
2134 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2135 MODULE_DESCRIPTION("i.MX SDMA driver");
2136 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2137 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2138 #endif
2139 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2140 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2141 #endif
2142 MODULE_LICENSE("GPL");
2143
