1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/cpufreq.h>
16 #include <linux/cpu_cooling.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/of.h>
23 #include <linux/slab.h>
24 #include <linux/smp.h>
25
26 /**
27 * struct cpu_data
28 * @pclk: the parent clock of cpu
29 * @table: frequency table
30 */
31 struct cpu_data {
32 struct clk **pclk;
33 struct cpufreq_frequency_table *table;
34 struct thermal_cooling_device *cdev;
35 };
36
37 /*
38 * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
39 * matched a more generic compatible.
40 */
41 #define SOC_BLACKLIST 1
42
43 /**
44 * struct soc_data - SoC specific data
45 * @flags: SOC_xxx
46 */
47 struct soc_data {
48 u32 flags;
49 };
50
get_bus_freq(void)51 static u32 get_bus_freq(void)
52 {
53 struct device_node *soc;
54 u32 sysfreq;
55 struct clk *pltclk;
56 int ret;
57
58 /* get platform freq by searching bus-frequency property */
59 soc = of_find_node_by_type(NULL, "soc");
60 if (soc) {
61 ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
62 of_node_put(soc);
63 if (!ret)
64 return sysfreq;
65 }
66
67 /* get platform freq by its clock name */
68 pltclk = clk_get(NULL, "cg-pll0-div1");
69 if (IS_ERR(pltclk)) {
70 pr_err("%s: can't get bus frequency %ld\n",
71 __func__, PTR_ERR(pltclk));
72 return PTR_ERR(pltclk);
73 }
74
75 return clk_get_rate(pltclk);
76 }
77
cpu_to_clk(int cpu)78 static struct clk *cpu_to_clk(int cpu)
79 {
80 struct device_node *np;
81 struct clk *clk;
82
83 if (!cpu_present(cpu))
84 return NULL;
85
86 np = of_get_cpu_node(cpu, NULL);
87 if (!np)
88 return NULL;
89
90 clk = of_clk_get(np, 0);
91 of_node_put(np);
92 return clk;
93 }
94
95 /* traverse cpu nodes to get cpu mask of sharing clock wire */
set_affected_cpus(struct cpufreq_policy * policy)96 static void set_affected_cpus(struct cpufreq_policy *policy)
97 {
98 struct cpumask *dstp = policy->cpus;
99 struct clk *clk;
100 int i;
101
102 for_each_present_cpu(i) {
103 clk = cpu_to_clk(i);
104 if (IS_ERR(clk)) {
105 pr_err("%s: no clock for cpu %d\n", __func__, i);
106 continue;
107 }
108
109 if (clk_is_match(policy->clk, clk))
110 cpumask_set_cpu(i, dstp);
111 }
112 }
113
114 /* reduce the duplicated frequencies in frequency table */
freq_table_redup(struct cpufreq_frequency_table * freq_table,int count)115 static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
116 int count)
117 {
118 int i, j;
119
120 for (i = 1; i < count; i++) {
121 for (j = 0; j < i; j++) {
122 if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
123 freq_table[j].frequency !=
124 freq_table[i].frequency)
125 continue;
126
127 freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
128 break;
129 }
130 }
131 }
132
133 /* sort the frequencies in frequency table in descenting order */
freq_table_sort(struct cpufreq_frequency_table * freq_table,int count)134 static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
135 int count)
136 {
137 int i, j, ind;
138 unsigned int freq, max_freq;
139 struct cpufreq_frequency_table table;
140
141 for (i = 0; i < count - 1; i++) {
142 max_freq = freq_table[i].frequency;
143 ind = i;
144 for (j = i + 1; j < count; j++) {
145 freq = freq_table[j].frequency;
146 if (freq == CPUFREQ_ENTRY_INVALID ||
147 freq <= max_freq)
148 continue;
149 ind = j;
150 max_freq = freq;
151 }
152
153 if (ind != i) {
154 /* exchange the frequencies */
155 table.driver_data = freq_table[i].driver_data;
156 table.frequency = freq_table[i].frequency;
157 freq_table[i].driver_data = freq_table[ind].driver_data;
158 freq_table[i].frequency = freq_table[ind].frequency;
159 freq_table[ind].driver_data = table.driver_data;
160 freq_table[ind].frequency = table.frequency;
161 }
162 }
163 }
164
qoriq_cpufreq_cpu_init(struct cpufreq_policy * policy)165 static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
166 {
167 struct device_node *np;
168 int i, count;
169 u32 freq;
170 struct clk *clk;
171 const struct clk_hw *hwclk;
172 struct cpufreq_frequency_table *table;
173 struct cpu_data *data;
174 unsigned int cpu = policy->cpu;
175 u64 u64temp;
176
177 np = of_get_cpu_node(cpu, NULL);
178 if (!np)
179 return -ENODEV;
180
181 data = kzalloc(sizeof(*data), GFP_KERNEL);
182 if (!data)
183 goto err_np;
184
185 policy->clk = of_clk_get(np, 0);
186 if (IS_ERR(policy->clk)) {
187 pr_err("%s: no clock information\n", __func__);
188 goto err_nomem2;
189 }
190
191 hwclk = __clk_get_hw(policy->clk);
192 count = clk_hw_get_num_parents(hwclk);
193
194 data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
195 if (!data->pclk)
196 goto err_nomem2;
197
198 table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
199 if (!table)
200 goto err_pclk;
201
202 for (i = 0; i < count; i++) {
203 clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
204 data->pclk[i] = clk;
205 freq = clk_get_rate(clk);
206 table[i].frequency = freq / 1000;
207 table[i].driver_data = i;
208 }
209 freq_table_redup(table, count);
210 freq_table_sort(table, count);
211 table[i].frequency = CPUFREQ_TABLE_END;
212 policy->freq_table = table;
213 data->table = table;
214
215 /* update ->cpus if we have cluster, no harm if not */
216 set_affected_cpus(policy);
217 policy->driver_data = data;
218
219 /* Minimum transition latency is 12 platform clocks */
220 u64temp = 12ULL * NSEC_PER_SEC;
221 do_div(u64temp, get_bus_freq());
222 policy->cpuinfo.transition_latency = u64temp + 1;
223
224 of_node_put(np);
225
226 return 0;
227
228 err_pclk:
229 kfree(data->pclk);
230 err_nomem2:
231 kfree(data);
232 err_np:
233 of_node_put(np);
234
235 return -ENODEV;
236 }
237
qoriq_cpufreq_cpu_exit(struct cpufreq_policy * policy)238 static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
239 {
240 struct cpu_data *data = policy->driver_data;
241
242 cpufreq_cooling_unregister(data->cdev);
243 kfree(data->pclk);
244 kfree(data->table);
245 kfree(data);
246 policy->driver_data = NULL;
247
248 return 0;
249 }
250
qoriq_cpufreq_target(struct cpufreq_policy * policy,unsigned int index)251 static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
252 unsigned int index)
253 {
254 struct clk *parent;
255 struct cpu_data *data = policy->driver_data;
256
257 parent = data->pclk[data->table[index].driver_data];
258 return clk_set_parent(policy->clk, parent);
259 }
260
261
qoriq_cpufreq_ready(struct cpufreq_policy * policy)262 static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
263 {
264 struct cpu_data *cpud = policy->driver_data;
265
266 cpud->cdev = of_cpufreq_cooling_register(policy);
267 }
268
269 static struct cpufreq_driver qoriq_cpufreq_driver = {
270 .name = "qoriq_cpufreq",
271 .flags = CPUFREQ_CONST_LOOPS,
272 .init = qoriq_cpufreq_cpu_init,
273 .exit = qoriq_cpufreq_cpu_exit,
274 .verify = cpufreq_generic_frequency_table_verify,
275 .target_index = qoriq_cpufreq_target,
276 .get = cpufreq_generic_get,
277 .ready = qoriq_cpufreq_ready,
278 .attr = cpufreq_generic_attr,
279 };
280
281 static const struct soc_data blacklist = {
282 .flags = SOC_BLACKLIST,
283 };
284
285 static const struct of_device_id node_matches[] __initconst = {
286 /* e6500 cannot use cpufreq due to erratum A-008083 */
287 { .compatible = "fsl,b4420-clockgen", &blacklist },
288 { .compatible = "fsl,b4860-clockgen", &blacklist },
289 { .compatible = "fsl,t2080-clockgen", &blacklist },
290 { .compatible = "fsl,t4240-clockgen", &blacklist },
291
292 { .compatible = "fsl,ls1012a-clockgen", },
293 { .compatible = "fsl,ls1021a-clockgen", },
294 { .compatible = "fsl,ls1043a-clockgen", },
295 { .compatible = "fsl,ls1046a-clockgen", },
296 { .compatible = "fsl,ls1088a-clockgen", },
297 { .compatible = "fsl,ls2080a-clockgen", },
298 { .compatible = "fsl,p4080-clockgen", },
299 { .compatible = "fsl,qoriq-clockgen-1.0", },
300 { .compatible = "fsl,qoriq-clockgen-2.0", },
301 {}
302 };
303
qoriq_cpufreq_init(void)304 static int __init qoriq_cpufreq_init(void)
305 {
306 int ret;
307 struct device_node *np;
308 const struct of_device_id *match;
309 const struct soc_data *data;
310
311 np = of_find_matching_node(NULL, node_matches);
312 if (!np)
313 return -ENODEV;
314
315 match = of_match_node(node_matches, np);
316 data = match->data;
317
318 of_node_put(np);
319
320 if (data && data->flags & SOC_BLACKLIST)
321 return -ENODEV;
322
323 ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
324 if (!ret)
325 pr_info("Freescale QorIQ CPU frequency scaling driver\n");
326
327 return ret;
328 }
329 module_init(qoriq_cpufreq_init);
330
qoriq_cpufreq_exit(void)331 static void __exit qoriq_cpufreq_exit(void)
332 {
333 cpufreq_unregister_driver(&qoriq_cpufreq_driver);
334 }
335 module_exit(qoriq_cpufreq_exit);
336
337 MODULE_LICENSE("GPL");
338 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
339 MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
340
