1 /*
2 * Copyright (C) 2011 Dmitry Eremin-Solenikov
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
11 * that is iMac G5 and latest single CPU desktop.
12 */
13
14 #undef DEBUG
15
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/sched.h>
24 #include <linux/cpufreq.h>
25 #include <linux/init.h>
26 #include <linux/completion.h>
27 #include <linux/mutex.h>
28 #include <linux/time.h>
29 #include <linux/of_device.h>
30
31 #define DBG(fmt...) pr_debug(fmt)
32
33 /* see 970FX user manual */
34
35 #define SCOM_PCR 0x0aa001 /* PCR scom addr */
36
37 #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
38 #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
39 #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
40 #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
41 #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
42 #define PCR_SPEED_SHIFT 17
43 #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
44 #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
45 #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
46 #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
47 #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
48 #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
49
50 #define SCOM_PSR 0x408001 /* PSR scom addr */
51 /* warning: PSR is a 64 bits register */
52 #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
53 #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
54 #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
55 #define PSR_CUR_SPEED_SHIFT (56)
56
57 /*
58 * The G5 only supports two frequencies (Quarter speed is not supported)
59 */
60 #define CPUFREQ_HIGH 0
61 #define CPUFREQ_LOW 1
62
63 static struct cpufreq_frequency_table maple_cpu_freqs[] = {
64 {0, CPUFREQ_HIGH, 0},
65 {0, CPUFREQ_LOW, 0},
66 {0, 0, CPUFREQ_TABLE_END},
67 };
68
69 /* Power mode data is an array of the 32 bits PCR values to use for
70 * the various frequencies, retrieved from the device-tree
71 */
72 static int maple_pmode_cur;
73
74 static const u32 *maple_pmode_data;
75 static int maple_pmode_max;
76
77 /*
78 * SCOM based frequency switching for 970FX rev3
79 */
maple_scom_switch_freq(int speed_mode)80 static int maple_scom_switch_freq(int speed_mode)
81 {
82 unsigned long flags;
83 int to;
84
85 local_irq_save(flags);
86
87 /* Clear PCR high */
88 scom970_write(SCOM_PCR, 0);
89 /* Clear PCR low */
90 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
91 /* Set PCR low */
92 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
93 maple_pmode_data[speed_mode]);
94
95 /* Wait for completion */
96 for (to = 0; to < 10; to++) {
97 unsigned long psr = scom970_read(SCOM_PSR);
98
99 if ((psr & PSR_CMD_RECEIVED) == 0 &&
100 (((psr >> PSR_CUR_SPEED_SHIFT) ^
101 (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
102 == 0)
103 break;
104 if (psr & PSR_CMD_COMPLETED)
105 break;
106 udelay(100);
107 }
108
109 local_irq_restore(flags);
110
111 maple_pmode_cur = speed_mode;
112 ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
113
114 return 0;
115 }
116
maple_scom_query_freq(void)117 static int maple_scom_query_freq(void)
118 {
119 unsigned long psr = scom970_read(SCOM_PSR);
120 int i;
121
122 for (i = 0; i <= maple_pmode_max; i++)
123 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
124 (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
125 break;
126 return i;
127 }
128
129 /*
130 * Common interface to the cpufreq core
131 */
132
maple_cpufreq_target(struct cpufreq_policy * policy,unsigned int index)133 static int maple_cpufreq_target(struct cpufreq_policy *policy,
134 unsigned int index)
135 {
136 return maple_scom_switch_freq(index);
137 }
138
maple_cpufreq_get_speed(unsigned int cpu)139 static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
140 {
141 return maple_cpu_freqs[maple_pmode_cur].frequency;
142 }
143
maple_cpufreq_cpu_init(struct cpufreq_policy * policy)144 static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
145 {
146 return cpufreq_generic_init(policy, maple_cpu_freqs, 12000);
147 }
148
149 static struct cpufreq_driver maple_cpufreq_driver = {
150 .name = "maple",
151 .flags = CPUFREQ_CONST_LOOPS,
152 .init = maple_cpufreq_cpu_init,
153 .verify = cpufreq_generic_frequency_table_verify,
154 .target_index = maple_cpufreq_target,
155 .get = maple_cpufreq_get_speed,
156 .attr = cpufreq_generic_attr,
157 };
158
maple_cpufreq_init(void)159 static int __init maple_cpufreq_init(void)
160 {
161 struct device_node *cpunode;
162 unsigned int psize;
163 unsigned long max_freq;
164 const u32 *valp;
165 u32 pvr_hi;
166 int rc = -ENODEV;
167
168 /*
169 * Behave here like powermac driver which checks machine compatibility
170 * to ease merging of two drivers in future.
171 */
172 if (!of_machine_is_compatible("Momentum,Maple") &&
173 !of_machine_is_compatible("Momentum,Apache"))
174 return 0;
175
176 /* Get first CPU node */
177 cpunode = of_cpu_device_node_get(0);
178 if (cpunode == NULL) {
179 pr_err("Can't find any CPU 0 node\n");
180 goto bail_noprops;
181 }
182
183 /* Check 970FX for now */
184 /* we actually don't care on which CPU to access PVR */
185 pvr_hi = PVR_VER(mfspr(SPRN_PVR));
186 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
187 pr_err("Unsupported CPU version (%x)\n", pvr_hi);
188 goto bail_noprops;
189 }
190
191 /* Look for the powertune data in the device-tree */
192 /*
193 * On Maple this property is provided by PIBS in dual-processor config,
194 * not provided by PIBS in CPU0 config and also not provided by SLOF,
195 * so YMMV
196 */
197 maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
198 if (!maple_pmode_data) {
199 DBG("No power-mode-data !\n");
200 goto bail_noprops;
201 }
202 maple_pmode_max = psize / sizeof(u32) - 1;
203
204 /*
205 * From what I see, clock-frequency is always the maximal frequency.
206 * The current driver can not slew sysclk yet, so we really only deal
207 * with powertune steps for now. We also only implement full freq and
208 * half freq in this version. So far, I haven't yet seen a machine
209 * supporting anything else.
210 */
211 valp = of_get_property(cpunode, "clock-frequency", NULL);
212 if (!valp)
213 return -ENODEV;
214 max_freq = (*valp)/1000;
215 maple_cpu_freqs[0].frequency = max_freq;
216 maple_cpu_freqs[1].frequency = max_freq/2;
217
218 /* Force apply current frequency to make sure everything is in
219 * sync (voltage is right for example). Firmware may leave us with
220 * a strange setting ...
221 */
222 msleep(10);
223 maple_pmode_cur = -1;
224 maple_scom_switch_freq(maple_scom_query_freq());
225
226 pr_info("Registering Maple CPU frequency driver\n");
227 pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
228 maple_cpu_freqs[1].frequency/1000,
229 maple_cpu_freqs[0].frequency/1000,
230 maple_cpu_freqs[maple_pmode_cur].frequency/1000);
231
232 rc = cpufreq_register_driver(&maple_cpufreq_driver);
233
234 of_node_put(cpunode);
235
236 return rc;
237
238 bail_noprops:
239 of_node_put(cpunode);
240
241 return rc;
242 }
243
244 module_init(maple_cpufreq_init);
245
246
247 MODULE_LICENSE("GPL");
248
