1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012 Regents of the University of California
4  * Copyright (C) 2017 SiFive
5  */
6 #include <linux/clocksource.h>
7 #include <linux/clockchips.h>
8 #include <linux/cpu.h>
9 #include <linux/delay.h>
10 #include <linux/irq.h>
11 #include <asm/sbi.h>
12 
13 /*
14  * All RISC-V systems have a timer attached to every hart.  These timers can be
15  * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup
16  * events.  In order to abstract the architecture-specific timer reading and
17  * setting functions away from the clock event insertion code, we provide
18  * function pointers to the clockevent subsystem that perform two basic
19  * operations: rdtime() reads the timer on the current CPU, and
20  * next_event(delta) sets the next timer event to 'delta' cycles in the future.
21  * As the timers are inherently a per-cpu resource, these callbacks perform
22  * operations on the current hart.  There is guaranteed to be exactly one timer
23  * per hart on all RISC-V systems.
24  */
25 
riscv_clock_next_event(unsigned long delta,struct clock_event_device * ce)26 static int riscv_clock_next_event(unsigned long delta,
27 		struct clock_event_device *ce)
28 {
29 	csr_set(sie, SIE_STIE);
30 	sbi_set_timer(get_cycles64() + delta);
31 	return 0;
32 }
33 
34 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
35 	.name			= "riscv_timer_clockevent",
36 	.features		= CLOCK_EVT_FEAT_ONESHOT,
37 	.rating			= 100,
38 	.set_next_event		= riscv_clock_next_event,
39 };
40 
41 /*
42  * It is guaranteed that all the timers across all the harts are synchronized
43  * within one tick of each other, so while this could technically go
44  * backwards when hopping between CPUs, practically it won't happen.
45  */
riscv_clocksource_rdtime(struct clocksource * cs)46 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
47 {
48 	return get_cycles64();
49 }
50 
51 static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
52 	.name		= "riscv_clocksource",
53 	.rating		= 300,
54 	.mask		= CLOCKSOURCE_MASK(BITS_PER_LONG),
55 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
56 	.read		= riscv_clocksource_rdtime,
57 };
58 
riscv_timer_starting_cpu(unsigned int cpu)59 static int riscv_timer_starting_cpu(unsigned int cpu)
60 {
61 	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
62 
63 	ce->cpumask = cpumask_of(cpu);
64 	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
65 
66 	csr_set(sie, SIE_STIE);
67 	return 0;
68 }
69 
riscv_timer_dying_cpu(unsigned int cpu)70 static int riscv_timer_dying_cpu(unsigned int cpu)
71 {
72 	csr_clear(sie, SIE_STIE);
73 	return 0;
74 }
75 
76 /* called directly from the low-level interrupt handler */
riscv_timer_interrupt(void)77 void riscv_timer_interrupt(void)
78 {
79 	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
80 
81 	csr_clear(sie, SIE_STIE);
82 	evdev->event_handler(evdev);
83 }
84 
riscv_timer_init_dt(struct device_node * n)85 static int __init riscv_timer_init_dt(struct device_node *n)
86 {
87 	int cpu_id = riscv_of_processor_hart(n), error;
88 	struct clocksource *cs;
89 
90 	if (cpu_id != smp_processor_id())
91 		return 0;
92 
93 	cs = per_cpu_ptr(&riscv_clocksource, cpu_id);
94 	clocksource_register_hz(cs, riscv_timebase);
95 
96 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
97 			 "clockevents/riscv/timer:starting",
98 			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
99 	if (error)
100 		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
101 		       error, cpu_id);
102 	return error;
103 }
104 
105 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
106