1 /*
2 * Copyright 2014 Linaro Ltd.
3 * Copyright (C) 2014 ZTE Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk-provider.h>
11 #include <linux/of_address.h>
12 #include <dt-bindings/clock/zx296702-clock.h>
13 #include "clk.h"
14
15 static DEFINE_SPINLOCK(reg_lock);
16
17 static void __iomem *topcrm_base;
18 static void __iomem *lsp0crpm_base;
19 static void __iomem *lsp1crpm_base;
20
21 static struct clk *topclk[ZX296702_TOPCLK_END];
22 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
23 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
24
25 static struct clk_onecell_data topclk_data;
26 static struct clk_onecell_data lsp0clk_data;
27 static struct clk_onecell_data lsp1clk_data;
28
29 #define CLK_MUX (topcrm_base + 0x04)
30 #define CLK_DIV (topcrm_base + 0x08)
31 #define CLK_EN0 (topcrm_base + 0x0c)
32 #define CLK_EN1 (topcrm_base + 0x10)
33 #define VOU_LOCAL_CLKEN (topcrm_base + 0x68)
34 #define VOU_LOCAL_CLKSEL (topcrm_base + 0x70)
35 #define VOU_LOCAL_DIV2_SET (topcrm_base + 0x74)
36 #define CLK_MUX1 (topcrm_base + 0x8c)
37
38 #define CLK_SDMMC1 (lsp0crpm_base + 0x0c)
39 #define CLK_GPIO (lsp0crpm_base + 0x2c)
40 #define CLK_SPDIF0 (lsp0crpm_base + 0x10)
41 #define SPDIF0_DIV (lsp0crpm_base + 0x14)
42 #define CLK_I2S0 (lsp0crpm_base + 0x18)
43 #define I2S0_DIV (lsp0crpm_base + 0x1c)
44 #define CLK_I2S1 (lsp0crpm_base + 0x20)
45 #define I2S1_DIV (lsp0crpm_base + 0x24)
46 #define CLK_I2S2 (lsp0crpm_base + 0x34)
47 #define I2S2_DIV (lsp0crpm_base + 0x38)
48
49 #define CLK_UART0 (lsp1crpm_base + 0x20)
50 #define CLK_UART1 (lsp1crpm_base + 0x24)
51 #define CLK_SDMMC0 (lsp1crpm_base + 0x2c)
52 #define CLK_SPDIF1 (lsp1crpm_base + 0x30)
53 #define SPDIF1_DIV (lsp1crpm_base + 0x34)
54
55 static const struct zx_pll_config pll_a9_config[] = {
56 { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
57 { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
58 { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
59 { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
60 { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
61 { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
62 };
63
64 static const struct clk_div_table main_hlk_div[] = {
65 { .val = 1, .div = 2, },
66 { .val = 3, .div = 4, },
67 { /* sentinel */ }
68 };
69
70 static const struct clk_div_table a9_as1_aclk_divider[] = {
71 { .val = 0, .div = 1, },
72 { .val = 1, .div = 2, },
73 { .val = 3, .div = 4, },
74 { /* sentinel */ }
75 };
76
77 static const struct clk_div_table sec_wclk_divider[] = {
78 { .val = 0, .div = 1, },
79 { .val = 1, .div = 2, },
80 { .val = 3, .div = 4, },
81 { .val = 5, .div = 6, },
82 { .val = 7, .div = 8, },
83 { /* sentinel */ }
84 };
85
86 static const char * const matrix_aclk_sel[] = {
87 "pll_mm0_198M",
88 "osc",
89 "clk_148M5",
90 "pll_lsp_104M",
91 };
92
93 static const char * const a9_wclk_sel[] = {
94 "pll_a9",
95 "osc",
96 "clk_500",
97 "clk_250",
98 };
99
100 static const char * const a9_as1_aclk_sel[] = {
101 "clk_250",
102 "osc",
103 "pll_mm0_396M",
104 "pll_mac_333M",
105 };
106
107 static const char * const a9_trace_clkin_sel[] = {
108 "clk_74M25",
109 "pll_mm1_108M",
110 "clk_125",
111 "clk_148M5",
112 };
113
114 static const char * const decppu_aclk_sel[] = {
115 "clk_250",
116 "pll_mm0_198M",
117 "pll_lsp_104M",
118 "pll_audio_294M912",
119 };
120
121 static const char * const vou_main_wclk_sel[] = {
122 "clk_148M5",
123 "clk_74M25",
124 "clk_27",
125 "pll_mm1_54M",
126 };
127
128 static const char * const vou_scaler_wclk_sel[] = {
129 "clk_250",
130 "pll_mac_333M",
131 "pll_audio_294M912",
132 "pll_mm0_198M",
133 };
134
135 static const char * const r2d_wclk_sel[] = {
136 "pll_audio_294M912",
137 "pll_mac_333M",
138 "pll_a9_350M",
139 "pll_mm0_396M",
140 };
141
142 static const char * const ddr_wclk_sel[] = {
143 "pll_mac_333M",
144 "pll_ddr_266M",
145 "pll_audio_294M912",
146 "pll_mm0_198M",
147 };
148
149 static const char * const nand_wclk_sel[] = {
150 "pll_lsp_104M",
151 "osc",
152 };
153
154 static const char * const lsp_26_wclk_sel[] = {
155 "pll_lsp_26M",
156 "osc",
157 };
158
159 static const char * const vl0_sel[] = {
160 "vou_main_channel_div",
161 "vou_aux_channel_div",
162 };
163
164 static const char * const hdmi_sel[] = {
165 "vou_main_channel_wclk",
166 "vou_aux_channel_wclk",
167 };
168
169 static const char * const sdmmc0_wclk_sel[] = {
170 "lsp1_104M_wclk",
171 "lsp1_26M_wclk",
172 };
173
174 static const char * const sdmmc1_wclk_sel[] = {
175 "lsp0_104M_wclk",
176 "lsp0_26M_wclk",
177 };
178
179 static const char * const uart_wclk_sel[] = {
180 "lsp1_104M_wclk",
181 "lsp1_26M_wclk",
182 };
183
184 static const char * const spdif0_wclk_sel[] = {
185 "lsp0_104M_wclk",
186 "lsp0_26M_wclk",
187 };
188
189 static const char * const spdif1_wclk_sel[] = {
190 "lsp1_104M_wclk",
191 "lsp1_26M_wclk",
192 };
193
194 static const char * const i2s_wclk_sel[] = {
195 "lsp0_104M_wclk",
196 "lsp0_26M_wclk",
197 };
198
zx_divtbl(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,const struct clk_div_table * table)199 static inline struct clk *zx_divtbl(const char *name, const char *parent,
200 void __iomem *reg, u8 shift, u8 width,
201 const struct clk_div_table *table)
202 {
203 return clk_register_divider_table(NULL, name, parent, 0, reg, shift,
204 width, 0, table, ®_lock);
205 }
206
zx_div(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)207 static inline struct clk *zx_div(const char *name, const char *parent,
208 void __iomem *reg, u8 shift, u8 width)
209 {
210 return clk_register_divider(NULL, name, parent, 0,
211 reg, shift, width, 0, ®_lock);
212 }
213
zx_mux(const char * name,const char * const * parents,int num_parents,void __iomem * reg,u8 shift,u8 width)214 static inline struct clk *zx_mux(const char *name, const char * const *parents,
215 int num_parents, void __iomem *reg, u8 shift, u8 width)
216 {
217 return clk_register_mux(NULL, name, parents, num_parents,
218 0, reg, shift, width, 0, ®_lock);
219 }
220
zx_gate(const char * name,const char * parent,void __iomem * reg,u8 shift)221 static inline struct clk *zx_gate(const char *name, const char *parent,
222 void __iomem *reg, u8 shift)
223 {
224 return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED,
225 reg, shift, CLK_SET_RATE_PARENT, ®_lock);
226 }
227
zx296702_top_clocks_init(struct device_node * np)228 static void __init zx296702_top_clocks_init(struct device_node *np)
229 {
230 struct clk **clk = topclk;
231 int i;
232
233 topcrm_base = of_iomap(np, 0);
234 WARN_ON(!topcrm_base);
235
236 clk[ZX296702_OSC] =
237 clk_register_fixed_rate(NULL, "osc", NULL, 0, 30000000);
238 clk[ZX296702_PLL_A9] =
239 clk_register_zx_pll("pll_a9", "osc", 0, topcrm_base
240 + 0x01c, pll_a9_config,
241 ARRAY_SIZE(pll_a9_config), ®_lock);
242
243 /* TODO: pll_a9_350M look like changeble follow a9 pll */
244 clk[ZX296702_PLL_A9_350M] =
245 clk_register_fixed_rate(NULL, "pll_a9_350M", "osc", 0,
246 350000000);
247 clk[ZX296702_PLL_MAC_1000M] =
248 clk_register_fixed_rate(NULL, "pll_mac_1000M", "osc", 0,
249 1000000000);
250 clk[ZX296702_PLL_MAC_333M] =
251 clk_register_fixed_rate(NULL, "pll_mac_333M", "osc", 0,
252 333000000);
253 clk[ZX296702_PLL_MM0_1188M] =
254 clk_register_fixed_rate(NULL, "pll_mm0_1188M", "osc", 0,
255 1188000000);
256 clk[ZX296702_PLL_MM0_396M] =
257 clk_register_fixed_rate(NULL, "pll_mm0_396M", "osc", 0,
258 396000000);
259 clk[ZX296702_PLL_MM0_198M] =
260 clk_register_fixed_rate(NULL, "pll_mm0_198M", "osc", 0,
261 198000000);
262 clk[ZX296702_PLL_MM1_108M] =
263 clk_register_fixed_rate(NULL, "pll_mm1_108M", "osc", 0,
264 108000000);
265 clk[ZX296702_PLL_MM1_72M] =
266 clk_register_fixed_rate(NULL, "pll_mm1_72M", "osc", 0,
267 72000000);
268 clk[ZX296702_PLL_MM1_54M] =
269 clk_register_fixed_rate(NULL, "pll_mm1_54M", "osc", 0,
270 54000000);
271 clk[ZX296702_PLL_LSP_104M] =
272 clk_register_fixed_rate(NULL, "pll_lsp_104M", "osc", 0,
273 104000000);
274 clk[ZX296702_PLL_LSP_26M] =
275 clk_register_fixed_rate(NULL, "pll_lsp_26M", "osc", 0,
276 26000000);
277 clk[ZX296702_PLL_DDR_266M] =
278 clk_register_fixed_rate(NULL, "pll_ddr_266M", "osc", 0,
279 266000000);
280 clk[ZX296702_PLL_AUDIO_294M912] =
281 clk_register_fixed_rate(NULL, "pll_audio_294M912", "osc", 0,
282 294912000);
283
284 /* bus clock */
285 clk[ZX296702_MATRIX_ACLK] =
286 zx_mux("matrix_aclk", matrix_aclk_sel,
287 ARRAY_SIZE(matrix_aclk_sel), CLK_MUX, 2, 2);
288 clk[ZX296702_MAIN_HCLK] =
289 zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2,
290 main_hlk_div);
291 clk[ZX296702_MAIN_PCLK] =
292 zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2,
293 main_hlk_div);
294
295 /* cpu clock */
296 clk[ZX296702_CLK_500] =
297 clk_register_fixed_factor(NULL, "clk_500", "pll_mac_1000M", 0,
298 1, 2);
299 clk[ZX296702_CLK_250] =
300 clk_register_fixed_factor(NULL, "clk_250", "pll_mac_1000M", 0,
301 1, 4);
302 clk[ZX296702_CLK_125] =
303 clk_register_fixed_factor(NULL, "clk_125", "clk_250", 0, 1, 2);
304 clk[ZX296702_CLK_148M5] =
305 clk_register_fixed_factor(NULL, "clk_148M5", "pll_mm0_1188M", 0,
306 1, 8);
307 clk[ZX296702_CLK_74M25] =
308 clk_register_fixed_factor(NULL, "clk_74M25", "pll_mm0_1188M", 0,
309 1, 16);
310 clk[ZX296702_A9_WCLK] =
311 zx_mux("a9_wclk", a9_wclk_sel, ARRAY_SIZE(a9_wclk_sel), CLK_MUX,
312 0, 2);
313 clk[ZX296702_A9_AS1_ACLK_MUX] =
314 zx_mux("a9_as1_aclk_mux", a9_as1_aclk_sel,
315 ARRAY_SIZE(a9_as1_aclk_sel), CLK_MUX, 4, 2);
316 clk[ZX296702_A9_TRACE_CLKIN_MUX] =
317 zx_mux("a9_trace_clkin_mux", a9_trace_clkin_sel,
318 ARRAY_SIZE(a9_trace_clkin_sel), CLK_MUX1, 0, 2);
319 clk[ZX296702_A9_AS1_ACLK_DIV] =
320 zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2,
321 a9_as1_aclk_divider);
322
323 /* multi-media clock */
324 clk[ZX296702_CLK_2] =
325 clk_register_fixed_factor(NULL, "clk_2", "pll_mm1_72M", 0,
326 1, 36);
327 clk[ZX296702_CLK_27] =
328 clk_register_fixed_factor(NULL, "clk_27", "pll_mm1_54M", 0,
329 1, 2);
330 clk[ZX296702_DECPPU_ACLK_MUX] =
331 zx_mux("decppu_aclk_mux", decppu_aclk_sel,
332 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 6, 2);
333 clk[ZX296702_PPU_ACLK_MUX] =
334 zx_mux("ppu_aclk_mux", decppu_aclk_sel,
335 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 8, 2);
336 clk[ZX296702_MALI400_ACLK_MUX] =
337 zx_mux("mali400_aclk_mux", decppu_aclk_sel,
338 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 12, 2);
339 clk[ZX296702_VOU_ACLK_MUX] =
340 zx_mux("vou_aclk_mux", decppu_aclk_sel,
341 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 10, 2);
342 clk[ZX296702_VOU_MAIN_WCLK_MUX] =
343 zx_mux("vou_main_wclk_mux", vou_main_wclk_sel,
344 ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 14, 2);
345 clk[ZX296702_VOU_AUX_WCLK_MUX] =
346 zx_mux("vou_aux_wclk_mux", vou_main_wclk_sel,
347 ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 16, 2);
348 clk[ZX296702_VOU_SCALER_WCLK_MUX] =
349 zx_mux("vou_scaler_wclk_mux", vou_scaler_wclk_sel,
350 ARRAY_SIZE(vou_scaler_wclk_sel), CLK_MUX,
351 18, 2);
352 clk[ZX296702_R2D_ACLK_MUX] =
353 zx_mux("r2d_aclk_mux", decppu_aclk_sel,
354 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 20, 2);
355 clk[ZX296702_R2D_WCLK_MUX] =
356 zx_mux("r2d_wclk_mux", r2d_wclk_sel,
357 ARRAY_SIZE(r2d_wclk_sel), CLK_MUX, 22, 2);
358
359 /* other clock */
360 clk[ZX296702_CLK_50] =
361 clk_register_fixed_factor(NULL, "clk_50", "pll_mac_1000M",
362 0, 1, 20);
363 clk[ZX296702_CLK_25] =
364 clk_register_fixed_factor(NULL, "clk_25", "pll_mac_1000M",
365 0, 1, 40);
366 clk[ZX296702_CLK_12] =
367 clk_register_fixed_factor(NULL, "clk_12", "pll_mm1_72M",
368 0, 1, 6);
369 clk[ZX296702_CLK_16M384] =
370 clk_register_fixed_factor(NULL, "clk_16M384",
371 "pll_audio_294M912", 0, 1, 18);
372 clk[ZX296702_CLK_32K768] =
373 clk_register_fixed_factor(NULL, "clk_32K768", "clk_16M384",
374 0, 1, 500);
375 clk[ZX296702_SEC_WCLK_DIV] =
376 zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3,
377 sec_wclk_divider);
378 clk[ZX296702_DDR_WCLK_MUX] =
379 zx_mux("ddr_wclk_mux", ddr_wclk_sel,
380 ARRAY_SIZE(ddr_wclk_sel), CLK_MUX, 24, 2);
381 clk[ZX296702_NAND_WCLK_MUX] =
382 zx_mux("nand_wclk_mux", nand_wclk_sel,
383 ARRAY_SIZE(nand_wclk_sel), CLK_MUX, 24, 2);
384 clk[ZX296702_LSP_26_WCLK_MUX] =
385 zx_mux("lsp_26_wclk_mux", lsp_26_wclk_sel,
386 ARRAY_SIZE(lsp_26_wclk_sel), CLK_MUX, 27, 1);
387
388 /* gates */
389 clk[ZX296702_A9_AS0_ACLK] =
390 zx_gate("a9_as0_aclk", "matrix_aclk", CLK_EN0, 0);
391 clk[ZX296702_A9_AS1_ACLK] =
392 zx_gate("a9_as1_aclk", "a9_as1_aclk_div", CLK_EN0, 1);
393 clk[ZX296702_A9_TRACE_CLKIN] =
394 zx_gate("a9_trace_clkin", "a9_trace_clkin_mux", CLK_EN0, 2);
395 clk[ZX296702_DECPPU_AXI_M_ACLK] =
396 zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3);
397 clk[ZX296702_DECPPU_AHB_S_HCLK] =
398 zx_gate("decppu_ahb_s_hclk", "main_hclk", CLK_EN0, 4);
399 clk[ZX296702_PPU_AXI_M_ACLK] =
400 zx_gate("ppu_axi_m_aclk", "ppu_aclk_mux", CLK_EN0, 5);
401 clk[ZX296702_PPU_AHB_S_HCLK] =
402 zx_gate("ppu_ahb_s_hclk", "main_hclk", CLK_EN0, 6);
403 clk[ZX296702_VOU_AXI_M_ACLK] =
404 zx_gate("vou_axi_m_aclk", "vou_aclk_mux", CLK_EN0, 7);
405 clk[ZX296702_VOU_APB_PCLK] =
406 zx_gate("vou_apb_pclk", "main_pclk", CLK_EN0, 8);
407 clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] =
408 zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux",
409 CLK_EN0, 9);
410 clk[ZX296702_VOU_AUX_CHANNEL_WCLK] =
411 zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux",
412 CLK_EN0, 10);
413 clk[ZX296702_VOU_HDMI_OSCLK_CEC] =
414 zx_gate("vou_hdmi_osclk_cec", "clk_2", CLK_EN0, 11);
415 clk[ZX296702_VOU_SCALER_WCLK] =
416 zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12);
417 clk[ZX296702_MALI400_AXI_M_ACLK] =
418 zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13);
419 clk[ZX296702_MALI400_APB_PCLK] =
420 zx_gate("mali400_apb_pclk", "main_pclk", CLK_EN0, 14);
421 clk[ZX296702_R2D_WCLK] =
422 zx_gate("r2d_wclk", "r2d_wclk_mux", CLK_EN0, 15);
423 clk[ZX296702_R2D_AXI_M_ACLK] =
424 zx_gate("r2d_axi_m_aclk", "r2d_aclk_mux", CLK_EN0, 16);
425 clk[ZX296702_R2D_AHB_HCLK] =
426 zx_gate("r2d_ahb_hclk", "main_hclk", CLK_EN0, 17);
427 clk[ZX296702_DDR3_AXI_S0_ACLK] =
428 zx_gate("ddr3_axi_s0_aclk", "matrix_aclk", CLK_EN0, 18);
429 clk[ZX296702_DDR3_APB_PCLK] =
430 zx_gate("ddr3_apb_pclk", "main_pclk", CLK_EN0, 19);
431 clk[ZX296702_DDR3_WCLK] =
432 zx_gate("ddr3_wclk", "ddr_wclk_mux", CLK_EN0, 20);
433 clk[ZX296702_USB20_0_AHB_HCLK] =
434 zx_gate("usb20_0_ahb_hclk", "main_hclk", CLK_EN0, 21);
435 clk[ZX296702_USB20_0_EXTREFCLK] =
436 zx_gate("usb20_0_extrefclk", "clk_12", CLK_EN0, 22);
437 clk[ZX296702_USB20_1_AHB_HCLK] =
438 zx_gate("usb20_1_ahb_hclk", "main_hclk", CLK_EN0, 23);
439 clk[ZX296702_USB20_1_EXTREFCLK] =
440 zx_gate("usb20_1_extrefclk", "clk_12", CLK_EN0, 24);
441 clk[ZX296702_USB20_2_AHB_HCLK] =
442 zx_gate("usb20_2_ahb_hclk", "main_hclk", CLK_EN0, 25);
443 clk[ZX296702_USB20_2_EXTREFCLK] =
444 zx_gate("usb20_2_extrefclk", "clk_12", CLK_EN0, 26);
445 clk[ZX296702_GMAC_AXI_M_ACLK] =
446 zx_gate("gmac_axi_m_aclk", "matrix_aclk", CLK_EN0, 27);
447 clk[ZX296702_GMAC_APB_PCLK] =
448 zx_gate("gmac_apb_pclk", "main_pclk", CLK_EN0, 28);
449 clk[ZX296702_GMAC_125_CLKIN] =
450 zx_gate("gmac_125_clkin", "clk_125", CLK_EN0, 29);
451 clk[ZX296702_GMAC_RMII_CLKIN] =
452 zx_gate("gmac_rmii_clkin", "clk_50", CLK_EN0, 30);
453 clk[ZX296702_GMAC_25M_CLK] =
454 zx_gate("gmac_25M_clk", "clk_25", CLK_EN0, 31);
455 clk[ZX296702_NANDFLASH_AHB_HCLK] =
456 zx_gate("nandflash_ahb_hclk", "main_hclk", CLK_EN1, 0);
457 clk[ZX296702_NANDFLASH_WCLK] =
458 zx_gate("nandflash_wclk", "nand_wclk_mux", CLK_EN1, 1);
459 clk[ZX296702_LSP0_APB_PCLK] =
460 zx_gate("lsp0_apb_pclk", "main_pclk", CLK_EN1, 2);
461 clk[ZX296702_LSP0_AHB_HCLK] =
462 zx_gate("lsp0_ahb_hclk", "main_hclk", CLK_EN1, 3);
463 clk[ZX296702_LSP0_26M_WCLK] =
464 zx_gate("lsp0_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 4);
465 clk[ZX296702_LSP0_104M_WCLK] =
466 zx_gate("lsp0_104M_wclk", "pll_lsp_104M", CLK_EN1, 5);
467 clk[ZX296702_LSP0_16M384_WCLK] =
468 zx_gate("lsp0_16M384_wclk", "clk_16M384", CLK_EN1, 6);
469 clk[ZX296702_LSP1_APB_PCLK] =
470 zx_gate("lsp1_apb_pclk", "main_pclk", CLK_EN1, 7);
471 /* FIXME: wclk enable bit is bit8. We hack it as reserved 31 for
472 * UART does not work after parent clk is disabled/enabled */
473 clk[ZX296702_LSP1_26M_WCLK] =
474 zx_gate("lsp1_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 31);
475 clk[ZX296702_LSP1_104M_WCLK] =
476 zx_gate("lsp1_104M_wclk", "pll_lsp_104M", CLK_EN1, 9);
477 clk[ZX296702_LSP1_32K_CLK] =
478 zx_gate("lsp1_32K_clk", "clk_32K768", CLK_EN1, 10);
479 clk[ZX296702_AON_HCLK] =
480 zx_gate("aon_hclk", "main_hclk", CLK_EN1, 11);
481 clk[ZX296702_SYS_CTRL_PCLK] =
482 zx_gate("sys_ctrl_pclk", "main_pclk", CLK_EN1, 12);
483 clk[ZX296702_DMA_PCLK] =
484 zx_gate("dma_pclk", "main_pclk", CLK_EN1, 13);
485 clk[ZX296702_DMA_ACLK] =
486 zx_gate("dma_aclk", "matrix_aclk", CLK_EN1, 14);
487 clk[ZX296702_SEC_HCLK] =
488 zx_gate("sec_hclk", "main_hclk", CLK_EN1, 15);
489 clk[ZX296702_AES_WCLK] =
490 zx_gate("aes_wclk", "sec_wclk_div", CLK_EN1, 16);
491 clk[ZX296702_DES_WCLK] =
492 zx_gate("des_wclk", "sec_wclk_div", CLK_EN1, 17);
493 clk[ZX296702_IRAM_ACLK] =
494 zx_gate("iram_aclk", "matrix_aclk", CLK_EN1, 18);
495 clk[ZX296702_IROM_ACLK] =
496 zx_gate("irom_aclk", "matrix_aclk", CLK_EN1, 19);
497 clk[ZX296702_BOOT_CTRL_HCLK] =
498 zx_gate("boot_ctrl_hclk", "main_hclk", CLK_EN1, 20);
499 clk[ZX296702_EFUSE_CLK_30] =
500 zx_gate("efuse_clk_30", "osc", CLK_EN1, 21);
501
502 /* TODO: add VOU Local clocks */
503 clk[ZX296702_VOU_MAIN_CHANNEL_DIV] =
504 zx_div("vou_main_channel_div", "vou_main_channel_wclk",
505 VOU_LOCAL_DIV2_SET, 1, 1);
506 clk[ZX296702_VOU_AUX_CHANNEL_DIV] =
507 zx_div("vou_aux_channel_div", "vou_aux_channel_wclk",
508 VOU_LOCAL_DIV2_SET, 0, 1);
509 clk[ZX296702_VOU_TV_ENC_HD_DIV] =
510 zx_div("vou_tv_enc_hd_div", "vou_tv_enc_hd_mux",
511 VOU_LOCAL_DIV2_SET, 3, 1);
512 clk[ZX296702_VOU_TV_ENC_SD_DIV] =
513 zx_div("vou_tv_enc_sd_div", "vou_tv_enc_sd_mux",
514 VOU_LOCAL_DIV2_SET, 2, 1);
515 clk[ZX296702_VL0_MUX] =
516 zx_mux("vl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
517 VOU_LOCAL_CLKSEL, 8, 1);
518 clk[ZX296702_VL1_MUX] =
519 zx_mux("vl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
520 VOU_LOCAL_CLKSEL, 9, 1);
521 clk[ZX296702_VL2_MUX] =
522 zx_mux("vl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
523 VOU_LOCAL_CLKSEL, 10, 1);
524 clk[ZX296702_GL0_MUX] =
525 zx_mux("gl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
526 VOU_LOCAL_CLKSEL, 5, 1);
527 clk[ZX296702_GL1_MUX] =
528 zx_mux("gl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
529 VOU_LOCAL_CLKSEL, 6, 1);
530 clk[ZX296702_GL2_MUX] =
531 zx_mux("gl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
532 VOU_LOCAL_CLKSEL, 7, 1);
533 clk[ZX296702_WB_MUX] =
534 zx_mux("wb_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
535 VOU_LOCAL_CLKSEL, 11, 1);
536 clk[ZX296702_HDMI_MUX] =
537 zx_mux("hdmi_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
538 VOU_LOCAL_CLKSEL, 4, 1);
539 clk[ZX296702_VOU_TV_ENC_HD_MUX] =
540 zx_mux("vou_tv_enc_hd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
541 VOU_LOCAL_CLKSEL, 3, 1);
542 clk[ZX296702_VOU_TV_ENC_SD_MUX] =
543 zx_mux("vou_tv_enc_sd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
544 VOU_LOCAL_CLKSEL, 2, 1);
545 clk[ZX296702_VL0_CLK] =
546 zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8);
547 clk[ZX296702_VL1_CLK] =
548 zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9);
549 clk[ZX296702_VL2_CLK] =
550 zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10);
551 clk[ZX296702_GL0_CLK] =
552 zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5);
553 clk[ZX296702_GL1_CLK] =
554 zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6);
555 clk[ZX296702_GL2_CLK] =
556 zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7);
557 clk[ZX296702_WB_CLK] =
558 zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11);
559 clk[ZX296702_CL_CLK] =
560 zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12);
561 clk[ZX296702_MAIN_MIX_CLK] =
562 zx_gate("main_mix_clk", "vou_main_channel_div",
563 VOU_LOCAL_CLKEN, 4);
564 clk[ZX296702_AUX_MIX_CLK] =
565 zx_gate("aux_mix_clk", "vou_aux_channel_div",
566 VOU_LOCAL_CLKEN, 3);
567 clk[ZX296702_HDMI_CLK] =
568 zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2);
569 clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] =
570 zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div",
571 VOU_LOCAL_CLKEN, 1);
572 clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] =
573 zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div",
574 VOU_LOCAL_CLKEN, 0);
575
576 /* CA9 PERIPHCLK = a9_wclk / 2 */
577 clk[ZX296702_A9_PERIPHCLK] =
578 clk_register_fixed_factor(NULL, "a9_periphclk", "a9_wclk",
579 0, 1, 2);
580
581 for (i = 0; i < ARRAY_SIZE(topclk); i++) {
582 if (IS_ERR(clk[i])) {
583 pr_err("zx296702 clk %d: register failed with %ld\n",
584 i, PTR_ERR(clk[i]));
585 return;
586 }
587 }
588
589 topclk_data.clks = topclk;
590 topclk_data.clk_num = ARRAY_SIZE(topclk);
591 of_clk_add_provider(np, of_clk_src_onecell_get, &topclk_data);
592 }
593 CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
594 zx296702_top_clocks_init);
595
zx296702_lsp0_clocks_init(struct device_node * np)596 static void __init zx296702_lsp0_clocks_init(struct device_node *np)
597 {
598 struct clk **clk = lsp0clk;
599 int i;
600
601 lsp0crpm_base = of_iomap(np, 0);
602 WARN_ON(!lsp0crpm_base);
603
604 /* SDMMC1 */
605 clk[ZX296702_SDMMC1_WCLK_MUX] =
606 zx_mux("sdmmc1_wclk_mux", sdmmc1_wclk_sel,
607 ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1);
608 clk[ZX296702_SDMMC1_WCLK_DIV] =
609 zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4);
610 clk[ZX296702_SDMMC1_WCLK] =
611 zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
612 clk[ZX296702_SDMMC1_PCLK] =
613 zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
614
615 clk[ZX296702_GPIO_CLK] =
616 zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
617
618 /* SPDIF */
619 clk[ZX296702_SPDIF0_WCLK_MUX] =
620 zx_mux("spdif0_wclk_mux", spdif0_wclk_sel,
621 ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1);
622 clk[ZX296702_SPDIF0_WCLK] =
623 zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
624 clk[ZX296702_SPDIF0_PCLK] =
625 zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
626
627 clk[ZX296702_SPDIF0_DIV] =
628 clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0,
629 SPDIF0_DIV);
630
631 /* I2S */
632 clk[ZX296702_I2S0_WCLK_MUX] =
633 zx_mux("i2s0_wclk_mux", i2s_wclk_sel,
634 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1);
635 clk[ZX296702_I2S0_WCLK] =
636 zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
637 clk[ZX296702_I2S0_PCLK] =
638 zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
639
640 clk[ZX296702_I2S0_DIV] =
641 clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV);
642
643 clk[ZX296702_I2S1_WCLK_MUX] =
644 zx_mux("i2s1_wclk_mux", i2s_wclk_sel,
645 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1);
646 clk[ZX296702_I2S1_WCLK] =
647 zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
648 clk[ZX296702_I2S1_PCLK] =
649 zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
650
651 clk[ZX296702_I2S1_DIV] =
652 clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV);
653
654 clk[ZX296702_I2S2_WCLK_MUX] =
655 zx_mux("i2s2_wclk_mux", i2s_wclk_sel,
656 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1);
657 clk[ZX296702_I2S2_WCLK] =
658 zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
659 clk[ZX296702_I2S2_PCLK] =
660 zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
661
662 clk[ZX296702_I2S2_DIV] =
663 clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV);
664
665 for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) {
666 if (IS_ERR(clk[i])) {
667 pr_err("zx296702 clk %d: register failed with %ld\n",
668 i, PTR_ERR(clk[i]));
669 return;
670 }
671 }
672
673 lsp0clk_data.clks = lsp0clk;
674 lsp0clk_data.clk_num = ARRAY_SIZE(lsp0clk);
675 of_clk_add_provider(np, of_clk_src_onecell_get, &lsp0clk_data);
676 }
677 CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
678 zx296702_lsp0_clocks_init);
679
zx296702_lsp1_clocks_init(struct device_node * np)680 static void __init zx296702_lsp1_clocks_init(struct device_node *np)
681 {
682 struct clk **clk = lsp1clk;
683 int i;
684
685 lsp1crpm_base = of_iomap(np, 0);
686 WARN_ON(!lsp1crpm_base);
687
688 /* UART0 */
689 clk[ZX296702_UART0_WCLK_MUX] =
690 zx_mux("uart0_wclk_mux", uart_wclk_sel,
691 ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1);
692 /* FIXME: uart wclk enable bit is bit1 in. We hack it as reserved 31 for
693 * UART does not work after parent clk is disabled/enabled */
694 clk[ZX296702_UART0_WCLK] =
695 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31);
696 clk[ZX296702_UART0_PCLK] =
697 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0);
698
699 /* UART1 */
700 clk[ZX296702_UART1_WCLK_MUX] =
701 zx_mux("uart1_wclk_mux", uart_wclk_sel,
702 ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1);
703 clk[ZX296702_UART1_WCLK] =
704 zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1);
705 clk[ZX296702_UART1_PCLK] =
706 zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0);
707
708 /* SDMMC0 */
709 clk[ZX296702_SDMMC0_WCLK_MUX] =
710 zx_mux("sdmmc0_wclk_mux", sdmmc0_wclk_sel,
711 ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1);
712 clk[ZX296702_SDMMC0_WCLK_DIV] =
713 zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4);
714 clk[ZX296702_SDMMC0_WCLK] =
715 zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1);
716 clk[ZX296702_SDMMC0_PCLK] =
717 zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
718
719 clk[ZX296702_SPDIF1_WCLK_MUX] =
720 zx_mux("spdif1_wclk_mux", spdif1_wclk_sel,
721 ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1);
722 clk[ZX296702_SPDIF1_WCLK] =
723 zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
724 clk[ZX296702_SPDIF1_PCLK] =
725 zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);
726
727 clk[ZX296702_SPDIF1_DIV] =
728 clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0,
729 SPDIF1_DIV);
730
731 for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) {
732 if (IS_ERR(clk[i])) {
733 pr_err("zx296702 clk %d: register failed with %ld\n",
734 i, PTR_ERR(clk[i]));
735 return;
736 }
737 }
738
739 lsp1clk_data.clks = lsp1clk;
740 lsp1clk_data.clk_num = ARRAY_SIZE(lsp1clk);
741 of_clk_add_provider(np, of_clk_src_onecell_get, &lsp1clk_data);
742 }
743 CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",
744 zx296702_lsp1_clocks_init);
745
