1 /*
2  * Renesas Clock Pulse Generator / Module Standby and Software Reset
3  *
4  * Copyright (C) 2015 Glider bvba
5  *
6  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
7  *
8  * Copyright (C) 2013 Ideas On Board SPRL
9  * Copyright (C) 2015 Renesas Electronics Corp.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; version 2 of the License.
14  */
15 
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/clk/renesas.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/init.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_clock.h>
28 #include <linux/pm_domain.h>
29 #include <linux/psci.h>
30 #include <linux/reset-controller.h>
31 #include <linux/slab.h>
32 
33 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 
35 #include "renesas-cpg-mssr.h"
36 #include "clk-div6.h"
37 
38 #ifdef DEBUG
39 #define WARN_DEBUG(x)	WARN_ON(x)
40 #else
41 #define WARN_DEBUG(x)	do { } while (0)
42 #endif
43 
44 
45 /*
46  * Module Standby and Software Reset register offets.
47  *
48  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
49  * R-Car Gen2, R-Car Gen3, and RZ/G1.
50  * These are NOT valid for R-Car Gen1 and RZ/A1!
51  */
52 
53 /*
54  * Module Stop Status Register offsets
55  */
56 
57 static const u16 mstpsr[] = {
58 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
59 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
60 };
61 
62 #define	MSTPSR(i)	mstpsr[i]
63 
64 
65 /*
66  * System Module Stop Control Register offsets
67  */
68 
69 static const u16 smstpcr[] = {
70 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
71 	0x990, 0x994, 0x998, 0x99C,
72 };
73 
74 #define	SMSTPCR(i)	smstpcr[i]
75 
76 
77 /*
78  * Software Reset Register offsets
79  */
80 
81 static const u16 srcr[] = {
82 	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
83 	0x920, 0x924, 0x928, 0x92C,
84 };
85 
86 #define	SRCR(i)		srcr[i]
87 
88 
89 /* Realtime Module Stop Control Register offsets */
90 #define RMSTPCR(i)	(smstpcr[i] - 0x20)
91 
92 /* Modem Module Stop Control Register offsets (r8a73a4) */
93 #define MMSTPCR(i)	(smstpcr[i] + 0x20)
94 
95 /* Software Reset Clearing Register offsets */
96 #define	SRSTCLR(i)	(0x940 + (i) * 4)
97 
98 
99 /**
100  * Clock Pulse Generator / Module Standby and Software Reset Private Data
101  *
102  * @rcdev: Optional reset controller entity
103  * @dev: CPG/MSSR device
104  * @base: CPG/MSSR register block base address
105  * @rmw_lock: protects RMW register accesses
106  * @clks: Array containing all Core and Module Clocks
107  * @num_core_clks: Number of Core Clocks in clks[]
108  * @num_mod_clks: Number of Module Clocks in clks[]
109  * @last_dt_core_clk: ID of the last Core Clock exported to DT
110  * @notifiers: Notifier chain to save/restore clock state for system resume
111  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
112  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
113  */
114 struct cpg_mssr_priv {
115 #ifdef CONFIG_RESET_CONTROLLER
116 	struct reset_controller_dev rcdev;
117 #endif
118 	struct device *dev;
119 	void __iomem *base;
120 	spinlock_t rmw_lock;
121 
122 	struct clk **clks;
123 	unsigned int num_core_clks;
124 	unsigned int num_mod_clks;
125 	unsigned int last_dt_core_clk;
126 
127 	struct raw_notifier_head notifiers;
128 	struct {
129 		u32 mask;
130 		u32 val;
131 	} smstpcr_saved[ARRAY_SIZE(smstpcr)];
132 };
133 
134 
135 /**
136  * struct mstp_clock - MSTP gating clock
137  * @hw: handle between common and hardware-specific interfaces
138  * @index: MSTP clock number
139  * @priv: CPG/MSSR private data
140  */
141 struct mstp_clock {
142 	struct clk_hw hw;
143 	u32 index;
144 	struct cpg_mssr_priv *priv;
145 };
146 
147 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
148 
cpg_mstp_clock_endisable(struct clk_hw * hw,bool enable)149 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
150 {
151 	struct mstp_clock *clock = to_mstp_clock(hw);
152 	struct cpg_mssr_priv *priv = clock->priv;
153 	unsigned int reg = clock->index / 32;
154 	unsigned int bit = clock->index % 32;
155 	struct device *dev = priv->dev;
156 	u32 bitmask = BIT(bit);
157 	unsigned long flags;
158 	unsigned int i;
159 	u32 value;
160 
161 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
162 		enable ? "ON" : "OFF");
163 	spin_lock_irqsave(&priv->rmw_lock, flags);
164 
165 	value = readl(priv->base + SMSTPCR(reg));
166 	if (enable)
167 		value &= ~bitmask;
168 	else
169 		value |= bitmask;
170 	writel(value, priv->base + SMSTPCR(reg));
171 
172 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
173 
174 	if (!enable)
175 		return 0;
176 
177 	for (i = 1000; i > 0; --i) {
178 		if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
179 			break;
180 		cpu_relax();
181 	}
182 
183 	if (!i) {
184 		dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
185 			priv->base + SMSTPCR(reg), bit);
186 		return -ETIMEDOUT;
187 	}
188 
189 	return 0;
190 }
191 
cpg_mstp_clock_enable(struct clk_hw * hw)192 static int cpg_mstp_clock_enable(struct clk_hw *hw)
193 {
194 	return cpg_mstp_clock_endisable(hw, true);
195 }
196 
cpg_mstp_clock_disable(struct clk_hw * hw)197 static void cpg_mstp_clock_disable(struct clk_hw *hw)
198 {
199 	cpg_mstp_clock_endisable(hw, false);
200 }
201 
cpg_mstp_clock_is_enabled(struct clk_hw * hw)202 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
203 {
204 	struct mstp_clock *clock = to_mstp_clock(hw);
205 	struct cpg_mssr_priv *priv = clock->priv;
206 	u32 value;
207 
208 	value = readl(priv->base + MSTPSR(clock->index / 32));
209 
210 	return !(value & BIT(clock->index % 32));
211 }
212 
213 static const struct clk_ops cpg_mstp_clock_ops = {
214 	.enable = cpg_mstp_clock_enable,
215 	.disable = cpg_mstp_clock_disable,
216 	.is_enabled = cpg_mstp_clock_is_enabled,
217 };
218 
219 static
cpg_mssr_clk_src_twocell_get(struct of_phandle_args * clkspec,void * data)220 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
221 					 void *data)
222 {
223 	unsigned int clkidx = clkspec->args[1];
224 	struct cpg_mssr_priv *priv = data;
225 	struct device *dev = priv->dev;
226 	unsigned int idx;
227 	const char *type;
228 	struct clk *clk;
229 
230 	switch (clkspec->args[0]) {
231 	case CPG_CORE:
232 		type = "core";
233 		if (clkidx > priv->last_dt_core_clk) {
234 			dev_err(dev, "Invalid %s clock index %u\n", type,
235 			       clkidx);
236 			return ERR_PTR(-EINVAL);
237 		}
238 		clk = priv->clks[clkidx];
239 		break;
240 
241 	case CPG_MOD:
242 		type = "module";
243 		idx = MOD_CLK_PACK(clkidx);
244 		if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
245 			dev_err(dev, "Invalid %s clock index %u\n", type,
246 				clkidx);
247 			return ERR_PTR(-EINVAL);
248 		}
249 		clk = priv->clks[priv->num_core_clks + idx];
250 		break;
251 
252 	default:
253 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
254 		return ERR_PTR(-EINVAL);
255 	}
256 
257 	if (IS_ERR(clk))
258 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
259 		       PTR_ERR(clk));
260 	else
261 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
262 			clkspec->args[0], clkspec->args[1], clk,
263 			clk_get_rate(clk));
264 	return clk;
265 }
266 
cpg_mssr_register_core_clk(const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct cpg_mssr_priv * priv)267 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
268 					      const struct cpg_mssr_info *info,
269 					      struct cpg_mssr_priv *priv)
270 {
271 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
272 	struct device *dev = priv->dev;
273 	unsigned int id = core->id, div = core->div;
274 	const char *parent_name;
275 
276 	WARN_DEBUG(id >= priv->num_core_clks);
277 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
278 
279 	if (!core->name) {
280 		/* Skip NULLified clock */
281 		return;
282 	}
283 
284 	switch (core->type) {
285 	case CLK_TYPE_IN:
286 		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
287 		break;
288 
289 	case CLK_TYPE_FF:
290 	case CLK_TYPE_DIV6P1:
291 	case CLK_TYPE_DIV6_RO:
292 		WARN_DEBUG(core->parent >= priv->num_core_clks);
293 		parent = priv->clks[core->parent];
294 		if (IS_ERR(parent)) {
295 			clk = parent;
296 			goto fail;
297 		}
298 
299 		parent_name = __clk_get_name(parent);
300 
301 		if (core->type == CLK_TYPE_DIV6_RO)
302 			/* Multiply with the DIV6 register value */
303 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;
304 
305 		if (core->type == CLK_TYPE_DIV6P1) {
306 			clk = cpg_div6_register(core->name, 1, &parent_name,
307 						priv->base + core->offset,
308 						&priv->notifiers);
309 		} else {
310 			clk = clk_register_fixed_factor(NULL, core->name,
311 							parent_name, 0,
312 							core->mult, div);
313 		}
314 		break;
315 
316 	default:
317 		if (info->cpg_clk_register)
318 			clk = info->cpg_clk_register(dev, core, info,
319 						     priv->clks, priv->base,
320 						     &priv->notifiers);
321 		else
322 			dev_err(dev, "%s has unsupported core clock type %u\n",
323 				core->name, core->type);
324 		break;
325 	}
326 
327 	if (IS_ERR_OR_NULL(clk))
328 		goto fail;
329 
330 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
331 	priv->clks[id] = clk;
332 	return;
333 
334 fail:
335 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
336 		core->name, PTR_ERR(clk));
337 }
338 
cpg_mssr_register_mod_clk(const struct mssr_mod_clk * mod,const struct cpg_mssr_info * info,struct cpg_mssr_priv * priv)339 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
340 					     const struct cpg_mssr_info *info,
341 					     struct cpg_mssr_priv *priv)
342 {
343 	struct mstp_clock *clock = NULL;
344 	struct device *dev = priv->dev;
345 	unsigned int id = mod->id;
346 	struct clk_init_data init;
347 	struct clk *parent, *clk;
348 	const char *parent_name;
349 	unsigned int i;
350 
351 	WARN_DEBUG(id < priv->num_core_clks);
352 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
353 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
354 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
355 
356 	if (!mod->name) {
357 		/* Skip NULLified clock */
358 		return;
359 	}
360 
361 	parent = priv->clks[mod->parent];
362 	if (IS_ERR(parent)) {
363 		clk = parent;
364 		goto fail;
365 	}
366 
367 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
368 	if (!clock) {
369 		clk = ERR_PTR(-ENOMEM);
370 		goto fail;
371 	}
372 
373 	init.name = mod->name;
374 	init.ops = &cpg_mstp_clock_ops;
375 	init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
376 	for (i = 0; i < info->num_crit_mod_clks; i++)
377 		if (id == info->crit_mod_clks[i]) {
378 			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
379 				mod->name);
380 			init.flags |= CLK_IS_CRITICAL;
381 			break;
382 		}
383 
384 	parent_name = __clk_get_name(parent);
385 	init.parent_names = &parent_name;
386 	init.num_parents = 1;
387 
388 	clock->index = id - priv->num_core_clks;
389 	clock->priv = priv;
390 	clock->hw.init = &init;
391 
392 	clk = clk_register(NULL, &clock->hw);
393 	if (IS_ERR(clk))
394 		goto fail;
395 
396 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
397 	priv->clks[id] = clk;
398 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
399 	return;
400 
401 fail:
402 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
403 		mod->name, PTR_ERR(clk));
404 	kfree(clock);
405 }
406 
407 struct cpg_mssr_clk_domain {
408 	struct generic_pm_domain genpd;
409 	struct device_node *np;
410 	unsigned int num_core_pm_clks;
411 	unsigned int core_pm_clks[0];
412 };
413 
414 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
415 
cpg_mssr_is_pm_clk(const struct of_phandle_args * clkspec,struct cpg_mssr_clk_domain * pd)416 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
417 			       struct cpg_mssr_clk_domain *pd)
418 {
419 	unsigned int i;
420 
421 	if (clkspec->np != pd->np || clkspec->args_count != 2)
422 		return false;
423 
424 	switch (clkspec->args[0]) {
425 	case CPG_CORE:
426 		for (i = 0; i < pd->num_core_pm_clks; i++)
427 			if (clkspec->args[1] == pd->core_pm_clks[i])
428 				return true;
429 		return false;
430 
431 	case CPG_MOD:
432 		return true;
433 
434 	default:
435 		return false;
436 	}
437 }
438 
cpg_mssr_attach_dev(struct generic_pm_domain * unused,struct device * dev)439 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
440 {
441 	struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
442 	struct device_node *np = dev->of_node;
443 	struct of_phandle_args clkspec;
444 	struct clk *clk;
445 	int i = 0;
446 	int error;
447 
448 	if (!pd) {
449 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
450 		return -EPROBE_DEFER;
451 	}
452 
453 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
454 					   &clkspec)) {
455 		if (cpg_mssr_is_pm_clk(&clkspec, pd))
456 			goto found;
457 
458 		of_node_put(clkspec.np);
459 		i++;
460 	}
461 
462 	return 0;
463 
464 found:
465 	clk = of_clk_get_from_provider(&clkspec);
466 	of_node_put(clkspec.np);
467 
468 	if (IS_ERR(clk))
469 		return PTR_ERR(clk);
470 
471 	error = pm_clk_create(dev);
472 	if (error) {
473 		dev_err(dev, "pm_clk_create failed %d\n", error);
474 		goto fail_put;
475 	}
476 
477 	error = pm_clk_add_clk(dev, clk);
478 	if (error) {
479 		dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
480 		goto fail_destroy;
481 	}
482 
483 	return 0;
484 
485 fail_destroy:
486 	pm_clk_destroy(dev);
487 fail_put:
488 	clk_put(clk);
489 	return error;
490 }
491 
cpg_mssr_detach_dev(struct generic_pm_domain * unused,struct device * dev)492 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
493 {
494 	if (!pm_clk_no_clocks(dev))
495 		pm_clk_destroy(dev);
496 }
497 
cpg_mssr_add_clk_domain(struct device * dev,const unsigned int * core_pm_clks,unsigned int num_core_pm_clks)498 static int __init cpg_mssr_add_clk_domain(struct device *dev,
499 					  const unsigned int *core_pm_clks,
500 					  unsigned int num_core_pm_clks)
501 {
502 	struct device_node *np = dev->of_node;
503 	struct generic_pm_domain *genpd;
504 	struct cpg_mssr_clk_domain *pd;
505 	size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
506 
507 	pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
508 	if (!pd)
509 		return -ENOMEM;
510 
511 	pd->np = np;
512 	pd->num_core_pm_clks = num_core_pm_clks;
513 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
514 
515 	genpd = &pd->genpd;
516 	genpd->name = np->name;
517 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
518 	genpd->attach_dev = cpg_mssr_attach_dev;
519 	genpd->detach_dev = cpg_mssr_detach_dev;
520 	pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
521 	cpg_mssr_clk_domain = pd;
522 
523 	of_genpd_add_provider_simple(np, genpd);
524 	return 0;
525 }
526 
527 #ifdef CONFIG_RESET_CONTROLLER
528 
529 #define rcdev_to_priv(x)	container_of(x, struct cpg_mssr_priv, rcdev)
530 
cpg_mssr_reset(struct reset_controller_dev * rcdev,unsigned long id)531 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
532 			  unsigned long id)
533 {
534 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
535 	unsigned int reg = id / 32;
536 	unsigned int bit = id % 32;
537 	u32 bitmask = BIT(bit);
538 	unsigned long flags;
539 	u32 value;
540 
541 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
542 
543 	/* Reset module */
544 	spin_lock_irqsave(&priv->rmw_lock, flags);
545 	value = readl(priv->base + SRCR(reg));
546 	value |= bitmask;
547 	writel(value, priv->base + SRCR(reg));
548 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
549 
550 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
551 	udelay(35);
552 
553 	/* Release module from reset state */
554 	writel(bitmask, priv->base + SRSTCLR(reg));
555 
556 	return 0;
557 }
558 
cpg_mssr_assert(struct reset_controller_dev * rcdev,unsigned long id)559 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
560 {
561 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
562 	unsigned int reg = id / 32;
563 	unsigned int bit = id % 32;
564 	u32 bitmask = BIT(bit);
565 	unsigned long flags;
566 	u32 value;
567 
568 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
569 
570 	spin_lock_irqsave(&priv->rmw_lock, flags);
571 	value = readl(priv->base + SRCR(reg));
572 	value |= bitmask;
573 	writel(value, priv->base + SRCR(reg));
574 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
575 	return 0;
576 }
577 
cpg_mssr_deassert(struct reset_controller_dev * rcdev,unsigned long id)578 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
579 			     unsigned long id)
580 {
581 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
582 	unsigned int reg = id / 32;
583 	unsigned int bit = id % 32;
584 	u32 bitmask = BIT(bit);
585 
586 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
587 
588 	writel(bitmask, priv->base + SRSTCLR(reg));
589 	return 0;
590 }
591 
cpg_mssr_status(struct reset_controller_dev * rcdev,unsigned long id)592 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
593 			   unsigned long id)
594 {
595 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
596 	unsigned int reg = id / 32;
597 	unsigned int bit = id % 32;
598 	u32 bitmask = BIT(bit);
599 
600 	return !!(readl(priv->base + SRCR(reg)) & bitmask);
601 }
602 
603 static const struct reset_control_ops cpg_mssr_reset_ops = {
604 	.reset = cpg_mssr_reset,
605 	.assert = cpg_mssr_assert,
606 	.deassert = cpg_mssr_deassert,
607 	.status = cpg_mssr_status,
608 };
609 
cpg_mssr_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)610 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
611 				const struct of_phandle_args *reset_spec)
612 {
613 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
614 	unsigned int unpacked = reset_spec->args[0];
615 	unsigned int idx = MOD_CLK_PACK(unpacked);
616 
617 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
618 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
619 		return -EINVAL;
620 	}
621 
622 	return idx;
623 }
624 
cpg_mssr_reset_controller_register(struct cpg_mssr_priv * priv)625 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
626 {
627 	priv->rcdev.ops = &cpg_mssr_reset_ops;
628 	priv->rcdev.of_node = priv->dev->of_node;
629 	priv->rcdev.of_reset_n_cells = 1;
630 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
631 	priv->rcdev.nr_resets = priv->num_mod_clks;
632 	return devm_reset_controller_register(priv->dev, &priv->rcdev);
633 }
634 
635 #else /* !CONFIG_RESET_CONTROLLER */
cpg_mssr_reset_controller_register(struct cpg_mssr_priv * priv)636 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
637 {
638 	return 0;
639 }
640 #endif /* !CONFIG_RESET_CONTROLLER */
641 
642 
643 static const struct of_device_id cpg_mssr_match[] = {
644 #ifdef CONFIG_CLK_R8A7743
645 	{
646 		.compatible = "renesas,r8a7743-cpg-mssr",
647 		.data = &r8a7743_cpg_mssr_info,
648 	},
649 #endif
650 #ifdef CONFIG_CLK_R8A7745
651 	{
652 		.compatible = "renesas,r8a7745-cpg-mssr",
653 		.data = &r8a7745_cpg_mssr_info,
654 	},
655 #endif
656 #ifdef CONFIG_CLK_R8A77470
657 	{
658 		.compatible = "renesas,r8a77470-cpg-mssr",
659 		.data = &r8a77470_cpg_mssr_info,
660 	},
661 #endif
662 #ifdef CONFIG_CLK_R8A7790
663 	{
664 		.compatible = "renesas,r8a7790-cpg-mssr",
665 		.data = &r8a7790_cpg_mssr_info,
666 	},
667 #endif
668 #ifdef CONFIG_CLK_R8A7791
669 	{
670 		.compatible = "renesas,r8a7791-cpg-mssr",
671 		.data = &r8a7791_cpg_mssr_info,
672 	},
673 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
674 	{
675 		.compatible = "renesas,r8a7793-cpg-mssr",
676 		.data = &r8a7791_cpg_mssr_info,
677 	},
678 #endif
679 #ifdef CONFIG_CLK_R8A7792
680 	{
681 		.compatible = "renesas,r8a7792-cpg-mssr",
682 		.data = &r8a7792_cpg_mssr_info,
683 	},
684 #endif
685 #ifdef CONFIG_CLK_R8A7794
686 	{
687 		.compatible = "renesas,r8a7794-cpg-mssr",
688 		.data = &r8a7794_cpg_mssr_info,
689 	},
690 #endif
691 #ifdef CONFIG_CLK_R8A7795
692 	{
693 		.compatible = "renesas,r8a7795-cpg-mssr",
694 		.data = &r8a7795_cpg_mssr_info,
695 	},
696 #endif
697 #ifdef CONFIG_CLK_R8A7796
698 	{
699 		.compatible = "renesas,r8a7796-cpg-mssr",
700 		.data = &r8a7796_cpg_mssr_info,
701 	},
702 #endif
703 #ifdef CONFIG_CLK_R8A77965
704 	{
705 		.compatible = "renesas,r8a77965-cpg-mssr",
706 		.data = &r8a77965_cpg_mssr_info,
707 	},
708 #endif
709 #ifdef CONFIG_CLK_R8A77970
710 	{
711 		.compatible = "renesas,r8a77970-cpg-mssr",
712 		.data = &r8a77970_cpg_mssr_info,
713 	},
714 #endif
715 #ifdef CONFIG_CLK_R8A77980
716 	{
717 		.compatible = "renesas,r8a77980-cpg-mssr",
718 		.data = &r8a77980_cpg_mssr_info,
719 	},
720 #endif
721 #ifdef CONFIG_CLK_R8A77990
722 	{
723 		.compatible = "renesas,r8a77990-cpg-mssr",
724 		.data = &r8a77990_cpg_mssr_info,
725 	},
726 #endif
727 #ifdef CONFIG_CLK_R8A77995
728 	{
729 		.compatible = "renesas,r8a77995-cpg-mssr",
730 		.data = &r8a77995_cpg_mssr_info,
731 	},
732 #endif
733 	{ /* sentinel */ }
734 };
735 
cpg_mssr_del_clk_provider(void * data)736 static void cpg_mssr_del_clk_provider(void *data)
737 {
738 	of_clk_del_provider(data);
739 }
740 
741 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
cpg_mssr_suspend_noirq(struct device * dev)742 static int cpg_mssr_suspend_noirq(struct device *dev)
743 {
744 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
745 	unsigned int reg;
746 
747 	/* This is the best we can do to check for the presence of PSCI */
748 	if (!psci_ops.cpu_suspend)
749 		return 0;
750 
751 	/* Save module registers with bits under our control */
752 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
753 		if (priv->smstpcr_saved[reg].mask)
754 			priv->smstpcr_saved[reg].val =
755 				readl(priv->base + SMSTPCR(reg));
756 	}
757 
758 	/* Save core clocks */
759 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
760 
761 	return 0;
762 }
763 
cpg_mssr_resume_noirq(struct device * dev)764 static int cpg_mssr_resume_noirq(struct device *dev)
765 {
766 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
767 	unsigned int reg, i;
768 	u32 mask, oldval, newval;
769 
770 	/* This is the best we can do to check for the presence of PSCI */
771 	if (!psci_ops.cpu_suspend)
772 		return 0;
773 
774 	/* Restore core clocks */
775 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
776 
777 	/* Restore module clocks */
778 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
779 		mask = priv->smstpcr_saved[reg].mask;
780 		if (!mask)
781 			continue;
782 
783 		oldval = readl(priv->base + SMSTPCR(reg));
784 		newval = oldval & ~mask;
785 		newval |= priv->smstpcr_saved[reg].val & mask;
786 		if (newval == oldval)
787 			continue;
788 
789 		writel(newval, priv->base + SMSTPCR(reg));
790 
791 		/* Wait until enabled clocks are really enabled */
792 		mask &= ~priv->smstpcr_saved[reg].val;
793 		if (!mask)
794 			continue;
795 
796 		for (i = 1000; i > 0; --i) {
797 			oldval = readl(priv->base + MSTPSR(reg));
798 			if (!(oldval & mask))
799 				break;
800 			cpu_relax();
801 		}
802 
803 		if (!i)
804 			dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
805 				 priv->base + SMSTPCR(reg), oldval & mask);
806 	}
807 
808 	return 0;
809 }
810 
811 static const struct dev_pm_ops cpg_mssr_pm = {
812 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
813 				      cpg_mssr_resume_noirq)
814 };
815 #define DEV_PM_OPS	&cpg_mssr_pm
816 #else
817 #define DEV_PM_OPS	NULL
818 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
819 
cpg_mssr_probe(struct platform_device * pdev)820 static int __init cpg_mssr_probe(struct platform_device *pdev)
821 {
822 	struct device *dev = &pdev->dev;
823 	struct device_node *np = dev->of_node;
824 	const struct cpg_mssr_info *info;
825 	struct cpg_mssr_priv *priv;
826 	unsigned int nclks, i;
827 	struct resource *res;
828 	struct clk **clks;
829 	int error;
830 
831 	info = of_device_get_match_data(dev);
832 	if (info->init) {
833 		error = info->init(dev);
834 		if (error)
835 			return error;
836 	}
837 
838 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
839 	if (!priv)
840 		return -ENOMEM;
841 
842 	priv->dev = dev;
843 	spin_lock_init(&priv->rmw_lock);
844 
845 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846 	priv->base = devm_ioremap_resource(dev, res);
847 	if (IS_ERR(priv->base))
848 		return PTR_ERR(priv->base);
849 
850 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
851 	clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
852 	if (!clks)
853 		return -ENOMEM;
854 
855 	dev_set_drvdata(dev, priv);
856 	priv->clks = clks;
857 	priv->num_core_clks = info->num_total_core_clks;
858 	priv->num_mod_clks = info->num_hw_mod_clks;
859 	priv->last_dt_core_clk = info->last_dt_core_clk;
860 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
861 
862 	for (i = 0; i < nclks; i++)
863 		clks[i] = ERR_PTR(-ENOENT);
864 
865 	for (i = 0; i < info->num_core_clks; i++)
866 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
867 
868 	for (i = 0; i < info->num_mod_clks; i++)
869 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
870 
871 	error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
872 	if (error)
873 		return error;
874 
875 	error = devm_add_action_or_reset(dev,
876 					 cpg_mssr_del_clk_provider,
877 					 np);
878 	if (error)
879 		return error;
880 
881 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
882 					info->num_core_pm_clks);
883 	if (error)
884 		return error;
885 
886 	error = cpg_mssr_reset_controller_register(priv);
887 	if (error)
888 		return error;
889 
890 	return 0;
891 }
892 
893 static struct platform_driver cpg_mssr_driver = {
894 	.driver		= {
895 		.name	= "renesas-cpg-mssr",
896 		.of_match_table = cpg_mssr_match,
897 		.pm = DEV_PM_OPS,
898 	},
899 };
900 
cpg_mssr_init(void)901 static int __init cpg_mssr_init(void)
902 {
903 	return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
904 }
905 
906 subsys_initcall(cpg_mssr_init);
907 
cpg_core_nullify_range(struct cpg_core_clk * core_clks,unsigned int num_core_clks,unsigned int first_clk,unsigned int last_clk)908 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
909 				   unsigned int num_core_clks,
910 				   unsigned int first_clk,
911 				   unsigned int last_clk)
912 {
913 	unsigned int i;
914 
915 	for (i = 0; i < num_core_clks; i++)
916 		if (core_clks[i].id >= first_clk &&
917 		    core_clks[i].id <= last_clk)
918 			core_clks[i].name = NULL;
919 }
920 
mssr_mod_nullify(struct mssr_mod_clk * mod_clks,unsigned int num_mod_clks,const unsigned int * clks,unsigned int n)921 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
922 			     unsigned int num_mod_clks,
923 			     const unsigned int *clks, unsigned int n)
924 {
925 	unsigned int i, j;
926 
927 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
928 		if (mod_clks[i].id == clks[j]) {
929 			mod_clks[i].name = NULL;
930 			j++;
931 		}
932 }
933 
mssr_mod_reparent(struct mssr_mod_clk * mod_clks,unsigned int num_mod_clks,const struct mssr_mod_reparent * clks,unsigned int n)934 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
935 			      unsigned int num_mod_clks,
936 			      const struct mssr_mod_reparent *clks,
937 			      unsigned int n)
938 {
939 	unsigned int i, j;
940 
941 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
942 		if (mod_clks[i].id == clks[j].clk) {
943 			mod_clks[i].parent = clks[j].parent;
944 			j++;
945 		}
946 }
947 
948 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
949 MODULE_LICENSE("GPL v2");
950