1 /*
2 * EIM driver for Freescale's i.MX chips
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10 #include <linux/module.h>
11 #include <linux/clk.h>
12 #include <linux/io.h>
13 #include <linux/of_device.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
16 #include <linux/regmap.h>
17
18 struct imx_weim_devtype {
19 unsigned int cs_count;
20 unsigned int cs_regs_count;
21 unsigned int cs_stride;
22 };
23
24 static const struct imx_weim_devtype imx1_weim_devtype = {
25 .cs_count = 6,
26 .cs_regs_count = 2,
27 .cs_stride = 0x08,
28 };
29
30 static const struct imx_weim_devtype imx27_weim_devtype = {
31 .cs_count = 6,
32 .cs_regs_count = 3,
33 .cs_stride = 0x10,
34 };
35
36 static const struct imx_weim_devtype imx50_weim_devtype = {
37 .cs_count = 4,
38 .cs_regs_count = 6,
39 .cs_stride = 0x18,
40 };
41
42 static const struct imx_weim_devtype imx51_weim_devtype = {
43 .cs_count = 6,
44 .cs_regs_count = 6,
45 .cs_stride = 0x18,
46 };
47
48 #define MAX_CS_REGS_COUNT 6
49
50 static const struct of_device_id weim_id_table[] = {
51 /* i.MX1/21 */
52 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
53 /* i.MX25/27/31/35 */
54 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
55 /* i.MX50/53/6Q */
56 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
57 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
58 /* i.MX51 */
59 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
60 { }
61 };
62 MODULE_DEVICE_TABLE(of, weim_id_table);
63
imx_weim_gpr_setup(struct platform_device * pdev)64 static int __init imx_weim_gpr_setup(struct platform_device *pdev)
65 {
66 struct device_node *np = pdev->dev.of_node;
67 struct property *prop;
68 const __be32 *p;
69 struct regmap *gpr;
70 u32 gprvals[4] = {
71 05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */
72 033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */
73 0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */
74 01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */
75 };
76 u32 gprval = 0;
77 u32 val;
78 int cs = 0;
79 int i = 0;
80
81 gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
82 if (IS_ERR(gpr)) {
83 dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
84 return 0;
85 }
86
87 of_property_for_each_u32(np, "ranges", prop, p, val) {
88 if (i % 4 == 0) {
89 cs = val;
90 } else if (i % 4 == 3 && val) {
91 val = (val / SZ_32M) | 1;
92 gprval |= val << cs * 3;
93 }
94 i++;
95 }
96
97 if (i == 0 || i % 4)
98 goto err;
99
100 for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
101 if (gprval == gprvals[i]) {
102 /* Found it. Set up IOMUXC_GPR1[11:0] with it. */
103 regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
104 return 0;
105 }
106 }
107
108 err:
109 dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
110 return -EINVAL;
111 }
112
113 /* Parse and set the timing for this device. */
weim_timing_setup(struct device_node * np,void __iomem * base,const struct imx_weim_devtype * devtype)114 static int __init weim_timing_setup(struct device_node *np, void __iomem *base,
115 const struct imx_weim_devtype *devtype)
116 {
117 u32 cs_idx, value[MAX_CS_REGS_COUNT];
118 int i, ret;
119
120 if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
121 return -EINVAL;
122
123 /* get the CS index from this child node's "reg" property. */
124 ret = of_property_read_u32(np, "reg", &cs_idx);
125 if (ret)
126 return ret;
127
128 if (cs_idx >= devtype->cs_count)
129 return -EINVAL;
130
131 ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
132 value, devtype->cs_regs_count);
133 if (ret)
134 return ret;
135
136 /* set the timing for WEIM */
137 for (i = 0; i < devtype->cs_regs_count; i++)
138 writel(value[i], base + cs_idx * devtype->cs_stride + i * 4);
139
140 return 0;
141 }
142
weim_parse_dt(struct platform_device * pdev,void __iomem * base)143 static int __init weim_parse_dt(struct platform_device *pdev,
144 void __iomem *base)
145 {
146 const struct of_device_id *of_id = of_match_device(weim_id_table,
147 &pdev->dev);
148 const struct imx_weim_devtype *devtype = of_id->data;
149 struct device_node *child;
150 int ret, have_child = 0;
151
152 if (devtype == &imx50_weim_devtype) {
153 ret = imx_weim_gpr_setup(pdev);
154 if (ret)
155 return ret;
156 }
157
158 for_each_available_child_of_node(pdev->dev.of_node, child) {
159 if (!child->name)
160 continue;
161
162 ret = weim_timing_setup(child, base, devtype);
163 if (ret)
164 dev_warn(&pdev->dev, "%pOF set timing failed.\n",
165 child);
166 else
167 have_child = 1;
168 }
169
170 if (have_child)
171 ret = of_platform_default_populate(pdev->dev.of_node,
172 NULL, &pdev->dev);
173 if (ret)
174 dev_err(&pdev->dev, "%pOF fail to create devices.\n",
175 pdev->dev.of_node);
176 return ret;
177 }
178
weim_probe(struct platform_device * pdev)179 static int __init weim_probe(struct platform_device *pdev)
180 {
181 struct resource *res;
182 struct clk *clk;
183 void __iomem *base;
184 int ret;
185
186 /* get the resource */
187 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
188 base = devm_ioremap_resource(&pdev->dev, res);
189 if (IS_ERR(base))
190 return PTR_ERR(base);
191
192 /* get the clock */
193 clk = devm_clk_get(&pdev->dev, NULL);
194 if (IS_ERR(clk))
195 return PTR_ERR(clk);
196
197 ret = clk_prepare_enable(clk);
198 if (ret)
199 return ret;
200
201 /* parse the device node */
202 ret = weim_parse_dt(pdev, base);
203 if (ret)
204 clk_disable_unprepare(clk);
205 else
206 dev_info(&pdev->dev, "Driver registered.\n");
207
208 return ret;
209 }
210
211 static struct platform_driver weim_driver = {
212 .driver = {
213 .name = "imx-weim",
214 .of_match_table = weim_id_table,
215 },
216 };
217 module_platform_driver_probe(weim_driver, weim_probe);
218
219 MODULE_AUTHOR("Freescale Semiconductor Inc.");
220 MODULE_DESCRIPTION("i.MX EIM Controller Driver");
221 MODULE_LICENSE("GPL");
222
