1 /*
2 * intel_pmic_crc.c - Intel CrystalCove PMIC operation region driver
3 *
4 * Copyright (C) 2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/init.h>
17 #include <linux/acpi.h>
18 #include <linux/mfd/intel_soc_pmic.h>
19 #include <linux/regmap.h>
20 #include <linux/platform_device.h>
21 #include "intel_pmic.h"
22
23 #define PWR_SOURCE_SELECT BIT(1)
24
25 #define PMIC_A0LOCK_REG 0xc5
26
27 static struct pmic_table power_table[] = {
28 /* {
29 .address = 0x00,
30 .reg = ??,
31 .bit = ??,
32 }, ** VSYS */
33 {
34 .address = 0x04,
35 .reg = 0x63,
36 .bit = 0x00,
37 }, /* SYSX -> VSYS_SX */
38 {
39 .address = 0x08,
40 .reg = 0x62,
41 .bit = 0x00,
42 }, /* SYSU -> VSYS_U */
43 {
44 .address = 0x0c,
45 .reg = 0x64,
46 .bit = 0x00,
47 }, /* SYSS -> VSYS_S */
48 {
49 .address = 0x10,
50 .reg = 0x6a,
51 .bit = 0x00,
52 }, /* V50S -> V5P0S */
53 {
54 .address = 0x14,
55 .reg = 0x6b,
56 .bit = 0x00,
57 }, /* HOST -> VHOST, USB2/3 host */
58 {
59 .address = 0x18,
60 .reg = 0x6c,
61 .bit = 0x00,
62 }, /* VBUS -> VBUS, USB2/3 OTG */
63 {
64 .address = 0x1c,
65 .reg = 0x6d,
66 .bit = 0x00,
67 }, /* HDMI -> VHDMI */
68 /* {
69 .address = 0x20,
70 .reg = ??,
71 .bit = ??,
72 }, ** S285 */
73 {
74 .address = 0x24,
75 .reg = 0x66,
76 .bit = 0x00,
77 }, /* X285 -> V2P85SX, camera */
78 /* {
79 .address = 0x28,
80 .reg = ??,
81 .bit = ??,
82 }, ** V33A */
83 {
84 .address = 0x2c,
85 .reg = 0x69,
86 .bit = 0x00,
87 }, /* V33S -> V3P3S, display/ssd/audio */
88 {
89 .address = 0x30,
90 .reg = 0x68,
91 .bit = 0x00,
92 }, /* V33U -> V3P3U, SDIO wifi&bt */
93 /* {
94 .address = 0x34 .. 0x40,
95 .reg = ??,
96 .bit = ??,
97 }, ** V33I, V18A, REFQ, V12A */
98 {
99 .address = 0x44,
100 .reg = 0x5c,
101 .bit = 0x00,
102 }, /* V18S -> V1P8S, SOC/USB PHY/SIM */
103 {
104 .address = 0x48,
105 .reg = 0x5d,
106 .bit = 0x00,
107 }, /* V18X -> V1P8SX, eMMC/camara/audio */
108 {
109 .address = 0x4c,
110 .reg = 0x5b,
111 .bit = 0x00,
112 }, /* V18U -> V1P8U, LPDDR */
113 {
114 .address = 0x50,
115 .reg = 0x61,
116 .bit = 0x00,
117 }, /* V12X -> V1P2SX, SOC SFR */
118 {
119 .address = 0x54,
120 .reg = 0x60,
121 .bit = 0x00,
122 }, /* V12S -> V1P2S, MIPI */
123 /* {
124 .address = 0x58,
125 .reg = ??,
126 .bit = ??,
127 }, ** V10A */
128 {
129 .address = 0x5c,
130 .reg = 0x56,
131 .bit = 0x00,
132 }, /* V10S -> V1P0S, SOC GFX */
133 {
134 .address = 0x60,
135 .reg = 0x57,
136 .bit = 0x00,
137 }, /* V10X -> V1P0SX, SOC display/DDR IO/PCIe */
138 {
139 .address = 0x64,
140 .reg = 0x59,
141 .bit = 0x00,
142 }, /* V105 -> V1P05S, L2 SRAM */
143 };
144
145 static struct pmic_table thermal_table[] = {
146 {
147 .address = 0x00,
148 .reg = 0x75
149 },
150 {
151 .address = 0x04,
152 .reg = 0x95
153 },
154 {
155 .address = 0x08,
156 .reg = 0x97
157 },
158 {
159 .address = 0x0c,
160 .reg = 0x77
161 },
162 {
163 .address = 0x10,
164 .reg = 0x9a
165 },
166 {
167 .address = 0x14,
168 .reg = 0x9c
169 },
170 {
171 .address = 0x18,
172 .reg = 0x79
173 },
174 {
175 .address = 0x1c,
176 .reg = 0x9f
177 },
178 {
179 .address = 0x20,
180 .reg = 0xa1
181 },
182 {
183 .address = 0x48,
184 .reg = 0x94
185 },
186 {
187 .address = 0x4c,
188 .reg = 0x99
189 },
190 {
191 .address = 0x50,
192 .reg = 0x9e
193 },
194 };
195
intel_crc_pmic_get_power(struct regmap * regmap,int reg,int bit,u64 * value)196 static int intel_crc_pmic_get_power(struct regmap *regmap, int reg,
197 int bit, u64 *value)
198 {
199 int data;
200
201 if (regmap_read(regmap, reg, &data))
202 return -EIO;
203
204 *value = (data & PWR_SOURCE_SELECT) && (data & BIT(bit)) ? 1 : 0;
205 return 0;
206 }
207
intel_crc_pmic_update_power(struct regmap * regmap,int reg,int bit,bool on)208 static int intel_crc_pmic_update_power(struct regmap *regmap, int reg,
209 int bit, bool on)
210 {
211 int data;
212
213 if (regmap_read(regmap, reg, &data))
214 return -EIO;
215
216 if (on) {
217 data |= PWR_SOURCE_SELECT | BIT(bit);
218 } else {
219 data &= ~BIT(bit);
220 data |= PWR_SOURCE_SELECT;
221 }
222
223 if (regmap_write(regmap, reg, data))
224 return -EIO;
225 return 0;
226 }
227
intel_crc_pmic_get_raw_temp(struct regmap * regmap,int reg)228 static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg)
229 {
230 int temp_l, temp_h;
231
232 /*
233 * Raw temperature value is 10bits: 8bits in reg
234 * and 2bits in reg-1: bit0,1
235 */
236 if (regmap_read(regmap, reg, &temp_l) ||
237 regmap_read(regmap, reg - 1, &temp_h))
238 return -EIO;
239
240 return temp_l | (temp_h & 0x3) << 8;
241 }
242
intel_crc_pmic_update_aux(struct regmap * regmap,int reg,int raw)243 static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw)
244 {
245 return regmap_write(regmap, reg, raw) ||
246 regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0;
247 }
248
intel_crc_pmic_get_policy(struct regmap * regmap,int reg,int bit,u64 * value)249 static int intel_crc_pmic_get_policy(struct regmap *regmap,
250 int reg, int bit, u64 *value)
251 {
252 int pen;
253
254 if (regmap_read(regmap, reg, &pen))
255 return -EIO;
256 *value = pen >> 7;
257 return 0;
258 }
259
intel_crc_pmic_update_policy(struct regmap * regmap,int reg,int bit,int enable)260 static int intel_crc_pmic_update_policy(struct regmap *regmap,
261 int reg, int bit, int enable)
262 {
263 int alert0;
264
265 /* Update to policy enable bit requires unlocking a0lock */
266 if (regmap_read(regmap, PMIC_A0LOCK_REG, &alert0))
267 return -EIO;
268
269 if (regmap_update_bits(regmap, PMIC_A0LOCK_REG, 0x01, 0))
270 return -EIO;
271
272 if (regmap_update_bits(regmap, reg, 0x80, enable << 7))
273 return -EIO;
274
275 /* restore alert0 */
276 if (regmap_write(regmap, PMIC_A0LOCK_REG, alert0))
277 return -EIO;
278
279 return 0;
280 }
281
282 static struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = {
283 .get_power = intel_crc_pmic_get_power,
284 .update_power = intel_crc_pmic_update_power,
285 .get_raw_temp = intel_crc_pmic_get_raw_temp,
286 .update_aux = intel_crc_pmic_update_aux,
287 .get_policy = intel_crc_pmic_get_policy,
288 .update_policy = intel_crc_pmic_update_policy,
289 .power_table = power_table,
290 .power_table_count= ARRAY_SIZE(power_table),
291 .thermal_table = thermal_table,
292 .thermal_table_count = ARRAY_SIZE(thermal_table),
293 };
294
intel_crc_pmic_opregion_probe(struct platform_device * pdev)295 static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
296 {
297 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
298 return intel_pmic_install_opregion_handler(&pdev->dev,
299 ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
300 &intel_crc_pmic_opregion_data);
301 }
302
303 static struct platform_driver intel_crc_pmic_opregion_driver = {
304 .probe = intel_crc_pmic_opregion_probe,
305 .driver = {
306 .name = "crystal_cove_pmic",
307 },
308 };
309 builtin_platform_driver(intel_crc_pmic_opregion_driver);
310
