1 /*
2 * Resource Director Technology(RDT)
3 * - Cache Allocation code.
4 *
5 * Copyright (C) 2016 Intel Corporation
6 *
7 * Authors:
8 * Fenghua Yu <fenghua.yu@intel.com>
9 * Tony Luck <tony.luck@intel.com>
10 * Vikas Shivappa <vikas.shivappa@intel.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * More information about RDT be found in the Intel (R) x86 Architecture
22 * Software Developer Manual June 2016, volume 3, section 17.17.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/slab.h>
28 #include <linux/err.h>
29 #include <linux/cacheinfo.h>
30 #include <linux/cpuhotplug.h>
31
32 #include <asm/intel-family.h>
33 #include <asm/intel_rdt_sched.h>
34 #include "intel_rdt.h"
35
36 #define MBA_IS_LINEAR 0x4
37 #define MBA_MAX_MBPS U32_MAX
38
39 /* Mutex to protect rdtgroup access. */
40 DEFINE_MUTEX(rdtgroup_mutex);
41
42 /*
43 * The cached intel_pqr_state is strictly per CPU and can never be
44 * updated from a remote CPU. Functions which modify the state
45 * are called with interrupts disabled and no preemption, which
46 * is sufficient for the protection.
47 */
48 DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
49
50 /*
51 * Used to store the max resource name width and max resource data width
52 * to display the schemata in a tabular format
53 */
54 int max_name_width, max_data_width;
55
56 /*
57 * Global boolean for rdt_alloc which is true if any
58 * resource allocation is enabled.
59 */
60 bool rdt_alloc_capable;
61
62 static void
63 mba_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
64 static void
65 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
66
67 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
68
69 struct rdt_resource rdt_resources_all[] = {
70 [RDT_RESOURCE_L3] =
71 {
72 .rid = RDT_RESOURCE_L3,
73 .name = "L3",
74 .domains = domain_init(RDT_RESOURCE_L3),
75 .msr_base = IA32_L3_CBM_BASE,
76 .msr_update = cat_wrmsr,
77 .cache_level = 3,
78 .cache = {
79 .min_cbm_bits = 1,
80 .cbm_idx_mult = 1,
81 .cbm_idx_offset = 0,
82 },
83 .parse_ctrlval = parse_cbm,
84 .format_str = "%d=%0*x",
85 .fflags = RFTYPE_RES_CACHE,
86 },
87 [RDT_RESOURCE_L3DATA] =
88 {
89 .rid = RDT_RESOURCE_L3DATA,
90 .name = "L3DATA",
91 .domains = domain_init(RDT_RESOURCE_L3DATA),
92 .msr_base = IA32_L3_CBM_BASE,
93 .msr_update = cat_wrmsr,
94 .cache_level = 3,
95 .cache = {
96 .min_cbm_bits = 1,
97 .cbm_idx_mult = 2,
98 .cbm_idx_offset = 0,
99 },
100 .parse_ctrlval = parse_cbm,
101 .format_str = "%d=%0*x",
102 .fflags = RFTYPE_RES_CACHE,
103 },
104 [RDT_RESOURCE_L3CODE] =
105 {
106 .rid = RDT_RESOURCE_L3CODE,
107 .name = "L3CODE",
108 .domains = domain_init(RDT_RESOURCE_L3CODE),
109 .msr_base = IA32_L3_CBM_BASE,
110 .msr_update = cat_wrmsr,
111 .cache_level = 3,
112 .cache = {
113 .min_cbm_bits = 1,
114 .cbm_idx_mult = 2,
115 .cbm_idx_offset = 1,
116 },
117 .parse_ctrlval = parse_cbm,
118 .format_str = "%d=%0*x",
119 .fflags = RFTYPE_RES_CACHE,
120 },
121 [RDT_RESOURCE_L2] =
122 {
123 .rid = RDT_RESOURCE_L2,
124 .name = "L2",
125 .domains = domain_init(RDT_RESOURCE_L2),
126 .msr_base = IA32_L2_CBM_BASE,
127 .msr_update = cat_wrmsr,
128 .cache_level = 2,
129 .cache = {
130 .min_cbm_bits = 1,
131 .cbm_idx_mult = 1,
132 .cbm_idx_offset = 0,
133 },
134 .parse_ctrlval = parse_cbm,
135 .format_str = "%d=%0*x",
136 .fflags = RFTYPE_RES_CACHE,
137 },
138 [RDT_RESOURCE_L2DATA] =
139 {
140 .rid = RDT_RESOURCE_L2DATA,
141 .name = "L2DATA",
142 .domains = domain_init(RDT_RESOURCE_L2DATA),
143 .msr_base = IA32_L2_CBM_BASE,
144 .msr_update = cat_wrmsr,
145 .cache_level = 2,
146 .cache = {
147 .min_cbm_bits = 1,
148 .cbm_idx_mult = 2,
149 .cbm_idx_offset = 0,
150 },
151 .parse_ctrlval = parse_cbm,
152 .format_str = "%d=%0*x",
153 .fflags = RFTYPE_RES_CACHE,
154 },
155 [RDT_RESOURCE_L2CODE] =
156 {
157 .rid = RDT_RESOURCE_L2CODE,
158 .name = "L2CODE",
159 .domains = domain_init(RDT_RESOURCE_L2CODE),
160 .msr_base = IA32_L2_CBM_BASE,
161 .msr_update = cat_wrmsr,
162 .cache_level = 2,
163 .cache = {
164 .min_cbm_bits = 1,
165 .cbm_idx_mult = 2,
166 .cbm_idx_offset = 1,
167 },
168 .parse_ctrlval = parse_cbm,
169 .format_str = "%d=%0*x",
170 .fflags = RFTYPE_RES_CACHE,
171 },
172 [RDT_RESOURCE_MBA] =
173 {
174 .rid = RDT_RESOURCE_MBA,
175 .name = "MB",
176 .domains = domain_init(RDT_RESOURCE_MBA),
177 .msr_base = IA32_MBA_THRTL_BASE,
178 .msr_update = mba_wrmsr,
179 .cache_level = 3,
180 .parse_ctrlval = parse_bw,
181 .format_str = "%d=%*u",
182 .fflags = RFTYPE_RES_MB,
183 },
184 };
185
cbm_idx(struct rdt_resource * r,unsigned int closid)186 static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
187 {
188 return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
189 }
190
191 /*
192 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
193 * as they do not have CPUID enumeration support for Cache allocation.
194 * The check for Vendor/Family/Model is not enough to guarantee that
195 * the MSRs won't #GP fault because only the following SKUs support
196 * CAT:
197 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
198 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
199 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
200 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
201 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
202 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
203 *
204 * Probe by trying to write the first of the L3 cach mask registers
205 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
206 * is always 20 on hsw server parts. The minimum cache bitmask length
207 * allowed for HSW server is always 2 bits. Hardcode all of them.
208 */
cache_alloc_hsw_probe(void)209 static inline void cache_alloc_hsw_probe(void)
210 {
211 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
212 u32 l, h, max_cbm = BIT_MASK(20) - 1;
213
214 if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
215 return;
216 rdmsr(IA32_L3_CBM_BASE, l, h);
217
218 /* If all the bits were set in MSR, return success */
219 if (l != max_cbm)
220 return;
221
222 r->num_closid = 4;
223 r->default_ctrl = max_cbm;
224 r->cache.cbm_len = 20;
225 r->cache.shareable_bits = 0xc0000;
226 r->cache.min_cbm_bits = 2;
227 r->alloc_capable = true;
228 r->alloc_enabled = true;
229
230 rdt_alloc_capable = true;
231 }
232
is_mba_sc(struct rdt_resource * r)233 bool is_mba_sc(struct rdt_resource *r)
234 {
235 if (!r)
236 return rdt_resources_all[RDT_RESOURCE_MBA].membw.mba_sc;
237
238 return r->membw.mba_sc;
239 }
240
241 /*
242 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
243 * exposed to user interface and the h/w understandable delay values.
244 *
245 * The non-linear delay values have the granularity of power of two
246 * and also the h/w does not guarantee a curve for configured delay
247 * values vs. actual b/w enforced.
248 * Hence we need a mapping that is pre calibrated so the user can
249 * express the memory b/w as a percentage value.
250 */
rdt_get_mb_table(struct rdt_resource * r)251 static inline bool rdt_get_mb_table(struct rdt_resource *r)
252 {
253 /*
254 * There are no Intel SKUs as of now to support non-linear delay.
255 */
256 pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
257 boot_cpu_data.x86, boot_cpu_data.x86_model);
258
259 return false;
260 }
261
rdt_get_mem_config(struct rdt_resource * r)262 static bool rdt_get_mem_config(struct rdt_resource *r)
263 {
264 union cpuid_0x10_3_eax eax;
265 union cpuid_0x10_x_edx edx;
266 u32 ebx, ecx;
267
268 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
269 r->num_closid = edx.split.cos_max + 1;
270 r->membw.max_delay = eax.split.max_delay + 1;
271 r->default_ctrl = MAX_MBA_BW;
272 if (ecx & MBA_IS_LINEAR) {
273 r->membw.delay_linear = true;
274 r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay;
275 r->membw.bw_gran = MAX_MBA_BW - r->membw.max_delay;
276 } else {
277 if (!rdt_get_mb_table(r))
278 return false;
279 }
280 r->data_width = 3;
281
282 r->alloc_capable = true;
283 r->alloc_enabled = true;
284
285 return true;
286 }
287
rdt_get_cache_alloc_cfg(int idx,struct rdt_resource * r)288 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
289 {
290 union cpuid_0x10_1_eax eax;
291 union cpuid_0x10_x_edx edx;
292 u32 ebx, ecx;
293
294 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
295 r->num_closid = edx.split.cos_max + 1;
296 r->cache.cbm_len = eax.split.cbm_len + 1;
297 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
298 r->cache.shareable_bits = ebx & r->default_ctrl;
299 r->data_width = (r->cache.cbm_len + 3) / 4;
300 r->alloc_capable = true;
301 r->alloc_enabled = true;
302 }
303
rdt_get_cdp_config(int level,int type)304 static void rdt_get_cdp_config(int level, int type)
305 {
306 struct rdt_resource *r_l = &rdt_resources_all[level];
307 struct rdt_resource *r = &rdt_resources_all[type];
308
309 r->num_closid = r_l->num_closid / 2;
310 r->cache.cbm_len = r_l->cache.cbm_len;
311 r->default_ctrl = r_l->default_ctrl;
312 r->cache.shareable_bits = r_l->cache.shareable_bits;
313 r->data_width = (r->cache.cbm_len + 3) / 4;
314 r->alloc_capable = true;
315 /*
316 * By default, CDP is disabled. CDP can be enabled by mount parameter
317 * "cdp" during resctrl file system mount time.
318 */
319 r->alloc_enabled = false;
320 }
321
rdt_get_cdp_l3_config(void)322 static void rdt_get_cdp_l3_config(void)
323 {
324 rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA);
325 rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE);
326 }
327
rdt_get_cdp_l2_config(void)328 static void rdt_get_cdp_l2_config(void)
329 {
330 rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA);
331 rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);
332 }
333
get_cache_id(int cpu,int level)334 static int get_cache_id(int cpu, int level)
335 {
336 struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
337 int i;
338
339 for (i = 0; i < ci->num_leaves; i++) {
340 if (ci->info_list[i].level == level)
341 return ci->info_list[i].id;
342 }
343
344 return -1;
345 }
346
347 /*
348 * Map the memory b/w percentage value to delay values
349 * that can be written to QOS_MSRs.
350 * There are currently no SKUs which support non linear delay values.
351 */
delay_bw_map(unsigned long bw,struct rdt_resource * r)352 u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
353 {
354 if (r->membw.delay_linear)
355 return MAX_MBA_BW - bw;
356
357 pr_warn_once("Non Linear delay-bw map not supported but queried\n");
358 return r->default_ctrl;
359 }
360
361 static void
mba_wrmsr(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)362 mba_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
363 {
364 unsigned int i;
365
366 /* Write the delay values for mba. */
367 for (i = m->low; i < m->high; i++)
368 wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r));
369 }
370
371 static void
cat_wrmsr(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)372 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
373 {
374 unsigned int i;
375
376 for (i = m->low; i < m->high; i++)
377 wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]);
378 }
379
get_domain_from_cpu(int cpu,struct rdt_resource * r)380 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
381 {
382 struct rdt_domain *d;
383
384 list_for_each_entry(d, &r->domains, list) {
385 /* Find the domain that contains this CPU */
386 if (cpumask_test_cpu(cpu, &d->cpu_mask))
387 return d;
388 }
389
390 return NULL;
391 }
392
rdt_ctrl_update(void * arg)393 void rdt_ctrl_update(void *arg)
394 {
395 struct msr_param *m = arg;
396 struct rdt_resource *r = m->res;
397 int cpu = smp_processor_id();
398 struct rdt_domain *d;
399
400 d = get_domain_from_cpu(cpu, r);
401 if (d) {
402 r->msr_update(d, m, r);
403 return;
404 }
405 pr_warn_once("cpu %d not found in any domain for resource %s\n",
406 cpu, r->name);
407 }
408
409 /*
410 * rdt_find_domain - Find a domain in a resource that matches input resource id
411 *
412 * Search resource r's domain list to find the resource id. If the resource
413 * id is found in a domain, return the domain. Otherwise, if requested by
414 * caller, return the first domain whose id is bigger than the input id.
415 * The domain list is sorted by id in ascending order.
416 */
rdt_find_domain(struct rdt_resource * r,int id,struct list_head ** pos)417 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,
418 struct list_head **pos)
419 {
420 struct rdt_domain *d;
421 struct list_head *l;
422
423 if (id < 0)
424 return ERR_PTR(id);
425
426 list_for_each(l, &r->domains) {
427 d = list_entry(l, struct rdt_domain, list);
428 /* When id is found, return its domain. */
429 if (id == d->id)
430 return d;
431 /* Stop searching when finding id's position in sorted list. */
432 if (id < d->id)
433 break;
434 }
435
436 if (pos)
437 *pos = l;
438
439 return NULL;
440 }
441
setup_default_ctrlval(struct rdt_resource * r,u32 * dc,u32 * dm)442 void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm)
443 {
444 int i;
445
446 /*
447 * Initialize the Control MSRs to having no control.
448 * For Cache Allocation: Set all bits in cbm
449 * For Memory Allocation: Set b/w requested to 100%
450 * and the bandwidth in MBps to U32_MAX
451 */
452 for (i = 0; i < r->num_closid; i++, dc++, dm++) {
453 *dc = r->default_ctrl;
454 *dm = MBA_MAX_MBPS;
455 }
456 }
457
domain_setup_ctrlval(struct rdt_resource * r,struct rdt_domain * d)458 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
459 {
460 struct msr_param m;
461 u32 *dc, *dm;
462
463 dc = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL);
464 if (!dc)
465 return -ENOMEM;
466
467 dm = kmalloc_array(r->num_closid, sizeof(*d->mbps_val), GFP_KERNEL);
468 if (!dm) {
469 kfree(dc);
470 return -ENOMEM;
471 }
472
473 d->ctrl_val = dc;
474 d->mbps_val = dm;
475 setup_default_ctrlval(r, dc, dm);
476
477 m.low = 0;
478 m.high = r->num_closid;
479 r->msr_update(d, &m, r);
480 return 0;
481 }
482
domain_setup_mon_state(struct rdt_resource * r,struct rdt_domain * d)483 static int domain_setup_mon_state(struct rdt_resource *r, struct rdt_domain *d)
484 {
485 size_t tsize;
486
487 if (is_llc_occupancy_enabled()) {
488 d->rmid_busy_llc = kcalloc(BITS_TO_LONGS(r->num_rmid),
489 sizeof(unsigned long),
490 GFP_KERNEL);
491 if (!d->rmid_busy_llc)
492 return -ENOMEM;
493 INIT_DELAYED_WORK(&d->cqm_limbo, cqm_handle_limbo);
494 }
495 if (is_mbm_total_enabled()) {
496 tsize = sizeof(*d->mbm_total);
497 d->mbm_total = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
498 if (!d->mbm_total) {
499 kfree(d->rmid_busy_llc);
500 return -ENOMEM;
501 }
502 }
503 if (is_mbm_local_enabled()) {
504 tsize = sizeof(*d->mbm_local);
505 d->mbm_local = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
506 if (!d->mbm_local) {
507 kfree(d->rmid_busy_llc);
508 kfree(d->mbm_total);
509 return -ENOMEM;
510 }
511 }
512
513 if (is_mbm_enabled()) {
514 INIT_DELAYED_WORK(&d->mbm_over, mbm_handle_overflow);
515 mbm_setup_overflow_handler(d, MBM_OVERFLOW_INTERVAL);
516 }
517
518 return 0;
519 }
520
521 /*
522 * domain_add_cpu - Add a cpu to a resource's domain list.
523 *
524 * If an existing domain in the resource r's domain list matches the cpu's
525 * resource id, add the cpu in the domain.
526 *
527 * Otherwise, a new domain is allocated and inserted into the right position
528 * in the domain list sorted by id in ascending order.
529 *
530 * The order in the domain list is visible to users when we print entries
531 * in the schemata file and schemata input is validated to have the same order
532 * as this list.
533 */
domain_add_cpu(int cpu,struct rdt_resource * r)534 static void domain_add_cpu(int cpu, struct rdt_resource *r)
535 {
536 int id = get_cache_id(cpu, r->cache_level);
537 struct list_head *add_pos = NULL;
538 struct rdt_domain *d;
539
540 d = rdt_find_domain(r, id, &add_pos);
541 if (IS_ERR(d)) {
542 pr_warn("Could't find cache id for cpu %d\n", cpu);
543 return;
544 }
545
546 if (d) {
547 cpumask_set_cpu(cpu, &d->cpu_mask);
548 return;
549 }
550
551 d = kzalloc_node(sizeof(*d), GFP_KERNEL, cpu_to_node(cpu));
552 if (!d)
553 return;
554
555 d->id = id;
556 cpumask_set_cpu(cpu, &d->cpu_mask);
557
558 if (r->alloc_capable && domain_setup_ctrlval(r, d)) {
559 kfree(d);
560 return;
561 }
562
563 if (r->mon_capable && domain_setup_mon_state(r, d)) {
564 kfree(d);
565 return;
566 }
567
568 list_add_tail(&d->list, add_pos);
569
570 /*
571 * If resctrl is mounted, add
572 * per domain monitor data directories.
573 */
574 if (static_branch_unlikely(&rdt_mon_enable_key))
575 mkdir_mondata_subdir_allrdtgrp(r, d);
576 }
577
domain_remove_cpu(int cpu,struct rdt_resource * r)578 static void domain_remove_cpu(int cpu, struct rdt_resource *r)
579 {
580 int id = get_cache_id(cpu, r->cache_level);
581 struct rdt_domain *d;
582
583 d = rdt_find_domain(r, id, NULL);
584 if (IS_ERR_OR_NULL(d)) {
585 pr_warn("Could't find cache id for cpu %d\n", cpu);
586 return;
587 }
588
589 cpumask_clear_cpu(cpu, &d->cpu_mask);
590 if (cpumask_empty(&d->cpu_mask)) {
591 /*
592 * If resctrl is mounted, remove all the
593 * per domain monitor data directories.
594 */
595 if (static_branch_unlikely(&rdt_mon_enable_key))
596 rmdir_mondata_subdir_allrdtgrp(r, d->id);
597 list_del(&d->list);
598 if (is_mbm_enabled())
599 cancel_delayed_work(&d->mbm_over);
600 if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) {
601 /*
602 * When a package is going down, forcefully
603 * decrement rmid->ebusy. There is no way to know
604 * that the L3 was flushed and hence may lead to
605 * incorrect counts in rare scenarios, but leaving
606 * the RMID as busy creates RMID leaks if the
607 * package never comes back.
608 */
609 __check_limbo(d, true);
610 cancel_delayed_work(&d->cqm_limbo);
611 }
612
613 kfree(d->ctrl_val);
614 kfree(d->mbps_val);
615 kfree(d->rmid_busy_llc);
616 kfree(d->mbm_total);
617 kfree(d->mbm_local);
618 kfree(d);
619 return;
620 }
621
622 if (r == &rdt_resources_all[RDT_RESOURCE_L3]) {
623 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) {
624 cancel_delayed_work(&d->mbm_over);
625 mbm_setup_overflow_handler(d, 0);
626 }
627 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu &&
628 has_busy_rmid(r, d)) {
629 cancel_delayed_work(&d->cqm_limbo);
630 cqm_setup_limbo_handler(d, 0);
631 }
632 }
633 }
634
clear_closid_rmid(int cpu)635 static void clear_closid_rmid(int cpu)
636 {
637 struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
638
639 state->default_closid = 0;
640 state->default_rmid = 0;
641 state->cur_closid = 0;
642 state->cur_rmid = 0;
643 wrmsr(IA32_PQR_ASSOC, 0, 0);
644 }
645
intel_rdt_online_cpu(unsigned int cpu)646 static int intel_rdt_online_cpu(unsigned int cpu)
647 {
648 struct rdt_resource *r;
649
650 mutex_lock(&rdtgroup_mutex);
651 for_each_capable_rdt_resource(r)
652 domain_add_cpu(cpu, r);
653 /* The cpu is set in default rdtgroup after online. */
654 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask);
655 clear_closid_rmid(cpu);
656 mutex_unlock(&rdtgroup_mutex);
657
658 return 0;
659 }
660
clear_childcpus(struct rdtgroup * r,unsigned int cpu)661 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu)
662 {
663 struct rdtgroup *cr;
664
665 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) {
666 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) {
667 break;
668 }
669 }
670 }
671
intel_rdt_offline_cpu(unsigned int cpu)672 static int intel_rdt_offline_cpu(unsigned int cpu)
673 {
674 struct rdtgroup *rdtgrp;
675 struct rdt_resource *r;
676
677 mutex_lock(&rdtgroup_mutex);
678 for_each_capable_rdt_resource(r)
679 domain_remove_cpu(cpu, r);
680 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) {
681 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) {
682 clear_childcpus(rdtgrp, cpu);
683 break;
684 }
685 }
686 clear_closid_rmid(cpu);
687 mutex_unlock(&rdtgroup_mutex);
688
689 return 0;
690 }
691
692 /*
693 * Choose a width for the resource name and resource data based on the
694 * resource that has widest name and cbm.
695 */
rdt_init_padding(void)696 static __init void rdt_init_padding(void)
697 {
698 struct rdt_resource *r;
699 int cl;
700
701 for_each_alloc_capable_rdt_resource(r) {
702 cl = strlen(r->name);
703 if (cl > max_name_width)
704 max_name_width = cl;
705
706 if (r->data_width > max_data_width)
707 max_data_width = r->data_width;
708 }
709 }
710
711 enum {
712 RDT_FLAG_CMT,
713 RDT_FLAG_MBM_TOTAL,
714 RDT_FLAG_MBM_LOCAL,
715 RDT_FLAG_L3_CAT,
716 RDT_FLAG_L3_CDP,
717 RDT_FLAG_L2_CAT,
718 RDT_FLAG_L2_CDP,
719 RDT_FLAG_MBA,
720 };
721
722 #define RDT_OPT(idx, n, f) \
723 [idx] = { \
724 .name = n, \
725 .flag = f \
726 }
727
728 struct rdt_options {
729 char *name;
730 int flag;
731 bool force_off, force_on;
732 };
733
734 static struct rdt_options rdt_options[] __initdata = {
735 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC),
736 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
737 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
738 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3),
739 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3),
740 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2),
741 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2),
742 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
743 };
744 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
745
set_rdt_options(char * str)746 static int __init set_rdt_options(char *str)
747 {
748 struct rdt_options *o;
749 bool force_off;
750 char *tok;
751
752 if (*str == '=')
753 str++;
754 while ((tok = strsep(&str, ",")) != NULL) {
755 force_off = *tok == '!';
756 if (force_off)
757 tok++;
758 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
759 if (strcmp(tok, o->name) == 0) {
760 if (force_off)
761 o->force_off = true;
762 else
763 o->force_on = true;
764 break;
765 }
766 }
767 }
768 return 1;
769 }
770 __setup("rdt", set_rdt_options);
771
rdt_cpu_has(int flag)772 static bool __init rdt_cpu_has(int flag)
773 {
774 bool ret = boot_cpu_has(flag);
775 struct rdt_options *o;
776
777 if (!ret)
778 return ret;
779
780 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
781 if (flag == o->flag) {
782 if (o->force_off)
783 ret = false;
784 if (o->force_on)
785 ret = true;
786 break;
787 }
788 }
789 return ret;
790 }
791
get_rdt_alloc_resources(void)792 static __init bool get_rdt_alloc_resources(void)
793 {
794 bool ret = false;
795
796 if (rdt_alloc_capable)
797 return true;
798
799 if (!boot_cpu_has(X86_FEATURE_RDT_A))
800 return false;
801
802 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
803 rdt_get_cache_alloc_cfg(1, &rdt_resources_all[RDT_RESOURCE_L3]);
804 if (rdt_cpu_has(X86_FEATURE_CDP_L3))
805 rdt_get_cdp_l3_config();
806 ret = true;
807 }
808 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
809 /* CPUID 0x10.2 fields are same format at 0x10.1 */
810 rdt_get_cache_alloc_cfg(2, &rdt_resources_all[RDT_RESOURCE_L2]);
811 if (rdt_cpu_has(X86_FEATURE_CDP_L2))
812 rdt_get_cdp_l2_config();
813 ret = true;
814 }
815
816 if (rdt_cpu_has(X86_FEATURE_MBA)) {
817 if (rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]))
818 ret = true;
819 }
820 return ret;
821 }
822
get_rdt_mon_resources(void)823 static __init bool get_rdt_mon_resources(void)
824 {
825 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
826 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID);
827 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL))
828 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID);
829 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))
830 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID);
831
832 if (!rdt_mon_features)
833 return false;
834
835 return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]);
836 }
837
rdt_quirks(void)838 static __init void rdt_quirks(void)
839 {
840 switch (boot_cpu_data.x86_model) {
841 case INTEL_FAM6_HASWELL_X:
842 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
843 cache_alloc_hsw_probe();
844 break;
845 case INTEL_FAM6_SKYLAKE_X:
846 if (boot_cpu_data.x86_stepping <= 4)
847 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
848 else
849 set_rdt_options("!l3cat");
850 }
851 }
852
get_rdt_resources(void)853 static __init bool get_rdt_resources(void)
854 {
855 rdt_quirks();
856 rdt_alloc_capable = get_rdt_alloc_resources();
857 rdt_mon_capable = get_rdt_mon_resources();
858
859 return (rdt_mon_capable || rdt_alloc_capable);
860 }
861
862 static enum cpuhp_state rdt_online;
863
intel_rdt_late_init(void)864 static int __init intel_rdt_late_init(void)
865 {
866 struct rdt_resource *r;
867 int state, ret;
868
869 if (!get_rdt_resources())
870 return -ENODEV;
871
872 rdt_init_padding();
873
874 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
875 "x86/rdt/cat:online:",
876 intel_rdt_online_cpu, intel_rdt_offline_cpu);
877 if (state < 0)
878 return state;
879
880 ret = rdtgroup_init();
881 if (ret) {
882 cpuhp_remove_state(state);
883 return ret;
884 }
885 rdt_online = state;
886
887 for_each_alloc_capable_rdt_resource(r)
888 pr_info("Intel RDT %s allocation detected\n", r->name);
889
890 for_each_mon_capable_rdt_resource(r)
891 pr_info("Intel RDT %s monitoring detected\n", r->name);
892
893 return 0;
894 }
895
896 late_initcall(intel_rdt_late_init);
897
intel_rdt_exit(void)898 static void __exit intel_rdt_exit(void)
899 {
900 cpuhp_remove_state(rdt_online);
901 rdtgroup_exit();
902 }
903
904 __exitcall(intel_rdt_exit);
905
