1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 btl $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 btl $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 .pushsection .entry_trampoline, "ax" 146 147/* 148 * The code in here gets remapped into cpu_entry_area's trampoline. This means 149 * that the assembler and linker have the wrong idea as to where this code 150 * lives (and, in fact, it's mapped more than once, so it's not even at a 151 * fixed address). So we can't reference any symbols outside the entry 152 * trampoline and expect it to work. 153 * 154 * Instead, we carefully abuse %rip-relative addressing. 155 * _entry_trampoline(%rip) refers to the start of the remapped) entry 156 * trampoline. We can thus find cpu_entry_area with this macro: 157 */ 158 159#define CPU_ENTRY_AREA \ 160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) 161 162/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ 163#define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ 164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA 165 166ENTRY(entry_SYSCALL_64_trampoline) 167 UNWIND_HINT_EMPTY 168 swapgs 169 170 /* Stash the user RSP. */ 171 movq %rsp, RSP_SCRATCH 172 173 /* Note: using %rsp as a scratch reg. */ 174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 175 176 /* Load the top of the task stack into RSP */ 177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp 178 179 /* Start building the simulated IRET frame. */ 180 pushq $__USER_DS /* pt_regs->ss */ 181 pushq RSP_SCRATCH /* pt_regs->sp */ 182 pushq %r11 /* pt_regs->flags */ 183 pushq $__USER_CS /* pt_regs->cs */ 184 pushq %rcx /* pt_regs->ip */ 185 186 /* 187 * x86 lacks a near absolute jump, and we can't jump to the real 188 * entry text with a relative jump. We could push the target 189 * address and then use retq, but this destroys the pipeline on 190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, 191 * spill RDI and restore it in a second-stage trampoline. 192 */ 193 pushq %rdi 194 movq $entry_SYSCALL_64_stage2, %rdi 195 JMP_NOSPEC %rdi 196END(entry_SYSCALL_64_trampoline) 197 198 .popsection 199 200ENTRY(entry_SYSCALL_64_stage2) 201 UNWIND_HINT_EMPTY 202 popq %rdi 203 jmp entry_SYSCALL_64_after_hwframe 204END(entry_SYSCALL_64_stage2) 205 206ENTRY(entry_SYSCALL_64) 207 UNWIND_HINT_EMPTY 208 /* 209 * Interrupts are off on entry. 210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 211 * it is too small to ever cause noticeable irq latency. 212 */ 213 214 swapgs 215 /* 216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it 217 * is not required to switch CR3. 218 */ 219 movq %rsp, PER_CPU_VAR(rsp_scratch) 220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 221 222 /* Construct struct pt_regs on stack */ 223 pushq $__USER_DS /* pt_regs->ss */ 224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 225 pushq %r11 /* pt_regs->flags */ 226 pushq $__USER_CS /* pt_regs->cs */ 227 pushq %rcx /* pt_regs->ip */ 228GLOBAL(entry_SYSCALL_64_after_hwframe) 229 pushq %rax /* pt_regs->orig_ax */ 230 231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 232 233 TRACE_IRQS_OFF 234 235 /* IRQs are off. */ 236 movq %rax, %rdi 237 movq %rsp, %rsi 238 call do_syscall_64 /* returns with IRQs disabled */ 239 240 TRACE_IRQS_IRETQ /* we're about to change IF */ 241 242 /* 243 * Try to use SYSRET instead of IRET if we're returning to 244 * a completely clean 64-bit userspace context. If we're not, 245 * go to the slow exit path. 246 */ 247 movq RCX(%rsp), %rcx 248 movq RIP(%rsp), %r11 249 250 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 251 jne swapgs_restore_regs_and_return_to_usermode 252 253 /* 254 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 255 * in kernel space. This essentially lets the user take over 256 * the kernel, since userspace controls RSP. 257 * 258 * If width of "canonical tail" ever becomes variable, this will need 259 * to be updated to remain correct on both old and new CPUs. 260 * 261 * Change top bits to match most significant bit (47th or 56th bit 262 * depending on paging mode) in the address. 263 */ 264#ifdef CONFIG_X86_5LEVEL 265 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 266 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 267#else 268 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 269 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 270#endif 271 272 /* If this changed %rcx, it was not canonical */ 273 cmpq %rcx, %r11 274 jne swapgs_restore_regs_and_return_to_usermode 275 276 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 277 jne swapgs_restore_regs_and_return_to_usermode 278 279 movq R11(%rsp), %r11 280 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 281 jne swapgs_restore_regs_and_return_to_usermode 282 283 /* 284 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 285 * restore RF properly. If the slowpath sets it for whatever reason, we 286 * need to restore it correctly. 287 * 288 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 289 * trap from userspace immediately after SYSRET. This would cause an 290 * infinite loop whenever #DB happens with register state that satisfies 291 * the opportunistic SYSRET conditions. For example, single-stepping 292 * this user code: 293 * 294 * movq $stuck_here, %rcx 295 * pushfq 296 * popq %r11 297 * stuck_here: 298 * 299 * would never get past 'stuck_here'. 300 */ 301 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 302 jnz swapgs_restore_regs_and_return_to_usermode 303 304 /* nothing to check for RSP */ 305 306 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 307 jne swapgs_restore_regs_and_return_to_usermode 308 309 /* 310 * We win! This label is here just for ease of understanding 311 * perf profiles. Nothing jumps here. 312 */ 313syscall_return_via_sysret: 314 /* rcx and r11 are already restored (see code above) */ 315 UNWIND_HINT_EMPTY 316 POP_REGS pop_rdi=0 skip_r11rcx=1 317 318 /* 319 * Now all regs are restored except RSP and RDI. 320 * Save old stack pointer and switch to trampoline stack. 321 */ 322 movq %rsp, %rdi 323 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 324 325 pushq RSP-RDI(%rdi) /* RSP */ 326 pushq (%rdi) /* RDI */ 327 328 /* 329 * We are on the trampoline stack. All regs except RDI are live. 330 * We can do future final exit work right here. 331 */ 332 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 333 334 popq %rdi 335 popq %rsp 336 USERGS_SYSRET64 337END(entry_SYSCALL_64) 338 339/* 340 * %rdi: prev task 341 * %rsi: next task 342 */ 343ENTRY(__switch_to_asm) 344 UNWIND_HINT_FUNC 345 /* 346 * Save callee-saved registers 347 * This must match the order in inactive_task_frame 348 */ 349 pushq %rbp 350 pushq %rbx 351 pushq %r12 352 pushq %r13 353 pushq %r14 354 pushq %r15 355 356 /* switch stack */ 357 movq %rsp, TASK_threadsp(%rdi) 358 movq TASK_threadsp(%rsi), %rsp 359 360#ifdef CONFIG_STACKPROTECTOR 361 movq TASK_stack_canary(%rsi), %rbx 362 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 363#endif 364 365#ifdef CONFIG_RETPOLINE 366 /* 367 * When switching from a shallower to a deeper call stack 368 * the RSB may either underflow or use entries populated 369 * with userspace addresses. On CPUs where those concerns 370 * exist, overwrite the RSB with entries which capture 371 * speculative execution to prevent attack. 372 */ 373 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 374#endif 375 376 /* restore callee-saved registers */ 377 popq %r15 378 popq %r14 379 popq %r13 380 popq %r12 381 popq %rbx 382 popq %rbp 383 384 jmp __switch_to 385END(__switch_to_asm) 386 387/* 388 * A newly forked process directly context switches into this address. 389 * 390 * rax: prev task we switched from 391 * rbx: kernel thread func (NULL for user thread) 392 * r12: kernel thread arg 393 */ 394ENTRY(ret_from_fork) 395 UNWIND_HINT_EMPTY 396 movq %rax, %rdi 397 call schedule_tail /* rdi: 'prev' task parameter */ 398 399 testq %rbx, %rbx /* from kernel_thread? */ 400 jnz 1f /* kernel threads are uncommon */ 401 4022: 403 UNWIND_HINT_REGS 404 movq %rsp, %rdi 405 call syscall_return_slowpath /* returns with IRQs disabled */ 406 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 407 jmp swapgs_restore_regs_and_return_to_usermode 408 4091: 410 /* kernel thread */ 411 UNWIND_HINT_EMPTY 412 movq %r12, %rdi 413 CALL_NOSPEC %rbx 414 /* 415 * A kernel thread is allowed to return here after successfully 416 * calling do_execve(). Exit to userspace to complete the execve() 417 * syscall. 418 */ 419 movq $0, RAX(%rsp) 420 jmp 2b 421END(ret_from_fork) 422 423/* 424 * Build the entry stubs with some assembler magic. 425 * We pack 1 stub into every 8-byte block. 426 */ 427 .align 8 428ENTRY(irq_entries_start) 429 vector=FIRST_EXTERNAL_VECTOR 430 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 431 UNWIND_HINT_IRET_REGS 432 pushq $(~vector+0x80) /* Note: always in signed byte range */ 433 jmp common_interrupt 434 .align 8 435 vector=vector+1 436 .endr 437END(irq_entries_start) 438 439.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 440#ifdef CONFIG_DEBUG_ENTRY 441 pushq %rax 442 SAVE_FLAGS(CLBR_RAX) 443 testl $X86_EFLAGS_IF, %eax 444 jz .Lokay_\@ 445 ud2 446.Lokay_\@: 447 popq %rax 448#endif 449.endm 450 451/* 452 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 453 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 454 * Requires kernel GSBASE. 455 * 456 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 457 */ 458.macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 459 DEBUG_ENTRY_ASSERT_IRQS_OFF 460 461 .if \save_ret 462 /* 463 * If save_ret is set, the original stack contains one additional 464 * entry -- the return address. Therefore, move the address one 465 * entry below %rsp to \old_rsp. 466 */ 467 leaq 8(%rsp), \old_rsp 468 .else 469 movq %rsp, \old_rsp 470 .endif 471 472 .if \regs 473 UNWIND_HINT_REGS base=\old_rsp 474 .endif 475 476 incl PER_CPU_VAR(irq_count) 477 jnz .Lirq_stack_push_old_rsp_\@ 478 479 /* 480 * Right now, if we just incremented irq_count to zero, we've 481 * claimed the IRQ stack but we haven't switched to it yet. 482 * 483 * If anything is added that can interrupt us here without using IST, 484 * it must be *extremely* careful to limit its stack usage. This 485 * could include kprobes and a hypothetical future IST-less #DB 486 * handler. 487 * 488 * The OOPS unwinder relies on the word at the top of the IRQ 489 * stack linking back to the previous RSP for the entire time we're 490 * on the IRQ stack. For this to work reliably, we need to write 491 * it before we actually move ourselves to the IRQ stack. 492 */ 493 494 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 495 movq PER_CPU_VAR(irq_stack_ptr), %rsp 496 497#ifdef CONFIG_DEBUG_ENTRY 498 /* 499 * If the first movq above becomes wrong due to IRQ stack layout 500 * changes, the only way we'll notice is if we try to unwind right 501 * here. Assert that we set up the stack right to catch this type 502 * of bug quickly. 503 */ 504 cmpq -8(%rsp), \old_rsp 505 je .Lirq_stack_okay\@ 506 ud2 507 .Lirq_stack_okay\@: 508#endif 509 510.Lirq_stack_push_old_rsp_\@: 511 pushq \old_rsp 512 513 .if \regs 514 UNWIND_HINT_REGS indirect=1 515 .endif 516 517 .if \save_ret 518 /* 519 * Push the return address to the stack. This return address can 520 * be found at the "real" original RSP, which was offset by 8 at 521 * the beginning of this macro. 522 */ 523 pushq -8(\old_rsp) 524 .endif 525.endm 526 527/* 528 * Undoes ENTER_IRQ_STACK. 529 */ 530.macro LEAVE_IRQ_STACK regs=1 531 DEBUG_ENTRY_ASSERT_IRQS_OFF 532 /* We need to be off the IRQ stack before decrementing irq_count. */ 533 popq %rsp 534 535 .if \regs 536 UNWIND_HINT_REGS 537 .endif 538 539 /* 540 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 541 * the irq stack but we're not on it. 542 */ 543 544 decl PER_CPU_VAR(irq_count) 545.endm 546 547/* 548 * Interrupt entry helper function. 549 * 550 * Entry runs with interrupts off. Stack layout at entry: 551 * +----------------------------------------------------+ 552 * | regs->ss | 553 * | regs->rsp | 554 * | regs->eflags | 555 * | regs->cs | 556 * | regs->ip | 557 * +----------------------------------------------------+ 558 * | regs->orig_ax = ~(interrupt number) | 559 * +----------------------------------------------------+ 560 * | return address | 561 * +----------------------------------------------------+ 562 */ 563ENTRY(interrupt_entry) 564 UNWIND_HINT_FUNC 565 ASM_CLAC 566 cld 567 568 testb $3, CS-ORIG_RAX+8(%rsp) 569 jz 1f 570 SWAPGS 571 572 /* 573 * Switch to the thread stack. The IRET frame and orig_ax are 574 * on the stack, as well as the return address. RDI..R12 are 575 * not (yet) on the stack and space has not (yet) been 576 * allocated for them. 577 */ 578 pushq %rdi 579 580 /* Need to switch before accessing the thread stack. */ 581 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 582 movq %rsp, %rdi 583 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 584 585 /* 586 * We have RDI, return address, and orig_ax on the stack on 587 * top of the IRET frame. That means offset=24 588 */ 589 UNWIND_HINT_IRET_REGS base=%rdi offset=24 590 591 pushq 7*8(%rdi) /* regs->ss */ 592 pushq 6*8(%rdi) /* regs->rsp */ 593 pushq 5*8(%rdi) /* regs->eflags */ 594 pushq 4*8(%rdi) /* regs->cs */ 595 pushq 3*8(%rdi) /* regs->ip */ 596 pushq 2*8(%rdi) /* regs->orig_ax */ 597 pushq 8(%rdi) /* return address */ 598 UNWIND_HINT_FUNC 599 600 movq (%rdi), %rdi 6011: 602 603 PUSH_AND_CLEAR_REGS save_ret=1 604 ENCODE_FRAME_POINTER 8 605 606 testb $3, CS+8(%rsp) 607 jz 1f 608 609 /* 610 * IRQ from user mode. 611 * 612 * We need to tell lockdep that IRQs are off. We can't do this until 613 * we fix gsbase, and we should do it before enter_from_user_mode 614 * (which can take locks). Since TRACE_IRQS_OFF is idempotent, 615 * the simplest way to handle it is to just call it twice if 616 * we enter from user mode. There's no reason to optimize this since 617 * TRACE_IRQS_OFF is a no-op if lockdep is off. 618 */ 619 TRACE_IRQS_OFF 620 621 CALL_enter_from_user_mode 622 6231: 624 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 625 /* We entered an interrupt context - irqs are off: */ 626 TRACE_IRQS_OFF 627 628 ret 629END(interrupt_entry) 630 631 632/* Interrupt entry/exit. */ 633 634 /* 635 * The interrupt stubs push (~vector+0x80) onto the stack and 636 * then jump to common_interrupt. 637 */ 638 .p2align CONFIG_X86_L1_CACHE_SHIFT 639common_interrupt: 640 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 641 call interrupt_entry 642 UNWIND_HINT_REGS indirect=1 643 call do_IRQ /* rdi points to pt_regs */ 644 /* 0(%rsp): old RSP */ 645ret_from_intr: 646 DISABLE_INTERRUPTS(CLBR_ANY) 647 TRACE_IRQS_OFF 648 649 LEAVE_IRQ_STACK 650 651 testb $3, CS(%rsp) 652 jz retint_kernel 653 654 /* Interrupt came from user space */ 655GLOBAL(retint_user) 656 mov %rsp,%rdi 657 call prepare_exit_to_usermode 658 TRACE_IRQS_IRETQ 659 660GLOBAL(swapgs_restore_regs_and_return_to_usermode) 661#ifdef CONFIG_DEBUG_ENTRY 662 /* Assert that pt_regs indicates user mode. */ 663 testb $3, CS(%rsp) 664 jnz 1f 665 ud2 6661: 667#endif 668 POP_REGS pop_rdi=0 669 670 /* 671 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 672 * Save old stack pointer and switch to trampoline stack. 673 */ 674 movq %rsp, %rdi 675 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 676 677 /* Copy the IRET frame to the trampoline stack. */ 678 pushq 6*8(%rdi) /* SS */ 679 pushq 5*8(%rdi) /* RSP */ 680 pushq 4*8(%rdi) /* EFLAGS */ 681 pushq 3*8(%rdi) /* CS */ 682 pushq 2*8(%rdi) /* RIP */ 683 684 /* Push user RDI on the trampoline stack. */ 685 pushq (%rdi) 686 687 /* 688 * We are on the trampoline stack. All regs except RDI are live. 689 * We can do future final exit work right here. 690 */ 691 692 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 693 694 /* Restore RDI. */ 695 popq %rdi 696 SWAPGS 697 INTERRUPT_RETURN 698 699 700/* Returning to kernel space */ 701retint_kernel: 702#ifdef CONFIG_PREEMPT 703 /* Interrupts are off */ 704 /* Check if we need preemption */ 705 btl $9, EFLAGS(%rsp) /* were interrupts off? */ 706 jnc 1f 7070: cmpl $0, PER_CPU_VAR(__preempt_count) 708 jnz 1f 709 call preempt_schedule_irq 710 jmp 0b 7111: 712#endif 713 /* 714 * The iretq could re-enable interrupts: 715 */ 716 TRACE_IRQS_IRETQ 717 718GLOBAL(restore_regs_and_return_to_kernel) 719#ifdef CONFIG_DEBUG_ENTRY 720 /* Assert that pt_regs indicates kernel mode. */ 721 testb $3, CS(%rsp) 722 jz 1f 723 ud2 7241: 725#endif 726 POP_REGS 727 addq $8, %rsp /* skip regs->orig_ax */ 728 /* 729 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 730 * when returning from IPI handler. 731 */ 732 INTERRUPT_RETURN 733 734ENTRY(native_iret) 735 UNWIND_HINT_IRET_REGS 736 /* 737 * Are we returning to a stack segment from the LDT? Note: in 738 * 64-bit mode SS:RSP on the exception stack is always valid. 739 */ 740#ifdef CONFIG_X86_ESPFIX64 741 testb $4, (SS-RIP)(%rsp) 742 jnz native_irq_return_ldt 743#endif 744 745.global native_irq_return_iret 746native_irq_return_iret: 747 /* 748 * This may fault. Non-paranoid faults on return to userspace are 749 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 750 * Double-faults due to espfix64 are handled in do_double_fault. 751 * Other faults here are fatal. 752 */ 753 iretq 754 755#ifdef CONFIG_X86_ESPFIX64 756native_irq_return_ldt: 757 /* 758 * We are running with user GSBASE. All GPRs contain their user 759 * values. We have a percpu ESPFIX stack that is eight slots 760 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 761 * of the ESPFIX stack. 762 * 763 * We clobber RAX and RDI in this code. We stash RDI on the 764 * normal stack and RAX on the ESPFIX stack. 765 * 766 * The ESPFIX stack layout we set up looks like this: 767 * 768 * --- top of ESPFIX stack --- 769 * SS 770 * RSP 771 * RFLAGS 772 * CS 773 * RIP <-- RSP points here when we're done 774 * RAX <-- espfix_waddr points here 775 * --- bottom of ESPFIX stack --- 776 */ 777 778 pushq %rdi /* Stash user RDI */ 779 SWAPGS /* to kernel GS */ 780 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 781 782 movq PER_CPU_VAR(espfix_waddr), %rdi 783 movq %rax, (0*8)(%rdi) /* user RAX */ 784 movq (1*8)(%rsp), %rax /* user RIP */ 785 movq %rax, (1*8)(%rdi) 786 movq (2*8)(%rsp), %rax /* user CS */ 787 movq %rax, (2*8)(%rdi) 788 movq (3*8)(%rsp), %rax /* user RFLAGS */ 789 movq %rax, (3*8)(%rdi) 790 movq (5*8)(%rsp), %rax /* user SS */ 791 movq %rax, (5*8)(%rdi) 792 movq (4*8)(%rsp), %rax /* user RSP */ 793 movq %rax, (4*8)(%rdi) 794 /* Now RAX == RSP. */ 795 796 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 797 798 /* 799 * espfix_stack[31:16] == 0. The page tables are set up such that 800 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 801 * espfix_waddr for any X. That is, there are 65536 RO aliases of 802 * the same page. Set up RSP so that RSP[31:16] contains the 803 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 804 * still points to an RO alias of the ESPFIX stack. 805 */ 806 orq PER_CPU_VAR(espfix_stack), %rax 807 808 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 809 SWAPGS /* to user GS */ 810 popq %rdi /* Restore user RDI */ 811 812 movq %rax, %rsp 813 UNWIND_HINT_IRET_REGS offset=8 814 815 /* 816 * At this point, we cannot write to the stack any more, but we can 817 * still read. 818 */ 819 popq %rax /* Restore user RAX */ 820 821 /* 822 * RSP now points to an ordinary IRET frame, except that the page 823 * is read-only and RSP[31:16] are preloaded with the userspace 824 * values. We can now IRET back to userspace. 825 */ 826 jmp native_irq_return_iret 827#endif 828END(common_interrupt) 829 830/* 831 * APIC interrupts. 832 */ 833.macro apicinterrupt3 num sym do_sym 834ENTRY(\sym) 835 UNWIND_HINT_IRET_REGS 836 pushq $~(\num) 837.Lcommon_\sym: 838 call interrupt_entry 839 UNWIND_HINT_REGS indirect=1 840 call \do_sym /* rdi points to pt_regs */ 841 jmp ret_from_intr 842END(\sym) 843.endm 844 845/* Make sure APIC interrupt handlers end up in the irqentry section: */ 846#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 847#define POP_SECTION_IRQENTRY .popsection 848 849.macro apicinterrupt num sym do_sym 850PUSH_SECTION_IRQENTRY 851apicinterrupt3 \num \sym \do_sym 852POP_SECTION_IRQENTRY 853.endm 854 855#ifdef CONFIG_SMP 856apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 857apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 858#endif 859 860#ifdef CONFIG_X86_UV 861apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 862#endif 863 864apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 865apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 866 867#ifdef CONFIG_HAVE_KVM 868apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 869apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 870apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 871#endif 872 873#ifdef CONFIG_X86_MCE_THRESHOLD 874apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 875#endif 876 877#ifdef CONFIG_X86_MCE_AMD 878apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 879#endif 880 881#ifdef CONFIG_X86_THERMAL_VECTOR 882apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 883#endif 884 885#ifdef CONFIG_SMP 886apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 887apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 888apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 889#endif 890 891apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 892apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 893 894#ifdef CONFIG_IRQ_WORK 895apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 896#endif 897 898/* 899 * Exception entry points. 900 */ 901#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 902 903.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 904ENTRY(\sym) 905 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 906 907 /* Sanity check */ 908 .if \shift_ist != -1 && \paranoid == 0 909 .error "using shift_ist requires paranoid=1" 910 .endif 911 912 ASM_CLAC 913 914 .if \has_error_code == 0 915 pushq $-1 /* ORIG_RAX: no syscall to restart */ 916 .endif 917 918 .if \paranoid == 1 919 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ 920 jnz .Lfrom_usermode_switch_stack_\@ 921 .endif 922 923 .if \paranoid 924 call paranoid_entry 925 .else 926 call error_entry 927 .endif 928 UNWIND_HINT_REGS 929 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 930 931 .if \paranoid 932 .if \shift_ist != -1 933 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 934 .else 935 TRACE_IRQS_OFF 936 .endif 937 .endif 938 939 movq %rsp, %rdi /* pt_regs pointer */ 940 941 .if \has_error_code 942 movq ORIG_RAX(%rsp), %rsi /* get error code */ 943 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 944 .else 945 xorl %esi, %esi /* no error code */ 946 .endif 947 948 .if \shift_ist != -1 949 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 950 .endif 951 952 call \do_sym 953 954 .if \shift_ist != -1 955 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 956 .endif 957 958 /* these procedures expect "no swapgs" flag in ebx */ 959 .if \paranoid 960 jmp paranoid_exit 961 .else 962 jmp error_exit 963 .endif 964 965 .if \paranoid == 1 966 /* 967 * Entry from userspace. Switch stacks and treat it 968 * as a normal entry. This means that paranoid handlers 969 * run in real process context if user_mode(regs). 970 */ 971.Lfrom_usermode_switch_stack_\@: 972 call error_entry 973 974 movq %rsp, %rdi /* pt_regs pointer */ 975 976 .if \has_error_code 977 movq ORIG_RAX(%rsp), %rsi /* get error code */ 978 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 979 .else 980 xorl %esi, %esi /* no error code */ 981 .endif 982 983 call \do_sym 984 985 jmp error_exit 986 .endif 987END(\sym) 988.endm 989 990idtentry divide_error do_divide_error has_error_code=0 991idtentry overflow do_overflow has_error_code=0 992idtentry bounds do_bounds has_error_code=0 993idtentry invalid_op do_invalid_op has_error_code=0 994idtentry device_not_available do_device_not_available has_error_code=0 995idtentry double_fault do_double_fault has_error_code=1 paranoid=2 996idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 997idtentry invalid_TSS do_invalid_TSS has_error_code=1 998idtentry segment_not_present do_segment_not_present has_error_code=1 999idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 1000idtentry coprocessor_error do_coprocessor_error has_error_code=0 1001idtentry alignment_check do_alignment_check has_error_code=1 1002idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 1003 1004 1005 /* 1006 * Reload gs selector with exception handling 1007 * edi: new selector 1008 */ 1009ENTRY(native_load_gs_index) 1010 FRAME_BEGIN 1011 pushfq 1012 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1013 TRACE_IRQS_OFF 1014 SWAPGS 1015.Lgs_change: 1016 movl %edi, %gs 10172: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1018 SWAPGS 1019 TRACE_IRQS_FLAGS (%rsp) 1020 popfq 1021 FRAME_END 1022 ret 1023ENDPROC(native_load_gs_index) 1024EXPORT_SYMBOL(native_load_gs_index) 1025 1026 _ASM_EXTABLE(.Lgs_change, bad_gs) 1027 .section .fixup, "ax" 1028 /* running with kernelgs */ 1029bad_gs: 1030 SWAPGS /* switch back to user gs */ 1031.macro ZAP_GS 1032 /* This can't be a string because the preprocessor needs to see it. */ 1033 movl $__USER_DS, %eax 1034 movl %eax, %gs 1035.endm 1036 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1037 xorl %eax, %eax 1038 movl %eax, %gs 1039 jmp 2b 1040 .previous 1041 1042/* Call softirq on interrupt stack. Interrupts are off. */ 1043ENTRY(do_softirq_own_stack) 1044 pushq %rbp 1045 mov %rsp, %rbp 1046 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1047 call __do_softirq 1048 LEAVE_IRQ_STACK regs=0 1049 leaveq 1050 ret 1051ENDPROC(do_softirq_own_stack) 1052 1053#ifdef CONFIG_XEN 1054idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1055 1056/* 1057 * A note on the "critical region" in our callback handler. 1058 * We want to avoid stacking callback handlers due to events occurring 1059 * during handling of the last event. To do this, we keep events disabled 1060 * until we've done all processing. HOWEVER, we must enable events before 1061 * popping the stack frame (can't be done atomically) and so it would still 1062 * be possible to get enough handler activations to overflow the stack. 1063 * Although unlikely, bugs of that kind are hard to track down, so we'd 1064 * like to avoid the possibility. 1065 * So, on entry to the handler we detect whether we interrupted an 1066 * existing activation in its critical region -- if so, we pop the current 1067 * activation and restart the handler using the previous one. 1068 */ 1069ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1070 1071/* 1072 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1073 * see the correct pointer to the pt_regs 1074 */ 1075 UNWIND_HINT_FUNC 1076 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1077 UNWIND_HINT_REGS 1078 1079 ENTER_IRQ_STACK old_rsp=%r10 1080 call xen_evtchn_do_upcall 1081 LEAVE_IRQ_STACK 1082 1083#ifndef CONFIG_PREEMPT 1084 call xen_maybe_preempt_hcall 1085#endif 1086 jmp error_exit 1087END(xen_do_hypervisor_callback) 1088 1089/* 1090 * Hypervisor uses this for application faults while it executes. 1091 * We get here for two reasons: 1092 * 1. Fault while reloading DS, ES, FS or GS 1093 * 2. Fault while executing IRET 1094 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1095 * registers that could be reloaded and zeroed the others. 1096 * Category 2 we fix up by killing the current process. We cannot use the 1097 * normal Linux return path in this case because if we use the IRET hypercall 1098 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1099 * We distinguish between categories by comparing each saved segment register 1100 * with its current contents: any discrepancy means we in category 1. 1101 */ 1102ENTRY(xen_failsafe_callback) 1103 UNWIND_HINT_EMPTY 1104 movl %ds, %ecx 1105 cmpw %cx, 0x10(%rsp) 1106 jne 1f 1107 movl %es, %ecx 1108 cmpw %cx, 0x18(%rsp) 1109 jne 1f 1110 movl %fs, %ecx 1111 cmpw %cx, 0x20(%rsp) 1112 jne 1f 1113 movl %gs, %ecx 1114 cmpw %cx, 0x28(%rsp) 1115 jne 1f 1116 /* All segments match their saved values => Category 2 (Bad IRET). */ 1117 movq (%rsp), %rcx 1118 movq 8(%rsp), %r11 1119 addq $0x30, %rsp 1120 pushq $0 /* RIP */ 1121 UNWIND_HINT_IRET_REGS offset=8 1122 jmp general_protection 11231: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1124 movq (%rsp), %rcx 1125 movq 8(%rsp), %r11 1126 addq $0x30, %rsp 1127 UNWIND_HINT_IRET_REGS 1128 pushq $-1 /* orig_ax = -1 => not a system call */ 1129 PUSH_AND_CLEAR_REGS 1130 ENCODE_FRAME_POINTER 1131 jmp error_exit 1132END(xen_failsafe_callback) 1133 1134apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1135 xen_hvm_callback_vector xen_evtchn_do_upcall 1136 1137#endif /* CONFIG_XEN */ 1138 1139#if IS_ENABLED(CONFIG_HYPERV) 1140apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1141 hyperv_callback_vector hyperv_vector_handler 1142 1143apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1144 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1145 1146apicinterrupt3 HYPERV_STIMER0_VECTOR \ 1147 hv_stimer0_callback_vector hv_stimer0_vector_handler 1148#endif /* CONFIG_HYPERV */ 1149 1150idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1151idtentry int3 do_int3 has_error_code=0 1152idtentry stack_segment do_stack_segment has_error_code=1 1153 1154#ifdef CONFIG_XEN 1155idtentry xennmi do_nmi has_error_code=0 1156idtentry xendebug do_debug has_error_code=0 1157idtentry xenint3 do_int3 has_error_code=0 1158#endif 1159 1160idtentry general_protection do_general_protection has_error_code=1 1161idtentry page_fault do_page_fault has_error_code=1 1162 1163#ifdef CONFIG_KVM_GUEST 1164idtentry async_page_fault do_async_page_fault has_error_code=1 1165#endif 1166 1167#ifdef CONFIG_X86_MCE 1168idtentry machine_check do_mce has_error_code=0 paranoid=1 1169#endif 1170 1171/* 1172 * Save all registers in pt_regs, and switch gs if needed. 1173 * Use slow, but surefire "are we in kernel?" check. 1174 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1175 */ 1176ENTRY(paranoid_entry) 1177 UNWIND_HINT_FUNC 1178 cld 1179 PUSH_AND_CLEAR_REGS save_ret=1 1180 ENCODE_FRAME_POINTER 8 1181 movl $1, %ebx 1182 movl $MSR_GS_BASE, %ecx 1183 rdmsr 1184 testl %edx, %edx 1185 js 1f /* negative -> in kernel */ 1186 SWAPGS 1187 xorl %ebx, %ebx 1188 11891: 1190 /* 1191 * Always stash CR3 in %r14. This value will be restored, 1192 * verbatim, at exit. Needed if paranoid_entry interrupted 1193 * another entry that already switched to the user CR3 value 1194 * but has not yet returned to userspace. 1195 * 1196 * This is also why CS (stashed in the "iret frame" by the 1197 * hardware at entry) can not be used: this may be a return 1198 * to kernel code, but with a user CR3 value. 1199 */ 1200 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1201 1202 ret 1203END(paranoid_entry) 1204 1205/* 1206 * "Paranoid" exit path from exception stack. This is invoked 1207 * only on return from non-NMI IST interrupts that came 1208 * from kernel space. 1209 * 1210 * We may be returning to very strange contexts (e.g. very early 1211 * in syscall entry), so checking for preemption here would 1212 * be complicated. Fortunately, we there's no good reason 1213 * to try to handle preemption here. 1214 * 1215 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1216 */ 1217ENTRY(paranoid_exit) 1218 UNWIND_HINT_REGS 1219 DISABLE_INTERRUPTS(CLBR_ANY) 1220 TRACE_IRQS_OFF_DEBUG 1221 testl %ebx, %ebx /* swapgs needed? */ 1222 jnz .Lparanoid_exit_no_swapgs 1223 TRACE_IRQS_IRETQ 1224 /* Always restore stashed CR3 value (see paranoid_entry) */ 1225 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1226 SWAPGS_UNSAFE_STACK 1227 jmp .Lparanoid_exit_restore 1228.Lparanoid_exit_no_swapgs: 1229 TRACE_IRQS_IRETQ_DEBUG 1230 /* Always restore stashed CR3 value (see paranoid_entry) */ 1231 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1232.Lparanoid_exit_restore: 1233 jmp restore_regs_and_return_to_kernel 1234END(paranoid_exit) 1235 1236/* 1237 * Save all registers in pt_regs, and switch GS if needed. 1238 */ 1239ENTRY(error_entry) 1240 UNWIND_HINT_FUNC 1241 cld 1242 PUSH_AND_CLEAR_REGS save_ret=1 1243 ENCODE_FRAME_POINTER 8 1244 testb $3, CS+8(%rsp) 1245 jz .Lerror_kernelspace 1246 1247 /* 1248 * We entered from user mode or we're pretending to have entered 1249 * from user mode due to an IRET fault. 1250 */ 1251 SWAPGS 1252 /* We have user CR3. Change to kernel CR3. */ 1253 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1254 1255.Lerror_entry_from_usermode_after_swapgs: 1256 /* Put us onto the real thread stack. */ 1257 popq %r12 /* save return addr in %12 */ 1258 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1259 call sync_regs 1260 movq %rax, %rsp /* switch stack */ 1261 ENCODE_FRAME_POINTER 1262 pushq %r12 1263 1264 /* 1265 * We need to tell lockdep that IRQs are off. We can't do this until 1266 * we fix gsbase, and we should do it before enter_from_user_mode 1267 * (which can take locks). 1268 */ 1269 TRACE_IRQS_OFF 1270 CALL_enter_from_user_mode 1271 ret 1272 1273.Lerror_entry_done: 1274 TRACE_IRQS_OFF 1275 ret 1276 1277 /* 1278 * There are two places in the kernel that can potentially fault with 1279 * usergs. Handle them here. B stepping K8s sometimes report a 1280 * truncated RIP for IRET exceptions returning to compat mode. Check 1281 * for these here too. 1282 */ 1283.Lerror_kernelspace: 1284 leaq native_irq_return_iret(%rip), %rcx 1285 cmpq %rcx, RIP+8(%rsp) 1286 je .Lerror_bad_iret 1287 movl %ecx, %eax /* zero extend */ 1288 cmpq %rax, RIP+8(%rsp) 1289 je .Lbstep_iret 1290 cmpq $.Lgs_change, RIP+8(%rsp) 1291 jne .Lerror_entry_done 1292 1293 /* 1294 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1295 * gsbase and proceed. We'll fix up the exception and land in 1296 * .Lgs_change's error handler with kernel gsbase. 1297 */ 1298 SWAPGS 1299 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1300 jmp .Lerror_entry_done 1301 1302.Lbstep_iret: 1303 /* Fix truncated RIP */ 1304 movq %rcx, RIP+8(%rsp) 1305 /* fall through */ 1306 1307.Lerror_bad_iret: 1308 /* 1309 * We came from an IRET to user mode, so we have user 1310 * gsbase and CR3. Switch to kernel gsbase and CR3: 1311 */ 1312 SWAPGS 1313 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1314 1315 /* 1316 * Pretend that the exception came from user mode: set up pt_regs 1317 * as if we faulted immediately after IRET. 1318 */ 1319 mov %rsp, %rdi 1320 call fixup_bad_iret 1321 mov %rax, %rsp 1322 jmp .Lerror_entry_from_usermode_after_swapgs 1323END(error_entry) 1324 1325ENTRY(error_exit) 1326 UNWIND_HINT_REGS 1327 DISABLE_INTERRUPTS(CLBR_ANY) 1328 TRACE_IRQS_OFF 1329 testb $3, CS(%rsp) 1330 jz retint_kernel 1331 jmp retint_user 1332END(error_exit) 1333 1334/* 1335 * Runs on exception stack. Xen PV does not go through this path at all, 1336 * so we can use real assembly here. 1337 * 1338 * Registers: 1339 * %r14: Used to save/restore the CR3 of the interrupted context 1340 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1341 */ 1342ENTRY(nmi) 1343 UNWIND_HINT_IRET_REGS 1344 1345 /* 1346 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1347 * the iretq it performs will take us out of NMI context. 1348 * This means that we can have nested NMIs where the next 1349 * NMI is using the top of the stack of the previous NMI. We 1350 * can't let it execute because the nested NMI will corrupt the 1351 * stack of the previous NMI. NMI handlers are not re-entrant 1352 * anyway. 1353 * 1354 * To handle this case we do the following: 1355 * Check the a special location on the stack that contains 1356 * a variable that is set when NMIs are executing. 1357 * The interrupted task's stack is also checked to see if it 1358 * is an NMI stack. 1359 * If the variable is not set and the stack is not the NMI 1360 * stack then: 1361 * o Set the special variable on the stack 1362 * o Copy the interrupt frame into an "outermost" location on the 1363 * stack 1364 * o Copy the interrupt frame into an "iret" location on the stack 1365 * o Continue processing the NMI 1366 * If the variable is set or the previous stack is the NMI stack: 1367 * o Modify the "iret" location to jump to the repeat_nmi 1368 * o return back to the first NMI 1369 * 1370 * Now on exit of the first NMI, we first clear the stack variable 1371 * The NMI stack will tell any nested NMIs at that point that it is 1372 * nested. Then we pop the stack normally with iret, and if there was 1373 * a nested NMI that updated the copy interrupt stack frame, a 1374 * jump will be made to the repeat_nmi code that will handle the second 1375 * NMI. 1376 * 1377 * However, espfix prevents us from directly returning to userspace 1378 * with a single IRET instruction. Similarly, IRET to user mode 1379 * can fault. We therefore handle NMIs from user space like 1380 * other IST entries. 1381 */ 1382 1383 ASM_CLAC 1384 1385 /* Use %rdx as our temp variable throughout */ 1386 pushq %rdx 1387 1388 testb $3, CS-RIP+8(%rsp) 1389 jz .Lnmi_from_kernel 1390 1391 /* 1392 * NMI from user mode. We need to run on the thread stack, but we 1393 * can't go through the normal entry paths: NMIs are masked, and 1394 * we don't want to enable interrupts, because then we'll end 1395 * up in an awkward situation in which IRQs are on but NMIs 1396 * are off. 1397 * 1398 * We also must not push anything to the stack before switching 1399 * stacks lest we corrupt the "NMI executing" variable. 1400 */ 1401 1402 swapgs 1403 cld 1404 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1405 movq %rsp, %rdx 1406 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1407 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1408 pushq 5*8(%rdx) /* pt_regs->ss */ 1409 pushq 4*8(%rdx) /* pt_regs->rsp */ 1410 pushq 3*8(%rdx) /* pt_regs->flags */ 1411 pushq 2*8(%rdx) /* pt_regs->cs */ 1412 pushq 1*8(%rdx) /* pt_regs->rip */ 1413 UNWIND_HINT_IRET_REGS 1414 pushq $-1 /* pt_regs->orig_ax */ 1415 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1416 ENCODE_FRAME_POINTER 1417 1418 /* 1419 * At this point we no longer need to worry about stack damage 1420 * due to nesting -- we're on the normal thread stack and we're 1421 * done with the NMI stack. 1422 */ 1423 1424 movq %rsp, %rdi 1425 movq $-1, %rsi 1426 call do_nmi 1427 1428 /* 1429 * Return back to user mode. We must *not* do the normal exit 1430 * work, because we don't want to enable interrupts. 1431 */ 1432 jmp swapgs_restore_regs_and_return_to_usermode 1433 1434.Lnmi_from_kernel: 1435 /* 1436 * Here's what our stack frame will look like: 1437 * +---------------------------------------------------------+ 1438 * | original SS | 1439 * | original Return RSP | 1440 * | original RFLAGS | 1441 * | original CS | 1442 * | original RIP | 1443 * +---------------------------------------------------------+ 1444 * | temp storage for rdx | 1445 * +---------------------------------------------------------+ 1446 * | "NMI executing" variable | 1447 * +---------------------------------------------------------+ 1448 * | iret SS } Copied from "outermost" frame | 1449 * | iret Return RSP } on each loop iteration; overwritten | 1450 * | iret RFLAGS } by a nested NMI to force another | 1451 * | iret CS } iteration if needed. | 1452 * | iret RIP } | 1453 * +---------------------------------------------------------+ 1454 * | outermost SS } initialized in first_nmi; | 1455 * | outermost Return RSP } will not be changed before | 1456 * | outermost RFLAGS } NMI processing is done. | 1457 * | outermost CS } Copied to "iret" frame on each | 1458 * | outermost RIP } iteration. | 1459 * +---------------------------------------------------------+ 1460 * | pt_regs | 1461 * +---------------------------------------------------------+ 1462 * 1463 * The "original" frame is used by hardware. Before re-enabling 1464 * NMIs, we need to be done with it, and we need to leave enough 1465 * space for the asm code here. 1466 * 1467 * We return by executing IRET while RSP points to the "iret" frame. 1468 * That will either return for real or it will loop back into NMI 1469 * processing. 1470 * 1471 * The "outermost" frame is copied to the "iret" frame on each 1472 * iteration of the loop, so each iteration starts with the "iret" 1473 * frame pointing to the final return target. 1474 */ 1475 1476 /* 1477 * Determine whether we're a nested NMI. 1478 * 1479 * If we interrupted kernel code between repeat_nmi and 1480 * end_repeat_nmi, then we are a nested NMI. We must not 1481 * modify the "iret" frame because it's being written by 1482 * the outer NMI. That's okay; the outer NMI handler is 1483 * about to about to call do_nmi anyway, so we can just 1484 * resume the outer NMI. 1485 */ 1486 1487 movq $repeat_nmi, %rdx 1488 cmpq 8(%rsp), %rdx 1489 ja 1f 1490 movq $end_repeat_nmi, %rdx 1491 cmpq 8(%rsp), %rdx 1492 ja nested_nmi_out 14931: 1494 1495 /* 1496 * Now check "NMI executing". If it's set, then we're nested. 1497 * This will not detect if we interrupted an outer NMI just 1498 * before IRET. 1499 */ 1500 cmpl $1, -8(%rsp) 1501 je nested_nmi 1502 1503 /* 1504 * Now test if the previous stack was an NMI stack. This covers 1505 * the case where we interrupt an outer NMI after it clears 1506 * "NMI executing" but before IRET. We need to be careful, though: 1507 * there is one case in which RSP could point to the NMI stack 1508 * despite there being no NMI active: naughty userspace controls 1509 * RSP at the very beginning of the SYSCALL targets. We can 1510 * pull a fast one on naughty userspace, though: we program 1511 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1512 * if it controls the kernel's RSP. We set DF before we clear 1513 * "NMI executing". 1514 */ 1515 lea 6*8(%rsp), %rdx 1516 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1517 cmpq %rdx, 4*8(%rsp) 1518 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1519 ja first_nmi 1520 1521 subq $EXCEPTION_STKSZ, %rdx 1522 cmpq %rdx, 4*8(%rsp) 1523 /* If it is below the NMI stack, it is a normal NMI */ 1524 jb first_nmi 1525 1526 /* Ah, it is within the NMI stack. */ 1527 1528 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1529 jz first_nmi /* RSP was user controlled. */ 1530 1531 /* This is a nested NMI. */ 1532 1533nested_nmi: 1534 /* 1535 * Modify the "iret" frame to point to repeat_nmi, forcing another 1536 * iteration of NMI handling. 1537 */ 1538 subq $8, %rsp 1539 leaq -10*8(%rsp), %rdx 1540 pushq $__KERNEL_DS 1541 pushq %rdx 1542 pushfq 1543 pushq $__KERNEL_CS 1544 pushq $repeat_nmi 1545 1546 /* Put stack back */ 1547 addq $(6*8), %rsp 1548 1549nested_nmi_out: 1550 popq %rdx 1551 1552 /* We are returning to kernel mode, so this cannot result in a fault. */ 1553 iretq 1554 1555first_nmi: 1556 /* Restore rdx. */ 1557 movq (%rsp), %rdx 1558 1559 /* Make room for "NMI executing". */ 1560 pushq $0 1561 1562 /* Leave room for the "iret" frame */ 1563 subq $(5*8), %rsp 1564 1565 /* Copy the "original" frame to the "outermost" frame */ 1566 .rept 5 1567 pushq 11*8(%rsp) 1568 .endr 1569 UNWIND_HINT_IRET_REGS 1570 1571 /* Everything up to here is safe from nested NMIs */ 1572 1573#ifdef CONFIG_DEBUG_ENTRY 1574 /* 1575 * For ease of testing, unmask NMIs right away. Disabled by 1576 * default because IRET is very expensive. 1577 */ 1578 pushq $0 /* SS */ 1579 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1580 addq $8, (%rsp) /* Fix up RSP */ 1581 pushfq /* RFLAGS */ 1582 pushq $__KERNEL_CS /* CS */ 1583 pushq $1f /* RIP */ 1584 iretq /* continues at repeat_nmi below */ 1585 UNWIND_HINT_IRET_REGS 15861: 1587#endif 1588 1589repeat_nmi: 1590 /* 1591 * If there was a nested NMI, the first NMI's iret will return 1592 * here. But NMIs are still enabled and we can take another 1593 * nested NMI. The nested NMI checks the interrupted RIP to see 1594 * if it is between repeat_nmi and end_repeat_nmi, and if so 1595 * it will just return, as we are about to repeat an NMI anyway. 1596 * This makes it safe to copy to the stack frame that a nested 1597 * NMI will update. 1598 * 1599 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1600 * we're repeating an NMI, gsbase has the same value that it had on 1601 * the first iteration. paranoid_entry will load the kernel 1602 * gsbase if needed before we call do_nmi. "NMI executing" 1603 * is zero. 1604 */ 1605 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1606 1607 /* 1608 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1609 * here must not modify the "iret" frame while we're writing to 1610 * it or it will end up containing garbage. 1611 */ 1612 addq $(10*8), %rsp 1613 .rept 5 1614 pushq -6*8(%rsp) 1615 .endr 1616 subq $(5*8), %rsp 1617end_repeat_nmi: 1618 1619 /* 1620 * Everything below this point can be preempted by a nested NMI. 1621 * If this happens, then the inner NMI will change the "iret" 1622 * frame to point back to repeat_nmi. 1623 */ 1624 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1625 1626 /* 1627 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1628 * as we should not be calling schedule in NMI context. 1629 * Even with normal interrupts enabled. An NMI should not be 1630 * setting NEED_RESCHED or anything that normal interrupts and 1631 * exceptions might do. 1632 */ 1633 call paranoid_entry 1634 UNWIND_HINT_REGS 1635 1636 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1637 movq %rsp, %rdi 1638 movq $-1, %rsi 1639 call do_nmi 1640 1641 /* Always restore stashed CR3 value (see paranoid_entry) */ 1642 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1643 1644 testl %ebx, %ebx /* swapgs needed? */ 1645 jnz nmi_restore 1646nmi_swapgs: 1647 SWAPGS_UNSAFE_STACK 1648nmi_restore: 1649 POP_REGS 1650 1651 /* 1652 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1653 * at the "iret" frame. 1654 */ 1655 addq $6*8, %rsp 1656 1657 /* 1658 * Clear "NMI executing". Set DF first so that we can easily 1659 * distinguish the remaining code between here and IRET from 1660 * the SYSCALL entry and exit paths. 1661 * 1662 * We arguably should just inspect RIP instead, but I (Andy) wrote 1663 * this code when I had the misapprehension that Xen PV supported 1664 * NMIs, and Xen PV would break that approach. 1665 */ 1666 std 1667 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1668 1669 /* 1670 * iretq reads the "iret" frame and exits the NMI stack in a 1671 * single instruction. We are returning to kernel mode, so this 1672 * cannot result in a fault. Similarly, we don't need to worry 1673 * about espfix64 on the way back to kernel mode. 1674 */ 1675 iretq 1676END(nmi) 1677 1678ENTRY(ignore_sysret) 1679 UNWIND_HINT_EMPTY 1680 mov $-ENOSYS, %eax 1681 sysret 1682END(ignore_sysret) 1683 1684ENTRY(rewind_stack_do_exit) 1685 UNWIND_HINT_FUNC 1686 /* Prevent any naive code from trying to unwind to our caller. */ 1687 xorl %ebp, %ebp 1688 1689 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1690 leaq -PTREGS_SIZE(%rax), %rsp 1691 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1692 1693 call do_exit 1694END(rewind_stack_do_exit) 1695
