1 /*
2 * SH7366 Setup
3 *
4 * Copyright (C) 2008 Renesas Solutions
5 *
6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/uio_driver.h>
17 #include <linux/sh_timer.h>
18 #include <linux/sh_intc.h>
19 #include <linux/usb/r8a66597.h>
20 #include <asm/clock.h>
21
22 static struct plat_sci_port scif0_platform_data = {
23 .scscr = SCSCR_REIE,
24 .type = PORT_SCIF,
25 };
26
27 static struct resource scif0_resources[] = {
28 DEFINE_RES_MEM(0xffe00000, 0x100),
29 DEFINE_RES_IRQ(evt2irq(0xc00)),
30 };
31
32 static struct platform_device scif0_device = {
33 .name = "sh-sci",
34 .id = 0,
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
37 .dev = {
38 .platform_data = &scif0_platform_data,
39 },
40 };
41
42 static struct resource iic_resources[] = {
43 [0] = {
44 .name = "IIC",
45 .start = 0x04470000,
46 .end = 0x04470017,
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .start = evt2irq(0xe00),
51 .end = evt2irq(0xe60),
52 .flags = IORESOURCE_IRQ,
53 },
54 };
55
56 static struct platform_device iic_device = {
57 .name = "i2c-sh_mobile",
58 .id = 0, /* "i2c0" clock */
59 .num_resources = ARRAY_SIZE(iic_resources),
60 .resource = iic_resources,
61 };
62
63 static struct r8a66597_platdata r8a66597_data = {
64 .on_chip = 1,
65 };
66
67 static struct resource usb_host_resources[] = {
68 [0] = {
69 .start = 0xa4d80000,
70 .end = 0xa4d800ff,
71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
74 .start = evt2irq(0xa20),
75 .end = evt2irq(0xa20),
76 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
77 },
78 };
79
80 static struct platform_device usb_host_device = {
81 .name = "r8a66597_hcd",
82 .id = -1,
83 .dev = {
84 .dma_mask = NULL,
85 .coherent_dma_mask = 0xffffffff,
86 .platform_data = &r8a66597_data,
87 },
88 .num_resources = ARRAY_SIZE(usb_host_resources),
89 .resource = usb_host_resources,
90 };
91
92 static struct uio_info vpu_platform_data = {
93 .name = "VPU5",
94 .version = "0",
95 .irq = evt2irq(0x980),
96 };
97
98 static struct resource vpu_resources[] = {
99 [0] = {
100 .name = "VPU",
101 .start = 0xfe900000,
102 .end = 0xfe902807,
103 .flags = IORESOURCE_MEM,
104 },
105 [1] = {
106 /* place holder for contiguous memory */
107 },
108 };
109
110 static struct platform_device vpu_device = {
111 .name = "uio_pdrv_genirq",
112 .id = 0,
113 .dev = {
114 .platform_data = &vpu_platform_data,
115 },
116 .resource = vpu_resources,
117 .num_resources = ARRAY_SIZE(vpu_resources),
118 };
119
120 static struct uio_info veu0_platform_data = {
121 .name = "VEU",
122 .version = "0",
123 .irq = evt2irq(0x8c0),
124 };
125
126 static struct resource veu0_resources[] = {
127 [0] = {
128 .name = "VEU(1)",
129 .start = 0xfe920000,
130 .end = 0xfe9200b7,
131 .flags = IORESOURCE_MEM,
132 },
133 [1] = {
134 /* place holder for contiguous memory */
135 },
136 };
137
138 static struct platform_device veu0_device = {
139 .name = "uio_pdrv_genirq",
140 .id = 1,
141 .dev = {
142 .platform_data = &veu0_platform_data,
143 },
144 .resource = veu0_resources,
145 .num_resources = ARRAY_SIZE(veu0_resources),
146 };
147
148 static struct uio_info veu1_platform_data = {
149 .name = "VEU",
150 .version = "0",
151 .irq = evt2irq(0x560),
152 };
153
154 static struct resource veu1_resources[] = {
155 [0] = {
156 .name = "VEU(2)",
157 .start = 0xfe924000,
158 .end = 0xfe9240b7,
159 .flags = IORESOURCE_MEM,
160 },
161 [1] = {
162 /* place holder for contiguous memory */
163 },
164 };
165
166 static struct platform_device veu1_device = {
167 .name = "uio_pdrv_genirq",
168 .id = 2,
169 .dev = {
170 .platform_data = &veu1_platform_data,
171 },
172 .resource = veu1_resources,
173 .num_resources = ARRAY_SIZE(veu1_resources),
174 };
175
176 static struct sh_timer_config cmt_platform_data = {
177 .channels_mask = 0x20,
178 };
179
180 static struct resource cmt_resources[] = {
181 DEFINE_RES_MEM(0x044a0000, 0x70),
182 DEFINE_RES_IRQ(evt2irq(0xf00)),
183 };
184
185 static struct platform_device cmt_device = {
186 .name = "sh-cmt-32",
187 .id = 0,
188 .dev = {
189 .platform_data = &cmt_platform_data,
190 },
191 .resource = cmt_resources,
192 .num_resources = ARRAY_SIZE(cmt_resources),
193 };
194
195 static struct sh_timer_config tmu0_platform_data = {
196 .channels_mask = 7,
197 };
198
199 static struct resource tmu0_resources[] = {
200 DEFINE_RES_MEM(0xffd80000, 0x2c),
201 DEFINE_RES_IRQ(evt2irq(0x400)),
202 DEFINE_RES_IRQ(evt2irq(0x420)),
203 DEFINE_RES_IRQ(evt2irq(0x440)),
204 };
205
206 static struct platform_device tmu0_device = {
207 .name = "sh-tmu",
208 .id = 0,
209 .dev = {
210 .platform_data = &tmu0_platform_data,
211 },
212 .resource = tmu0_resources,
213 .num_resources = ARRAY_SIZE(tmu0_resources),
214 };
215
216 static struct platform_device *sh7366_devices[] __initdata = {
217 &scif0_device,
218 &cmt_device,
219 &tmu0_device,
220 &iic_device,
221 &usb_host_device,
222 &vpu_device,
223 &veu0_device,
224 &veu1_device,
225 };
226
sh7366_devices_setup(void)227 static int __init sh7366_devices_setup(void)
228 {
229 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
230 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
231 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
232
233 return platform_add_devices(sh7366_devices,
234 ARRAY_SIZE(sh7366_devices));
235 }
236 arch_initcall(sh7366_devices_setup);
237
238 static struct platform_device *sh7366_early_devices[] __initdata = {
239 &scif0_device,
240 &cmt_device,
241 &tmu0_device,
242 };
243
plat_early_device_setup(void)244 void __init plat_early_device_setup(void)
245 {
246 early_platform_add_devices(sh7366_early_devices,
247 ARRAY_SIZE(sh7366_early_devices));
248 }
249
250 enum {
251 UNUSED=0,
252 ENABLED,
253 DISABLED,
254
255 /* interrupt sources */
256 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
257 ICB,
258 DMAC0, DMAC1, DMAC2, DMAC3,
259 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
260 MFI, VPU, USB,
261 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
262 DMAC4, DMAC5, DMAC_DADERR,
263 SCIF, SCIFA1, SCIFA2,
264 DENC, MSIOF,
265 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
266 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
267 SDHI, CMT, TSIF, SIU,
268 TMU0, TMU1, TMU2,
269 VEU2, LCDC,
270
271 /* interrupt groups */
272
273 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
274 };
275
276 static struct intc_vect vectors[] __initdata = {
277 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
278 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
279 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
280 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
281 INTC_VECT(ICB, 0x700),
282 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
283 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
284 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
285 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
286 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
287 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
288 INTC_VECT(MMC_MMC3I, 0xb40),
289 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
290 INTC_VECT(DMAC_DADERR, 0xbc0),
291 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
292 INTC_VECT(SCIFA2, 0xc40),
293 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
294 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
295 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
296 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
297 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
298 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
299 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
300 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
301 INTC_VECT(SIU, 0xf80),
302 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
303 INTC_VECT(TMU2, 0x440),
304 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
305 };
306
307 static struct intc_group groups[] __initdata = {
308 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
309 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
310 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
311 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
312 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
313 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
314 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
315 };
316
317 static struct intc_mask_reg mask_registers[] __initdata = {
318 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
319 { } },
320 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
321 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
322 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
323 { 0, 0, 0, VPU, 0, 0, 0, MFI } },
324 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
325 { 0, 0, 0, ICB } },
326 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
327 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
328 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
329 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
330 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
331 { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
332 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
333 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
334 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
335 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
336 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
337 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
338 { 0, 0, 0, CMT, 0, USB, } },
339 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
340 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
341 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
342 { 0, 0, 0, 0, 0, 0, 0, TSIF } },
343 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
344 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
345 };
346
347 static struct intc_prio_reg prio_registers[] __initdata = {
348 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
349 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
350 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
351 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
352 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
353 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
354 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
355 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
356 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
357 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
358 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
359 { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
360 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
361 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
362 };
363
364 static struct intc_sense_reg sense_registers[] __initdata = {
365 { 0xa414001c, 16, 2, /* ICR1 */
366 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
367 };
368
369 static struct intc_mask_reg ack_registers[] __initdata = {
370 { 0xa4140024, 0, 8, /* INTREQ00 */
371 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
372 };
373
374 static struct intc_desc intc_desc __initdata = {
375 .name = "sh7366",
376 .force_enable = ENABLED,
377 .force_disable = DISABLED,
378 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
379 prio_registers, sense_registers, ack_registers),
380 };
381
plat_irq_setup(void)382 void __init plat_irq_setup(void)
383 {
384 register_intc_controller(&intc_desc);
385 }
386
plat_mem_setup(void)387 void __init plat_mem_setup(void)
388 {
389 /* TODO: Register Node 1 */
390 }
391
