1 /*
2 * SH7269 Setup
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 * Copyright (C) 2012 Phil Edworthy
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/usb/r8a66597.h>
16 #include <linux/sh_timer.h>
17 #include <linux/io.h>
18
19 enum {
20 UNUSED = 0,
21
22 /* interrupt sources */
23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
24 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
25
26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
27 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
28 USB, VDC4, CMT0, CMT1, BSC, WDT,
29 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
30 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
31 PWMT1, PWMT2, ADC_ADI,
32 SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
33 RSPDIF,
34 IIC30, IIC31, IIC32, IIC33,
35 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
36 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
37 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
38 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
39 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
40 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
41 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
42 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
43 RCAN0, RCAN1, RCAN2,
44 RSPIC0, RSPIC1,
45 IEBC, CD_ROMD,
46 NFMC,
47 SDHI0, SDHI1,
48 RTC,
49 SRCC0, SRCC1, SRCC2,
50
51 /* interrupt groups */
52 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
53 };
54
55 static struct intc_vect vectors[] __initdata = {
56 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
57 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
58 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
59 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
60
61 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
62 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
63 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
64 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
65
66 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
67 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
68 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
69 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
70 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
71 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
72 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
73 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
74 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
75 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
76 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
77 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
78 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
79 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
80 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
81 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
82
83 INTC_IRQ(USB, 170),
84
85 INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
86 INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
87 INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
88 INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
89
90 INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
91
92 INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
93
94 INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
95 INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
96 INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
97 INTC_IRQ(MTU0_VEF, 198),
98 INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
99 INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
100 INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
101 INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
102 INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
103 INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
104 INTC_IRQ(MTU3_TCI3V, 211),
105 INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
106 INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
107 INTC_IRQ(MTU4_TCI4V, 216),
108
109 INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
110
111 INTC_IRQ(ADC_ADI, 223),
112
113 INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
114 INTC_IRQ(SSIF0, 226),
115 INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
116 INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
117 INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
118 INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
119 INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
120
121 INTC_IRQ(RSPDIF, 237),
122
123 INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
124 INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
125 INTC_IRQ(IIC30, 242),
126 INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
127 INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
128 INTC_IRQ(IIC31, 247),
129 INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
130 INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
131 INTC_IRQ(IIC32, 252),
132 INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
133 INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
134 INTC_IRQ(IIC33, 257),
135
136 INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
137 INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
138 INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
139 INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
140 INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
141 INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
142 INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
143 INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
144 INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
145 INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
146 INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
147 INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
148 INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
149 INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
150 INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
151 INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
152
153 INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
154 INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
155 INTC_IRQ(RCAN0, 295),
156 INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
157 INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
158 INTC_IRQ(RCAN1, 300),
159 INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
160 INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
161 INTC_IRQ(RCAN2, 305),
162
163 INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
164 INTC_IRQ(RSPIC0, 308),
165 INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
166 INTC_IRQ(RSPIC1, 311),
167
168 INTC_IRQ(IEBC, 318),
169
170 INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
171 INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
172 INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
173
174 INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
175 INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
176
177 INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
178 INTC_IRQ(SDHI0, 334),
179 INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
180 INTC_IRQ(SDHI1, 337),
181
182 INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
183 INTC_IRQ(RTC, 340),
184
185 INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
186 INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
187 INTC_IRQ(SRCC0, 345),
188 INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
189 INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
190 INTC_IRQ(SRCC1, 350),
191 INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
192 INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
193 INTC_IRQ(SRCC2, 355),
194 };
195
196 static struct intc_group groups[] __initdata = {
197 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
198 PINT4, PINT5, PINT6, PINT7),
199 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
200 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
201 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
202 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
203 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
204 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
205 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
206 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
207 };
208
209 static struct intc_prio_reg prio_registers[] __initdata = {
210 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
211 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
212 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
213 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
214 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
215 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
216 DMAC10, DMAC11 } },
217 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
218 DMAC14, DMAC15 } },
219 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
220 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
221 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
222 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
223 MTU1_AB, MTU1_VU } },
224 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
225 MTU3_ABCD, MTU3_TCI3V } },
226 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
227 PWMT1, PWMT2 } },
228 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
229 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
230 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
231 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
232 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
233 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
234 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
235 { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
236 { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
237 { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
238 { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
239 };
240
241 static struct intc_mask_reg mask_registers[] __initdata = {
242 { 0xfffe0808, 0, 16, /* PINTER */
243 { 0, 0, 0, 0, 0, 0, 0, 0,
244 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
245 };
246
247 static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
248 mask_registers, prio_registers, NULL);
249
250 static struct plat_sci_port scif0_platform_data = {
251 .scscr = SCSCR_REIE,
252 .type = PORT_SCIF,
253 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
254 };
255
256 static struct resource scif0_resources[] = {
257 DEFINE_RES_MEM(0xe8007000, 0x100),
258 DEFINE_RES_IRQ(259),
259 DEFINE_RES_IRQ(260),
260 DEFINE_RES_IRQ(261),
261 DEFINE_RES_IRQ(258),
262 };
263
264 static struct platform_device scif0_device = {
265 .name = "sh-sci",
266 .id = 0,
267 .resource = scif0_resources,
268 .num_resources = ARRAY_SIZE(scif0_resources),
269 .dev = {
270 .platform_data = &scif0_platform_data,
271 },
272 };
273
274 static struct plat_sci_port scif1_platform_data = {
275 .scscr = SCSCR_REIE,
276 .type = PORT_SCIF,
277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
278 };
279
280 static struct resource scif1_resources[] = {
281 DEFINE_RES_MEM(0xe8007800, 0x100),
282 DEFINE_RES_IRQ(263),
283 DEFINE_RES_IRQ(264),
284 DEFINE_RES_IRQ(265),
285 DEFINE_RES_IRQ(262),
286 };
287
288 static struct platform_device scif1_device = {
289 .name = "sh-sci",
290 .id = 1,
291 .resource = scif1_resources,
292 .num_resources = ARRAY_SIZE(scif1_resources),
293 .dev = {
294 .platform_data = &scif1_platform_data,
295 },
296 };
297
298 static struct plat_sci_port scif2_platform_data = {
299 .scscr = SCSCR_REIE,
300 .type = PORT_SCIF,
301 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
302 };
303
304 static struct resource scif2_resources[] = {
305 DEFINE_RES_MEM(0xe8008000, 0x100),
306 DEFINE_RES_IRQ(267),
307 DEFINE_RES_IRQ(268),
308 DEFINE_RES_IRQ(269),
309 DEFINE_RES_IRQ(266),
310 };
311
312 static struct platform_device scif2_device = {
313 .name = "sh-sci",
314 .id = 2,
315 .resource = scif2_resources,
316 .num_resources = ARRAY_SIZE(scif2_resources),
317 .dev = {
318 .platform_data = &scif2_platform_data,
319 },
320 };
321
322 static struct plat_sci_port scif3_platform_data = {
323 .scscr = SCSCR_REIE,
324 .type = PORT_SCIF,
325 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
326 };
327
328 static struct resource scif3_resources[] = {
329 DEFINE_RES_MEM(0xe8008800, 0x100),
330 DEFINE_RES_IRQ(271),
331 DEFINE_RES_IRQ(272),
332 DEFINE_RES_IRQ(273),
333 DEFINE_RES_IRQ(270),
334 };
335
336 static struct platform_device scif3_device = {
337 .name = "sh-sci",
338 .id = 3,
339 .resource = scif3_resources,
340 .num_resources = ARRAY_SIZE(scif3_resources),
341 .dev = {
342 .platform_data = &scif3_platform_data,
343 },
344 };
345
346 static struct plat_sci_port scif4_platform_data = {
347 .scscr = SCSCR_REIE,
348 .type = PORT_SCIF,
349 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
350 };
351
352 static struct resource scif4_resources[] = {
353 DEFINE_RES_MEM(0xe8009000, 0x100),
354 DEFINE_RES_IRQ(275),
355 DEFINE_RES_IRQ(276),
356 DEFINE_RES_IRQ(277),
357 DEFINE_RES_IRQ(274),
358 };
359
360 static struct platform_device scif4_device = {
361 .name = "sh-sci",
362 .id = 4,
363 .resource = scif4_resources,
364 .num_resources = ARRAY_SIZE(scif4_resources),
365 .dev = {
366 .platform_data = &scif4_platform_data,
367 },
368 };
369
370 static struct plat_sci_port scif5_platform_data = {
371 .scscr = SCSCR_REIE,
372 .type = PORT_SCIF,
373 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
374 };
375
376 static struct resource scif5_resources[] = {
377 DEFINE_RES_MEM(0xe8009800, 0x100),
378 DEFINE_RES_IRQ(279),
379 DEFINE_RES_IRQ(280),
380 DEFINE_RES_IRQ(281),
381 DEFINE_RES_IRQ(278),
382 };
383
384 static struct platform_device scif5_device = {
385 .name = "sh-sci",
386 .id = 5,
387 .resource = scif5_resources,
388 .num_resources = ARRAY_SIZE(scif5_resources),
389 .dev = {
390 .platform_data = &scif5_platform_data,
391 },
392 };
393
394 static struct plat_sci_port scif6_platform_data = {
395 .scscr = SCSCR_REIE,
396 .type = PORT_SCIF,
397 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
398 };
399
400 static struct resource scif6_resources[] = {
401 DEFINE_RES_MEM(0xe800a000, 0x100),
402 DEFINE_RES_IRQ(283),
403 DEFINE_RES_IRQ(284),
404 DEFINE_RES_IRQ(285),
405 DEFINE_RES_IRQ(282),
406 };
407
408 static struct platform_device scif6_device = {
409 .name = "sh-sci",
410 .id = 6,
411 .resource = scif6_resources,
412 .num_resources = ARRAY_SIZE(scif6_resources),
413 .dev = {
414 .platform_data = &scif6_platform_data,
415 },
416 };
417
418 static struct plat_sci_port scif7_platform_data = {
419 .scscr = SCSCR_REIE,
420 .type = PORT_SCIF,
421 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
422 };
423
424 static struct resource scif7_resources[] = {
425 DEFINE_RES_MEM(0xe800a800, 0x100),
426 DEFINE_RES_IRQ(287),
427 DEFINE_RES_IRQ(288),
428 DEFINE_RES_IRQ(289),
429 DEFINE_RES_IRQ(286),
430 };
431
432 static struct platform_device scif7_device = {
433 .name = "sh-sci",
434 .id = 7,
435 .resource = scif7_resources,
436 .num_resources = ARRAY_SIZE(scif7_resources),
437 .dev = {
438 .platform_data = &scif7_platform_data,
439 },
440 };
441
442 static struct sh_timer_config cmt_platform_data = {
443 .channels_mask = 3,
444 };
445
446 static struct resource cmt_resources[] = {
447 DEFINE_RES_MEM(0xfffec000, 0x10),
448 DEFINE_RES_IRQ(188),
449 DEFINE_RES_IRQ(189),
450 };
451
452 static struct platform_device cmt_device = {
453 .name = "sh-cmt-16",
454 .id = 0,
455 .dev = {
456 .platform_data = &cmt_platform_data,
457 },
458 .resource = cmt_resources,
459 .num_resources = ARRAY_SIZE(cmt_resources),
460 };
461
462 static struct resource mtu2_resources[] = {
463 DEFINE_RES_MEM(0xfffe4000, 0x400),
464 DEFINE_RES_IRQ_NAMED(192, "tgi0a"),
465 DEFINE_RES_IRQ_NAMED(203, "tgi1a"),
466 };
467
468 static struct platform_device mtu2_device = {
469 .name = "sh-mtu2",
470 .id = -1,
471 .resource = mtu2_resources,
472 .num_resources = ARRAY_SIZE(mtu2_resources),
473 };
474
475 static struct resource rtc_resources[] = {
476 [0] = {
477 .start = 0xfffe6000,
478 .end = 0xfffe6000 + 0x30 - 1,
479 .flags = IORESOURCE_IO,
480 },
481 [1] = {
482 /* Shared Period/Carry/Alarm IRQ */
483 .start = 338,
484 .flags = IORESOURCE_IRQ,
485 },
486 };
487
488 static struct platform_device rtc_device = {
489 .name = "sh-rtc",
490 .id = -1,
491 .num_resources = ARRAY_SIZE(rtc_resources),
492 .resource = rtc_resources,
493 };
494
495 /* USB Host */
496 static struct r8a66597_platdata r8a66597_data = {
497 .on_chip = 1,
498 .endian = 1,
499 };
500
501 static struct resource r8a66597_usb_host_resources[] = {
502 [0] = {
503 .start = 0xe8010000,
504 .end = 0xe80100e4,
505 .flags = IORESOURCE_MEM,
506 },
507 [1] = {
508 .start = 170,
509 .end = 170,
510 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
511 },
512 };
513
514 static struct platform_device r8a66597_usb_host_device = {
515 .name = "r8a66597_hcd",
516 .id = 0,
517 .dev = {
518 .dma_mask = NULL, /* not use dma */
519 .coherent_dma_mask = 0xffffffff,
520 .platform_data = &r8a66597_data,
521 },
522 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
523 .resource = r8a66597_usb_host_resources,
524 };
525
526 static struct platform_device *sh7269_devices[] __initdata = {
527 &scif0_device,
528 &scif1_device,
529 &scif2_device,
530 &scif3_device,
531 &scif4_device,
532 &scif5_device,
533 &scif6_device,
534 &scif7_device,
535 &cmt_device,
536 &mtu2_device,
537 &rtc_device,
538 &r8a66597_usb_host_device,
539 };
540
sh7269_devices_setup(void)541 static int __init sh7269_devices_setup(void)
542 {
543 return platform_add_devices(sh7269_devices,
544 ARRAY_SIZE(sh7269_devices));
545 }
546 arch_initcall(sh7269_devices_setup);
547
plat_irq_setup(void)548 void __init plat_irq_setup(void)
549 {
550 register_intc_controller(&intc_desc);
551 }
552
553 static struct platform_device *sh7269_early_devices[] __initdata = {
554 &scif0_device,
555 &scif1_device,
556 &scif2_device,
557 &scif3_device,
558 &scif4_device,
559 &scif5_device,
560 &scif6_device,
561 &scif7_device,
562 &cmt_device,
563 &mtu2_device,
564 };
565
plat_early_device_setup(void)566 void __init plat_early_device_setup(void)
567 {
568 early_platform_add_devices(sh7269_early_devices,
569 ARRAY_SIZE(sh7269_early_devices));
570 }
571
