1 /*
2 * arch/sh/kernel/cpu/sh2a/opcode_helper.c
3 *
4 * Helper for the SH-2A 32-bit opcodes.
5 *
6 * Copyright (C) 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12 #include <linux/kernel.h>
13
14 /*
15 * Instructions on SH are generally fixed at 16-bits, however, SH-2A
16 * introduces some 32-bit instructions. Since there are no real
17 * constraints on their use (and they can be mixed and matched), we need
18 * to check the instruction encoding to work out if it's a true 32-bit
19 * instruction or not.
20 *
21 * Presently, 32-bit opcodes have only slight variations in what the
22 * actual encoding looks like in the first-half of the instruction, which
23 * makes it fairly straightforward to differentiate from the 16-bit ones.
24 *
25 * First 16-bits of encoding Used by
26 *
27 * 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d,
28 * fmov.s, movu.b, movu.w
29 *
30 * 0011nnnn0iii1001 bclr.b, bld.b, bset.b, bst.b, band.b,
31 * bandnot.b, bldnot.b, bor.b, bornot.b,
32 * bxor.b
33 *
34 * 0000nnnniiii0000 movi20
35 * 0000nnnniiii0001 movi20s
36 */
instruction_size(unsigned int insn)37 unsigned int instruction_size(unsigned int insn)
38 {
39 /* Look for the common cases */
40 switch ((insn & 0xf00f)) {
41 case 0x0000: /* movi20 */
42 case 0x0001: /* movi20s */
43 case 0x3001: /* 32-bit mov/fmov/movu variants */
44 return 4;
45 }
46
47 /* And the special cases.. */
48 switch ((insn & 0xf08f)) {
49 case 0x3009: /* 32-bit b*.b bit operations */
50 return 4;
51 }
52
53 return 2;
54 }
55
