1 /*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/seq_file.h>
15 #include <linux/root_dev.h>
16 #include <linux/cpu.h>
17 #include <linux/console.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20
21 #include <asm/io.h>
22 #include <asm/prom.h>
23 #include <asm/processor.h>
24 #include <asm/pgtable.h>
25 #include <asm/setup.h>
26 #include <asm/smp.h>
27 #include <asm/elf.h>
28 #include <asm/cputable.h>
29 #include <asm/bootx.h>
30 #include <asm/btext.h>
31 #include <asm/machdep.h>
32 #include <linux/uaccess.h>
33 #include <asm/pmac_feature.h>
34 #include <asm/sections.h>
35 #include <asm/nvram.h>
36 #include <asm/xmon.h>
37 #include <asm/time.h>
38 #include <asm/serial.h>
39 #include <asm/udbg.h>
40 #include <asm/code-patching.h>
41 #include <asm/cpu_has_feature.h>
42 #include <asm/asm-prototypes.h>
43 #include <asm/kdump.h>
44 #include <asm/feature-fixups.h>
45
46 #include "setup.h"
47
48 #define DBG(fmt...)
49
50 extern void bootx_init(unsigned long r4, unsigned long phys);
51
52 int boot_cpuid_phys;
53 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
54
55 int smp_hw_index[NR_CPUS];
56 EXPORT_SYMBOL(smp_hw_index);
57
58 unsigned long ISA_DMA_THRESHOLD;
59 unsigned int DMA_MODE_READ;
60 unsigned int DMA_MODE_WRITE;
61
62 EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
63 EXPORT_SYMBOL(DMA_MODE_READ);
64 EXPORT_SYMBOL(DMA_MODE_WRITE);
65
66 /*
67 * We're called here very early in the boot.
68 *
69 * Note that the kernel may be running at an address which is different
70 * from the address that it was linked at, so we must use RELOC/PTRRELOC
71 * to access static data (including strings). -- paulus
72 */
early_init(unsigned long dt_ptr)73 notrace unsigned long __init early_init(unsigned long dt_ptr)
74 {
75 unsigned long offset = reloc_offset();
76
77 /* First zero the BSS -- use memset_io, some platforms don't have
78 * caches on yet */
79 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
80 __bss_stop - __bss_start);
81
82 /*
83 * Identify the CPU type and fix up code sections
84 * that depend on which cpu we have.
85 */
86 identify_cpu(offset, mfspr(SPRN_PVR));
87
88 apply_feature_fixups();
89
90 return KERNELBASE + offset;
91 }
92
93
94 /*
95 * This is run before start_kernel(), the kernel has been relocated
96 * and we are running with enough of the MMU enabled to have our
97 * proper kernel virtual addresses
98 *
99 * We do the initial parsing of the flat device-tree and prepares
100 * for the MMU to be fully initialized.
101 */
machine_init(u64 dt_ptr)102 notrace void __init machine_init(u64 dt_ptr)
103 {
104 unsigned int *addr = (unsigned int *)((unsigned long)&patch__memset_nocache +
105 patch__memset_nocache);
106 unsigned long insn;
107
108 /* Configure static keys first, now that we're relocated. */
109 setup_feature_keys();
110
111 /* Enable early debugging if any specified (see udbg.h) */
112 udbg_early_init();
113
114 patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP);
115
116 insn = create_cond_branch(addr, branch_target(addr), 0x820000);
117 patch_instruction(addr, insn); /* replace b by bne cr0 */
118
119 /* Do some early initialization based on the flat device tree */
120 early_init_devtree(__va(dt_ptr));
121
122 early_init_mmu();
123
124 setup_kdump_trampoline();
125 }
126
127 /* Checks "l2cr=xxxx" command-line option */
ppc_setup_l2cr(char * str)128 static int __init ppc_setup_l2cr(char *str)
129 {
130 if (cpu_has_feature(CPU_FTR_L2CR)) {
131 unsigned long val = simple_strtoul(str, NULL, 0);
132 printk(KERN_INFO "l2cr set to %lx\n", val);
133 _set_L2CR(0); /* force invalidate by disable cache */
134 _set_L2CR(val); /* and enable it */
135 }
136 return 1;
137 }
138 __setup("l2cr=", ppc_setup_l2cr);
139
140 /* Checks "l3cr=xxxx" command-line option */
ppc_setup_l3cr(char * str)141 static int __init ppc_setup_l3cr(char *str)
142 {
143 if (cpu_has_feature(CPU_FTR_L3CR)) {
144 unsigned long val = simple_strtoul(str, NULL, 0);
145 printk(KERN_INFO "l3cr set to %lx\n", val);
146 _set_L3CR(val); /* and enable it */
147 }
148 return 1;
149 }
150 __setup("l3cr=", ppc_setup_l3cr);
151
152 #ifdef CONFIG_GENERIC_NVRAM
153
154 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
nvram_read_byte(int addr)155 unsigned char nvram_read_byte(int addr)
156 {
157 if (ppc_md.nvram_read_val)
158 return ppc_md.nvram_read_val(addr);
159 return 0xff;
160 }
161 EXPORT_SYMBOL(nvram_read_byte);
162
nvram_write_byte(unsigned char val,int addr)163 void nvram_write_byte(unsigned char val, int addr)
164 {
165 if (ppc_md.nvram_write_val)
166 ppc_md.nvram_write_val(addr, val);
167 }
168 EXPORT_SYMBOL(nvram_write_byte);
169
nvram_get_size(void)170 ssize_t nvram_get_size(void)
171 {
172 if (ppc_md.nvram_size)
173 return ppc_md.nvram_size();
174 return -1;
175 }
176 EXPORT_SYMBOL(nvram_get_size);
177
nvram_sync(void)178 void nvram_sync(void)
179 {
180 if (ppc_md.nvram_sync)
181 ppc_md.nvram_sync();
182 }
183 EXPORT_SYMBOL(nvram_sync);
184
185 #endif /* CONFIG_NVRAM */
186
ppc_init(void)187 static int __init ppc_init(void)
188 {
189 /* clear the progress line */
190 if (ppc_md.progress)
191 ppc_md.progress(" ", 0xffff);
192
193 /* call platform init */
194 if (ppc_md.init != NULL) {
195 ppc_md.init();
196 }
197 return 0;
198 }
199 arch_initcall(ppc_init);
200
irqstack_early_init(void)201 void __init irqstack_early_init(void)
202 {
203 unsigned int i;
204
205 /* interrupt stacks must be in lowmem, we get that for free on ppc32
206 * as the memblock is limited to lowmem by default */
207 for_each_possible_cpu(i) {
208 softirq_ctx[i] = (struct thread_info *)
209 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
210 hardirq_ctx[i] = (struct thread_info *)
211 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
212 }
213 }
214
215 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
exc_lvl_early_init(void)216 void __init exc_lvl_early_init(void)
217 {
218 unsigned int i, hw_cpu;
219
220 /* interrupt stacks must be in lowmem, we get that for free on ppc32
221 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
222 for_each_possible_cpu(i) {
223 #ifdef CONFIG_SMP
224 hw_cpu = get_hard_smp_processor_id(i);
225 #else
226 hw_cpu = 0;
227 #endif
228
229 critirq_ctx[hw_cpu] = (struct thread_info *)
230 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
231 #ifdef CONFIG_BOOKE
232 dbgirq_ctx[hw_cpu] = (struct thread_info *)
233 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
234 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
235 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
236 #endif
237 }
238 }
239 #endif
240
setup_power_save(void)241 void __init setup_power_save(void)
242 {
243 #ifdef CONFIG_6xx
244 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
245 cpu_has_feature(CPU_FTR_CAN_NAP))
246 ppc_md.power_save = ppc6xx_idle;
247 #endif
248
249 #ifdef CONFIG_E500
250 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
251 cpu_has_feature(CPU_FTR_CAN_NAP))
252 ppc_md.power_save = e500_idle;
253 #endif
254 }
255
initialize_cache_info(void)256 __init void initialize_cache_info(void)
257 {
258 /*
259 * Set cache line size based on type of cpu as a default.
260 * Systems with OF can look in the properties on the cpu node(s)
261 * for a possibly more accurate value.
262 */
263 dcache_bsize = cur_cpu_spec->dcache_bsize;
264 icache_bsize = cur_cpu_spec->icache_bsize;
265 ucache_bsize = 0;
266 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
267 ucache_bsize = icache_bsize = dcache_bsize;
268 }
269
