1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2011 John Crispin <john@phrozen.org>
16 */
17
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/io.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/export.h>
23 #include <linux/spinlock.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26
27 #include <lantiq_soc.h>
28 #include <xway_dma.h>
29
30 #define LTQ_DMA_ID 0x08
31 #define LTQ_DMA_CTRL 0x10
32 #define LTQ_DMA_CPOLL 0x14
33 #define LTQ_DMA_CS 0x18
34 #define LTQ_DMA_CCTRL 0x1C
35 #define LTQ_DMA_CDBA 0x20
36 #define LTQ_DMA_CDLEN 0x24
37 #define LTQ_DMA_CIS 0x28
38 #define LTQ_DMA_CIE 0x2C
39 #define LTQ_DMA_PS 0x40
40 #define LTQ_DMA_PCTRL 0x44
41 #define LTQ_DMA_IRNEN 0xf4
42
43 #define DMA_DESCPT BIT(3) /* descriptor complete irq */
44 #define DMA_TX BIT(8) /* TX channel direction */
45 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */
46 #define DMA_PDEN BIT(6) /* enable packet drop */
47 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */
48 #define DMA_RESET BIT(0) /* channel on / off bit */
49 #define DMA_IRQ_ACK 0x7e /* IRQ status register */
50 #define DMA_POLL BIT(31) /* turn on channel polling */
51 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
52 #define DMA_2W_BURST BIT(1) /* 2 word burst length */
53 #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
54 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
55 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
56
57 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
58 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
59 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
60 ltq_dma_membase + (z))
61
62 static void __iomem *ltq_dma_membase;
63 static DEFINE_SPINLOCK(ltq_dma_lock);
64
65 void
ltq_dma_enable_irq(struct ltq_dma_channel * ch)66 ltq_dma_enable_irq(struct ltq_dma_channel *ch)
67 {
68 unsigned long flags;
69
70 spin_lock_irqsave(<q_dma_lock, flags);
71 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
72 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
73 spin_unlock_irqrestore(<q_dma_lock, flags);
74 }
75 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
76
77 void
ltq_dma_disable_irq(struct ltq_dma_channel * ch)78 ltq_dma_disable_irq(struct ltq_dma_channel *ch)
79 {
80 unsigned long flags;
81
82 spin_lock_irqsave(<q_dma_lock, flags);
83 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
84 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
85 spin_unlock_irqrestore(<q_dma_lock, flags);
86 }
87 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
88
89 void
ltq_dma_ack_irq(struct ltq_dma_channel * ch)90 ltq_dma_ack_irq(struct ltq_dma_channel *ch)
91 {
92 unsigned long flags;
93
94 spin_lock_irqsave(<q_dma_lock, flags);
95 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
96 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
97 spin_unlock_irqrestore(<q_dma_lock, flags);
98 }
99 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
100
101 void
ltq_dma_open(struct ltq_dma_channel * ch)102 ltq_dma_open(struct ltq_dma_channel *ch)
103 {
104 unsigned long flag;
105
106 spin_lock_irqsave(<q_dma_lock, flag);
107 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
108 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
109 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
110 spin_unlock_irqrestore(<q_dma_lock, flag);
111 }
112 EXPORT_SYMBOL_GPL(ltq_dma_open);
113
114 void
ltq_dma_close(struct ltq_dma_channel * ch)115 ltq_dma_close(struct ltq_dma_channel *ch)
116 {
117 unsigned long flag;
118
119 spin_lock_irqsave(<q_dma_lock, flag);
120 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
121 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
122 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
123 spin_unlock_irqrestore(<q_dma_lock, flag);
124 }
125 EXPORT_SYMBOL_GPL(ltq_dma_close);
126
127 static void
ltq_dma_alloc(struct ltq_dma_channel * ch)128 ltq_dma_alloc(struct ltq_dma_channel *ch)
129 {
130 unsigned long flags;
131
132 ch->desc = 0;
133 ch->desc_base = dma_zalloc_coherent(ch->dev,
134 LTQ_DESC_NUM * LTQ_DESC_SIZE,
135 &ch->phys, GFP_ATOMIC);
136
137 spin_lock_irqsave(<q_dma_lock, flags);
138 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
139 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
140 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
141 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
142 wmb();
143 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
144 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
145 ;
146 spin_unlock_irqrestore(<q_dma_lock, flags);
147 }
148
149 void
ltq_dma_alloc_tx(struct ltq_dma_channel * ch)150 ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
151 {
152 unsigned long flags;
153
154 ltq_dma_alloc(ch);
155
156 spin_lock_irqsave(<q_dma_lock, flags);
157 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
158 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
159 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
160 spin_unlock_irqrestore(<q_dma_lock, flags);
161 }
162 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
163
164 void
ltq_dma_alloc_rx(struct ltq_dma_channel * ch)165 ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
166 {
167 unsigned long flags;
168
169 ltq_dma_alloc(ch);
170
171 spin_lock_irqsave(<q_dma_lock, flags);
172 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
173 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
174 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
175 spin_unlock_irqrestore(<q_dma_lock, flags);
176 }
177 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
178
179 void
ltq_dma_free(struct ltq_dma_channel * ch)180 ltq_dma_free(struct ltq_dma_channel *ch)
181 {
182 if (!ch->desc_base)
183 return;
184 ltq_dma_close(ch);
185 dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE,
186 ch->desc_base, ch->phys);
187 }
188 EXPORT_SYMBOL_GPL(ltq_dma_free);
189
190 void
ltq_dma_init_port(int p)191 ltq_dma_init_port(int p)
192 {
193 ltq_dma_w32(p, LTQ_DMA_PS);
194 switch (p) {
195 case DMA_PORT_ETOP:
196 /*
197 * Tell the DMA engine to swap the endianness of data frames and
198 * drop packets if the channel arbitration fails.
199 */
200 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
201 LTQ_DMA_PCTRL);
202 break;
203
204 case DMA_PORT_DEU:
205 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
206 LTQ_DMA_PCTRL);
207 break;
208
209 default:
210 break;
211 }
212 }
213 EXPORT_SYMBOL_GPL(ltq_dma_init_port);
214
215 static int
ltq_dma_init(struct platform_device * pdev)216 ltq_dma_init(struct platform_device *pdev)
217 {
218 struct clk *clk;
219 struct resource *res;
220 unsigned id;
221 int i;
222
223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
225 if (IS_ERR(ltq_dma_membase))
226 panic("Failed to remap dma resource");
227
228 /* power up and reset the dma engine */
229 clk = clk_get(&pdev->dev, NULL);
230 if (IS_ERR(clk))
231 panic("Failed to get dma clock");
232
233 clk_enable(clk);
234 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
235
236 /* disable all interrupts */
237 ltq_dma_w32(0, LTQ_DMA_IRNEN);
238
239 /* reset/configure each channel */
240 for (i = 0; i < DMA_MAX_CHANNEL; i++) {
241 ltq_dma_w32(i, LTQ_DMA_CS);
242 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
243 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
244 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
245 }
246
247 id = ltq_dma_r32(LTQ_DMA_ID);
248 dev_info(&pdev->dev,
249 "Init done - hw rev: %X, ports: %d, channels: %d\n",
250 id & 0x1f, (id >> 16) & 0xf, id >> 20);
251
252 return 0;
253 }
254
255 static const struct of_device_id dma_match[] = {
256 { .compatible = "lantiq,dma-xway" },
257 {},
258 };
259
260 static struct platform_driver dma_driver = {
261 .probe = ltq_dma_init,
262 .driver = {
263 .name = "dma-xway",
264 .of_match_table = dma_match,
265 },
266 };
267
268 int __init
dma_init(void)269 dma_init(void)
270 {
271 return platform_driver_register(&dma_driver);
272 }
273
274 postcore_initcall(dma_init);
275
