1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 David Daney 7 */ 8 9 #include <linux/sched.h> 10 11 #include <asm/processor.h> 12 #include <asm/watch.h> 13 14 /* 15 * Install the watch registers for the current thread. A maximum of 16 * four registers are installed although the machine may have more. 17 */ mips_install_watch_registers(struct task_struct * t)18void mips_install_watch_registers(struct task_struct *t) 19 { 20 struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264; 21 unsigned int watchhi = MIPS_WATCHHI_G | /* Trap all ASIDs */ 22 MIPS_WATCHHI_IRW; /* Clear result bits */ 23 24 switch (current_cpu_data.watch_reg_use_cnt) { 25 default: 26 BUG(); 27 case 4: 28 write_c0_watchlo3(watches->watchlo[3]); 29 write_c0_watchhi3(watchhi | watches->watchhi[3]); 30 case 3: 31 write_c0_watchlo2(watches->watchlo[2]); 32 write_c0_watchhi2(watchhi | watches->watchhi[2]); 33 case 2: 34 write_c0_watchlo1(watches->watchlo[1]); 35 write_c0_watchhi1(watchhi | watches->watchhi[1]); 36 case 1: 37 write_c0_watchlo0(watches->watchlo[0]); 38 write_c0_watchhi0(watchhi | watches->watchhi[0]); 39 } 40 } 41 42 /* 43 * Read back the watchhi registers so the user space debugger has 44 * access to the I, R, and W bits. A maximum of four registers are 45 * read although the machine may have more. 46 */ mips_read_watch_registers(void)47void mips_read_watch_registers(void) 48 { 49 struct mips3264_watch_reg_state *watches = 50 ¤t->thread.watch.mips3264; 51 unsigned int watchhi_mask = MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW; 52 53 switch (current_cpu_data.watch_reg_use_cnt) { 54 default: 55 BUG(); 56 case 4: 57 watches->watchhi[3] = (read_c0_watchhi3() & watchhi_mask); 58 case 3: 59 watches->watchhi[2] = (read_c0_watchhi2() & watchhi_mask); 60 case 2: 61 watches->watchhi[1] = (read_c0_watchhi1() & watchhi_mask); 62 case 1: 63 watches->watchhi[0] = (read_c0_watchhi0() & watchhi_mask); 64 } 65 if (current_cpu_data.watch_reg_use_cnt == 1 && 66 (watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) { 67 /* Pathological case of release 1 architecture that 68 * doesn't set the condition bits. We assume that 69 * since we got here, the watch condition was met and 70 * signal that the conditions requested in watchlo 71 * were met. */ 72 watches->watchhi[0] |= (watches->watchlo[0] & MIPS_WATCHHI_IRW); 73 } 74 } 75 76 /* 77 * Disable all watch registers. Although only four registers are 78 * installed, all are cleared to eliminate the possibility of endless 79 * looping in the watch handler. 80 */ mips_clear_watch_registers(void)81void mips_clear_watch_registers(void) 82 { 83 switch (current_cpu_data.watch_reg_count) { 84 default: 85 BUG(); 86 case 8: 87 write_c0_watchlo7(0); 88 case 7: 89 write_c0_watchlo6(0); 90 case 6: 91 write_c0_watchlo5(0); 92 case 5: 93 write_c0_watchlo4(0); 94 case 4: 95 write_c0_watchlo3(0); 96 case 3: 97 write_c0_watchlo2(0); 98 case 2: 99 write_c0_watchlo1(0); 100 case 1: 101 write_c0_watchlo0(0); 102 } 103 } 104 mips_probe_watch_registers(struct cpuinfo_mips * c)105void mips_probe_watch_registers(struct cpuinfo_mips *c) 106 { 107 unsigned int t; 108 109 if ((c->options & MIPS_CPU_WATCH) == 0) 110 return; 111 /* 112 * Check which of the I,R and W bits are supported, then 113 * disable the register. 114 */ 115 write_c0_watchlo0(MIPS_WATCHLO_IRW); 116 back_to_back_c0_hazard(); 117 t = read_c0_watchlo0(); 118 write_c0_watchlo0(0); 119 c->watch_reg_masks[0] = t & MIPS_WATCHLO_IRW; 120 121 /* Write the mask bits and read them back to determine which 122 * can be used. */ 123 c->watch_reg_count = 1; 124 c->watch_reg_use_cnt = 1; 125 t = read_c0_watchhi0(); 126 write_c0_watchhi0(t | MIPS_WATCHHI_MASK); 127 back_to_back_c0_hazard(); 128 t = read_c0_watchhi0(); 129 c->watch_reg_masks[0] |= (t & MIPS_WATCHHI_MASK); 130 if ((t & MIPS_WATCHHI_M) == 0) 131 return; 132 133 write_c0_watchlo1(MIPS_WATCHLO_IRW); 134 back_to_back_c0_hazard(); 135 t = read_c0_watchlo1(); 136 write_c0_watchlo1(0); 137 c->watch_reg_masks[1] = t & MIPS_WATCHLO_IRW; 138 139 c->watch_reg_count = 2; 140 c->watch_reg_use_cnt = 2; 141 t = read_c0_watchhi1(); 142 write_c0_watchhi1(t | MIPS_WATCHHI_MASK); 143 back_to_back_c0_hazard(); 144 t = read_c0_watchhi1(); 145 c->watch_reg_masks[1] |= (t & MIPS_WATCHHI_MASK); 146 if ((t & MIPS_WATCHHI_M) == 0) 147 return; 148 149 write_c0_watchlo2(MIPS_WATCHLO_IRW); 150 back_to_back_c0_hazard(); 151 t = read_c0_watchlo2(); 152 write_c0_watchlo2(0); 153 c->watch_reg_masks[2] = t & MIPS_WATCHLO_IRW; 154 155 c->watch_reg_count = 3; 156 c->watch_reg_use_cnt = 3; 157 t = read_c0_watchhi2(); 158 write_c0_watchhi2(t | MIPS_WATCHHI_MASK); 159 back_to_back_c0_hazard(); 160 t = read_c0_watchhi2(); 161 c->watch_reg_masks[2] |= (t & MIPS_WATCHHI_MASK); 162 if ((t & MIPS_WATCHHI_M) == 0) 163 return; 164 165 write_c0_watchlo3(MIPS_WATCHLO_IRW); 166 back_to_back_c0_hazard(); 167 t = read_c0_watchlo3(); 168 write_c0_watchlo3(0); 169 c->watch_reg_masks[3] = t & MIPS_WATCHLO_IRW; 170 171 c->watch_reg_count = 4; 172 c->watch_reg_use_cnt = 4; 173 t = read_c0_watchhi3(); 174 write_c0_watchhi3(t | MIPS_WATCHHI_MASK); 175 back_to_back_c0_hazard(); 176 t = read_c0_watchhi3(); 177 c->watch_reg_masks[3] |= (t & MIPS_WATCHHI_MASK); 178 if ((t & MIPS_WATCHHI_M) == 0) 179 return; 180 181 /* We use at most 4, but probe and report up to 8. */ 182 c->watch_reg_count = 5; 183 t = read_c0_watchhi4(); 184 if ((t & MIPS_WATCHHI_M) == 0) 185 return; 186 187 c->watch_reg_count = 6; 188 t = read_c0_watchhi5(); 189 if ((t & MIPS_WATCHHI_M) == 0) 190 return; 191 192 c->watch_reg_count = 7; 193 t = read_c0_watchhi6(); 194 if ((t & MIPS_WATCHHI_M) == 0) 195 return; 196 197 c->watch_reg_count = 8; 198 } 199
