1 // SPDX-License-Identifier: GPL-2.0
2 /***************************************************************************/
3
4 /*
5 * m5249.c -- platform support for ColdFire 5249 based boards
6 *
7 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
8 */
9
10 /***************************************************************************/
11
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/platform_device.h>
17 #include <asm/machdep.h>
18 #include <asm/coldfire.h>
19 #include <asm/mcfsim.h>
20 #include <asm/mcfclk.h>
21
22 /***************************************************************************/
23
24 DEFINE_CLK(pll, "pll.0", MCF_CLK);
25 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
26 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
27 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
28 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
29 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
30 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
31 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
32 DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
33
34 struct clk *mcf_clks[] = {
35 &clk_pll,
36 &clk_sys,
37 &clk_mcftmr0,
38 &clk_mcftmr1,
39 &clk_mcfuart0,
40 &clk_mcfuart1,
41 &clk_mcfqspi0,
42 &clk_mcfi2c0,
43 &clk_mcfi2c1,
44 NULL
45 };
46
47 /***************************************************************************/
48
49 #ifdef CONFIG_M5249C3
50
51 static struct resource m5249_smc91x_resources[] = {
52 {
53 .start = 0xe0000300,
54 .end = 0xe0000300 + 0x100,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = MCF_IRQ_GPIO6,
59 .end = MCF_IRQ_GPIO6,
60 .flags = IORESOURCE_IRQ,
61 },
62 };
63
64 static struct platform_device m5249_smc91x = {
65 .name = "smc91x",
66 .id = 0,
67 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
68 .resource = m5249_smc91x_resources,
69 };
70
71 #endif /* CONFIG_M5249C3 */
72
73 static struct platform_device *m5249_devices[] __initdata = {
74 #ifdef CONFIG_M5249C3
75 &m5249_smc91x,
76 #endif
77 };
78
79 /***************************************************************************/
80
m5249_qspi_init(void)81 static void __init m5249_qspi_init(void)
82 {
83 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
84 /* QSPI irq setup */
85 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
86 MCFSIM_QSPIICR);
87 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
88 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
89 }
90
91 /***************************************************************************/
92
m5249_i2c_init(void)93 static void __init m5249_i2c_init(void)
94 {
95 #if IS_ENABLED(CONFIG_I2C_IMX)
96 u32 r;
97
98 /* first I2C controller uses regular irq setup */
99 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
100 MCFSIM_I2CICR);
101 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
102
103 /* second I2C controller is completely different */
104 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
105 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
106 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
107 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
108 #endif /* CONFIG_I2C_IMX */
109 }
110
111 /***************************************************************************/
112
113 #ifdef CONFIG_M5249C3
114
m5249_smc91x_init(void)115 static void __init m5249_smc91x_init(void)
116 {
117 u32 gpio;
118
119 /* Set the GPIO line as interrupt source for smc91x device */
120 gpio = readl(MCFSIM2_GPIOINTENABLE);
121 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
122
123 gpio = readl(MCFINTC2_INTPRI5);
124 writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
125 }
126
127 #endif /* CONFIG_M5249C3 */
128
129 /***************************************************************************/
130
config_BSP(char * commandp,int size)131 void __init config_BSP(char *commandp, int size)
132 {
133 mach_sched_init = hw_timer_init;
134
135 #ifdef CONFIG_M5249C3
136 m5249_smc91x_init();
137 #endif
138 m5249_qspi_init();
139 m5249_i2c_init();
140 }
141
142 /***************************************************************************/
143
init_BSP(void)144 static int __init init_BSP(void)
145 {
146 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
147 return 0;
148 }
149
150 arch_initcall(init_BSP);
151
152 /***************************************************************************/
153
