1 /*
2 * Based on arch/arm/include/asm/cacheflush.h
3 *
4 * Copyright (C) 1999-2002 Russell King.
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef __ASM_CACHEFLUSH_H
20 #define __ASM_CACHEFLUSH_H
21
22 #include <linux/kgdb.h>
23 #include <linux/mm.h>
24
25 /*
26 * This flag is used to indicate that the page pointed to by a pte is clean
27 * and does not require cleaning before returning it to the user.
28 */
29 #define PG_dcache_clean PG_arch_1
30
31 /*
32 * MM Cache Management
33 * ===================
34 *
35 * The arch/arm64/mm/cache.S implements these methods.
36 *
37 * Start addresses are inclusive and end addresses are exclusive; start
38 * addresses should be rounded down, end addresses up.
39 *
40 * See Documentation/core-api/cachetlb.rst for more information. Please note that
41 * the implementation assumes non-aliasing VIPT D-cache and (aliasing)
42 * VIPT I-cache.
43 *
44 * flush_cache_mm(mm)
45 *
46 * Clean and invalidate all user space cache entries
47 * before a change of page tables.
48 *
49 * flush_icache_range(start, end)
50 *
51 * Ensure coherency between the I-cache and the D-cache in the
52 * region described by start, end.
53 * - start - virtual start address
54 * - end - virtual end address
55 *
56 * invalidate_icache_range(start, end)
57 *
58 * Invalidate the I-cache in the region described by start, end.
59 * - start - virtual start address
60 * - end - virtual end address
61 *
62 * __flush_cache_user_range(start, end)
63 *
64 * Ensure coherency between the I-cache and the D-cache in the
65 * region described by start, end.
66 * - start - virtual start address
67 * - end - virtual end address
68 *
69 * __flush_dcache_area(kaddr, size)
70 *
71 * Ensure that the data held in page is written back.
72 * - kaddr - page address
73 * - size - region size
74 */
75 extern void __flush_icache_range(unsigned long start, unsigned long end);
76 extern int invalidate_icache_range(unsigned long start, unsigned long end);
77 extern void __flush_dcache_area(void *addr, size_t len);
78 extern void __inval_dcache_area(void *addr, size_t len);
79 extern void __clean_dcache_area_poc(void *addr, size_t len);
80 extern void __clean_dcache_area_pop(void *addr, size_t len);
81 extern void __clean_dcache_area_pou(void *addr, size_t len);
82 extern long __flush_cache_user_range(unsigned long start, unsigned long end);
83 extern void sync_icache_aliases(void *kaddr, unsigned long len);
84
flush_icache_range(unsigned long start,unsigned long end)85 static inline void flush_icache_range(unsigned long start, unsigned long end)
86 {
87 __flush_icache_range(start, end);
88
89 /*
90 * IPI all online CPUs so that they undergo a context synchronization
91 * event and are forced to refetch the new instructions.
92 */
93 #ifdef CONFIG_KGDB
94 /*
95 * KGDB performs cache maintenance with interrupts disabled, so we
96 * will deadlock trying to IPI the secondary CPUs. In theory, we can
97 * set CACHE_FLUSH_IS_SAFE to 0 to avoid this known issue, but that
98 * just means that KGDB will elide the maintenance altogether! As it
99 * turns out, KGDB uses IPIs to round-up the secondary CPUs during
100 * the patching operation, so we don't need extra IPIs here anyway.
101 * In which case, add a KGDB-specific bodge and return early.
102 */
103 if (kgdb_connected && irqs_disabled())
104 return;
105 #endif
106 kick_all_cpus_sync();
107 }
108
flush_cache_mm(struct mm_struct * mm)109 static inline void flush_cache_mm(struct mm_struct *mm)
110 {
111 }
112
flush_cache_page(struct vm_area_struct * vma,unsigned long user_addr,unsigned long pfn)113 static inline void flush_cache_page(struct vm_area_struct *vma,
114 unsigned long user_addr, unsigned long pfn)
115 {
116 }
117
flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)118 static inline void flush_cache_range(struct vm_area_struct *vma,
119 unsigned long start, unsigned long end)
120 {
121 }
122
123 /*
124 * Cache maintenance functions used by the DMA API. No to be used directly.
125 */
126 extern void __dma_map_area(const void *, size_t, int);
127 extern void __dma_unmap_area(const void *, size_t, int);
128 extern void __dma_flush_area(const void *, size_t);
129
130 /*
131 * Copy user data from/to a page which is mapped into a different
132 * processes address space. Really, we want to allow our "user
133 * space" model to handle this.
134 */
135 extern void copy_to_user_page(struct vm_area_struct *, struct page *,
136 unsigned long, void *, const void *, unsigned long);
137 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
138 do { \
139 memcpy(dst, src, len); \
140 } while (0)
141
142 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
143
144 /*
145 * flush_dcache_page is used when the kernel has written to the page
146 * cache page at virtual address page->virtual.
147 *
148 * If this page isn't mapped (ie, page_mapping == NULL), or it might
149 * have userspace mappings, then we _must_ always clean + invalidate
150 * the dcache entries associated with the kernel mapping.
151 *
152 * Otherwise we can defer the operation, and clean the cache when we are
153 * about to change to user space. This is the same method as used on SPARC64.
154 * See update_mmu_cache for the user space part.
155 */
156 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
157 extern void flush_dcache_page(struct page *);
158
__flush_icache_all(void)159 static inline void __flush_icache_all(void)
160 {
161 if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
162 return;
163
164 asm("ic ialluis");
165 dsb(ish);
166 }
167
168 #define flush_dcache_mmap_lock(mapping) do { } while (0)
169 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
170
171 /*
172 * We don't appear to need to do anything here. In fact, if we did, we'd
173 * duplicate cache flushing elsewhere performed by flush_dcache_page().
174 */
175 #define flush_icache_page(vma,page) do { } while (0)
176
177 /*
178 * Not required on AArch64 (PIPT or VIPT non-aliasing D-cache).
179 */
flush_cache_vmap(unsigned long start,unsigned long end)180 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
181 {
182 }
183
flush_cache_vunmap(unsigned long start,unsigned long end)184 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
185 {
186 }
187
188 int set_memory_valid(unsigned long addr, int numpages, int enable);
189
190 #endif
191
