1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8996.h> 15#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 16#include <dt-bindings/clock/qcom,rpmcc.h> 17 18/ { 19 model = "Qualcomm Technologies, Inc. MSM8996"; 20 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 memory { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 mba_region: mba@91500000 { 40 reg = <0x0 0x91500000 0x0 0x200000>; 41 no-map; 42 }; 43 44 slpi_region: slpi@90b00000 { 45 reg = <0x0 0x90b00000 0x0 0xa00000>; 46 no-map; 47 }; 48 49 venus_region: venus@90400000 { 50 reg = <0x0 0x90400000 0x0 0x700000>; 51 no-map; 52 }; 53 54 adsp_region: adsp@8ea00000 { 55 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 56 no-map; 57 }; 58 59 mpss_region: mpss@88800000 { 60 reg = <0x0 0x88800000 0x0 0x6200000>; 61 no-map; 62 }; 63 64 smem_mem: smem-mem@86000000 { 65 reg = <0x0 0x86000000 0x0 0x200000>; 66 no-map; 67 }; 68 69 memory@85800000 { 70 reg = <0x0 0x85800000 0x0 0x800000>; 71 no-map; 72 }; 73 74 memory@86200000 { 75 reg = <0x0 0x86200000 0x0 0x2600000>; 76 no-map; 77 }; 78 79 rmtfs@86700000 { 80 compatible = "qcom,rmtfs-mem"; 81 82 size = <0x0 0x200000>; 83 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 84 no-map; 85 86 qcom,client-id = <1>; 87 qcom,vmid = <15>; 88 }; 89 }; 90 91 cpus { 92 #address-cells = <2>; 93 #size-cells = <0>; 94 95 CPU0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo"; 98 reg = <0x0 0x0>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 L2_0: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 }; 105 }; 106 107 CPU1: cpu@1 { 108 device_type = "cpu"; 109 compatible = "qcom,kryo"; 110 reg = <0x0 0x1>; 111 enable-method = "psci"; 112 next-level-cache = <&L2_0>; 113 }; 114 115 CPU2: cpu@100 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo"; 118 reg = <0x0 0x100>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_1>; 121 L2_1: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 }; 125 }; 126 127 CPU3: cpu@101 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo"; 130 reg = <0x0 0x101>; 131 enable-method = "psci"; 132 next-level-cache = <&L2_1>; 133 }; 134 135 cpu-map { 136 cluster0 { 137 core0 { 138 cpu = <&CPU0>; 139 }; 140 141 core1 { 142 cpu = <&CPU1>; 143 }; 144 }; 145 146 cluster1 { 147 core0 { 148 cpu = <&CPU2>; 149 }; 150 151 core1 { 152 cpu = <&CPU3>; 153 }; 154 }; 155 }; 156 }; 157 158 thermal-zones { 159 cpu-thermal0 { 160 polling-delay-passive = <250>; 161 polling-delay = <1000>; 162 163 thermal-sensors = <&tsens0 3>; 164 165 trips { 166 cpu_alert0: trip0 { 167 temperature = <75000>; 168 hysteresis = <2000>; 169 type = "passive"; 170 }; 171 172 cpu_crit0: trip1 { 173 temperature = <110000>; 174 hysteresis = <2000>; 175 type = "critical"; 176 }; 177 }; 178 }; 179 180 cpu-thermal1 { 181 polling-delay-passive = <250>; 182 polling-delay = <1000>; 183 184 thermal-sensors = <&tsens0 5>; 185 186 trips { 187 cpu_alert1: trip0 { 188 temperature = <75000>; 189 hysteresis = <2000>; 190 type = "passive"; 191 }; 192 193 cpu_crit1: trip1 { 194 temperature = <110000>; 195 hysteresis = <2000>; 196 type = "critical"; 197 }; 198 }; 199 }; 200 201 cpu-thermal2 { 202 polling-delay-passive = <250>; 203 polling-delay = <1000>; 204 205 thermal-sensors = <&tsens0 8>; 206 207 trips { 208 cpu_alert2: trip0 { 209 temperature = <75000>; 210 hysteresis = <2000>; 211 type = "passive"; 212 }; 213 214 cpu_crit2: trip1 { 215 temperature = <110000>; 216 hysteresis = <2000>; 217 type = "critical"; 218 }; 219 }; 220 }; 221 222 cpu-thermal3 { 223 polling-delay-passive = <250>; 224 polling-delay = <1000>; 225 226 thermal-sensors = <&tsens0 10>; 227 228 trips { 229 cpu_alert3: trip0 { 230 temperature = <75000>; 231 hysteresis = <2000>; 232 type = "passive"; 233 }; 234 235 cpu_crit3: trip1 { 236 temperature = <110000>; 237 hysteresis = <2000>; 238 type = "critical"; 239 }; 240 }; 241 }; 242 }; 243 244 timer { 245 compatible = "arm,armv8-timer"; 246 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 247 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 248 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 249 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 250 }; 251 252 clocks { 253 xo_board: xo_board { 254 compatible = "fixed-clock"; 255 #clock-cells = <0>; 256 clock-frequency = <19200000>; 257 clock-output-names = "xo_board"; 258 }; 259 260 sleep_clk: sleep_clk { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 clock-frequency = <32764>; 264 clock-output-names = "sleep_clk"; 265 }; 266 }; 267 268 psci { 269 compatible = "arm,psci-1.0"; 270 method = "smc"; 271 }; 272 273 firmware { 274 scm { 275 compatible = "qcom,scm-msm8996"; 276 277 qcom,dload-mode = <&tcsr 0x13000>; 278 }; 279 }; 280 281 tcsr_mutex: hwlock { 282 compatible = "qcom,tcsr-mutex"; 283 syscon = <&tcsr_mutex_regs 0 0x1000>; 284 #hwlock-cells = <1>; 285 }; 286 287 smem { 288 compatible = "qcom,smem"; 289 memory-region = <&smem_mem>; 290 hwlocks = <&tcsr_mutex 3>; 291 }; 292 293 rpm-glink { 294 compatible = "qcom,glink-rpm"; 295 296 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 297 298 qcom,rpm-msg-ram = <&rpm_msg_ram>; 299 300 mboxes = <&apcs_glb 0>; 301 302 rpm_requests { 303 compatible = "qcom,rpm-msm8996"; 304 qcom,glink-channels = "rpm_requests"; 305 306 rpmcc: qcom,rpmcc { 307 compatible = "qcom,rpmcc-msm8996"; 308 #clock-cells = <1>; 309 }; 310 311 pm8994-regulators { 312 compatible = "qcom,rpm-pm8994-regulators"; 313 314 pm8994_s1: s1 {}; 315 pm8994_s2: s2 {}; 316 pm8994_s3: s3 {}; 317 pm8994_s4: s4 {}; 318 pm8994_s5: s5 {}; 319 pm8994_s6: s6 {}; 320 pm8994_s7: s7 {}; 321 pm8994_s8: s8 {}; 322 pm8994_s9: s9 {}; 323 pm8994_s10: s10 {}; 324 pm8994_s11: s11 {}; 325 pm8994_s12: s12 {}; 326 327 pm8994_l1: l1 {}; 328 pm8994_l2: l2 {}; 329 pm8994_l3: l3 {}; 330 pm8994_l4: l4 {}; 331 pm8994_l5: l5 {}; 332 pm8994_l6: l6 {}; 333 pm8994_l7: l7 {}; 334 pm8994_l8: l8 {}; 335 pm8994_l9: l9 {}; 336 pm8994_l10: l10 {}; 337 pm8994_l11: l11 {}; 338 pm8994_l12: l12 {}; 339 pm8994_l13: l13 {}; 340 pm8994_l14: l14 {}; 341 pm8994_l15: l15 {}; 342 pm8994_l16: l16 {}; 343 pm8994_l17: l17 {}; 344 pm8994_l18: l18 {}; 345 pm8994_l19: l19 {}; 346 pm8994_l20: l20 {}; 347 pm8994_l21: l21 {}; 348 pm8994_l22: l22 {}; 349 pm8994_l23: l23 {}; 350 pm8994_l24: l24 {}; 351 pm8994_l25: l25 {}; 352 pm8994_l26: l26 {}; 353 pm8994_l27: l27 {}; 354 pm8994_l28: l28 {}; 355 pm8994_l29: l29 {}; 356 pm8994_l30: l30 {}; 357 pm8994_l31: l31 {}; 358 pm8994_l32: l32 {}; 359 }; 360 361 }; 362 }; 363 364 soc: soc { 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges = <0 0 0 0xffffffff>; 368 compatible = "simple-bus"; 369 370 rpm_msg_ram: memory@68000 { 371 compatible = "qcom,rpm-msg-ram"; 372 reg = <0x68000 0x6000>; 373 }; 374 375 tcsr_mutex_regs: syscon@740000 { 376 compatible = "syscon"; 377 reg = <0x740000 0x20000>; 378 }; 379 380 tsens0: thermal-sensor@4a9000 { 381 compatible = "qcom,msm8996-tsens"; 382 reg = <0x4a9000 0x1000>, /* TM */ 383 <0x4a8000 0x1000>; /* SROT */ 384 #qcom,sensors = <13>; 385 #thermal-sensor-cells = <1>; 386 }; 387 388 tsens1: thermal-sensor@4ad000 { 389 compatible = "qcom,msm8996-tsens"; 390 reg = <0x4ad000 0x1000>, /* TM */ 391 <0x4ac000 0x1000>; /* SROT */ 392 #qcom,sensors = <8>; 393 #thermal-sensor-cells = <1>; 394 }; 395 396 tcsr: syscon@7a0000 { 397 compatible = "qcom,tcsr-msm8996", "syscon"; 398 reg = <0x7a0000 0x18000>; 399 }; 400 401 intc: interrupt-controller@9bc0000 { 402 compatible = "arm,gic-v3"; 403 #interrupt-cells = <3>; 404 interrupt-controller; 405 #redistributor-regions = <1>; 406 redistributor-stride = <0x0 0x40000>; 407 reg = <0x09bc0000 0x10000>, 408 <0x09c00000 0x100000>; 409 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 apcs: syscon@9820000 { 413 compatible = "syscon"; 414 reg = <0x9820000 0x1000>; 415 }; 416 417 apcs_glb: mailbox@9820000 { 418 compatible = "qcom,msm8996-apcs-hmss-global"; 419 reg = <0x9820000 0x1000>; 420 421 #mbox-cells = <1>; 422 }; 423 424 gcc: clock-controller@300000 { 425 compatible = "qcom,gcc-msm8996"; 426 #clock-cells = <1>; 427 #reset-cells = <1>; 428 #power-domain-cells = <1>; 429 reg = <0x300000 0x90000>; 430 }; 431 432 kryocc: clock-controller@6400000 { 433 compatible = "qcom,apcc-msm8996"; 434 reg = <0x6400000 0x90000>; 435 #clock-cells = <1>; 436 }; 437 438 blsp1_uart1: serial@7570000 { 439 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 440 reg = <0x07570000 0x1000>; 441 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 443 <&gcc GCC_BLSP1_AHB_CLK>; 444 clock-names = "core", "iface"; 445 status = "disabled"; 446 }; 447 448 blsp1_spi0: spi@7575000 { 449 compatible = "qcom,spi-qup-v2.2.1"; 450 reg = <0x07575000 0x600>; 451 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 453 <&gcc GCC_BLSP1_AHB_CLK>; 454 clock-names = "core", "iface"; 455 pinctrl-names = "default", "sleep"; 456 pinctrl-0 = <&blsp1_spi0_default>; 457 pinctrl-1 = <&blsp1_spi0_sleep>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 blsp2_i2c0: i2c@75b5000 { 464 compatible = "qcom,i2c-qup-v2.2.1"; 465 reg = <0x075b5000 0x1000>; 466 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 468 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 469 clock-names = "iface", "core"; 470 pinctrl-names = "default", "sleep"; 471 pinctrl-0 = <&blsp2_i2c0_default>; 472 pinctrl-1 = <&blsp2_i2c0_sleep>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 blsp2_uart1: serial@75b0000 { 479 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 480 reg = <0x75b0000 0x1000>; 481 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 483 <&gcc GCC_BLSP2_AHB_CLK>; 484 clock-names = "core", "iface"; 485 status = "disabled"; 486 }; 487 488 blsp2_i2c1: i2c@75b6000 { 489 compatible = "qcom,i2c-qup-v2.2.1"; 490 reg = <0x075b6000 0x1000>; 491 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 493 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 494 clock-names = "iface", "core"; 495 pinctrl-names = "default", "sleep"; 496 pinctrl-0 = <&blsp2_i2c1_default>; 497 pinctrl-1 = <&blsp2_i2c1_sleep>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 status = "disabled"; 501 }; 502 503 blsp2_uart2: serial@75b1000 { 504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 505 reg = <0x075b1000 0x1000>; 506 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 508 <&gcc GCC_BLSP2_AHB_CLK>; 509 clock-names = "core", "iface"; 510 status = "disabled"; 511 }; 512 513 blsp1_i2c2: i2c@7577000 { 514 compatible = "qcom,i2c-qup-v2.2.1"; 515 reg = <0x07577000 0x1000>; 516 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 518 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 519 clock-names = "iface", "core"; 520 pinctrl-names = "default", "sleep"; 521 pinctrl-0 = <&blsp1_i2c2_default>; 522 pinctrl-1 = <&blsp1_i2c2_sleep>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 }; 527 528 blsp2_spi5: spi@75ba000{ 529 compatible = "qcom,spi-qup-v2.2.1"; 530 reg = <0x075ba000 0x600>; 531 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 533 <&gcc GCC_BLSP2_AHB_CLK>; 534 clock-names = "core", "iface"; 535 pinctrl-names = "default", "sleep"; 536 pinctrl-0 = <&blsp2_spi5_default>; 537 pinctrl-1 = <&blsp2_spi5_sleep>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 sdhc2: sdhci@74a4900 { 544 status = "disabled"; 545 compatible = "qcom,sdhci-msm-v4"; 546 reg = <0x74a4900 0x314>, <0x74a4000 0x800>; 547 reg-names = "hc_mem", "core_mem"; 548 549 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 550 <0 221 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "hc_irq", "pwr_irq"; 552 553 clock-names = "iface", "core", "xo"; 554 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 555 <&gcc GCC_SDCC2_APPS_CLK>, 556 <&xo_board>; 557 bus-width = <4>; 558 }; 559 560 msmgpio: pinctrl@1010000 { 561 compatible = "qcom,msm8996-pinctrl"; 562 reg = <0x01010000 0x300000>; 563 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 564 gpio-controller; 565 #gpio-cells = <2>; 566 interrupt-controller; 567 #interrupt-cells = <2>; 568 }; 569 570 timer@9840000 { 571 #address-cells = <1>; 572 #size-cells = <1>; 573 ranges; 574 compatible = "arm,armv7-timer-mem"; 575 reg = <0x09840000 0x1000>; 576 clock-frequency = <19200000>; 577 578 frame@9850000 { 579 frame-number = <0>; 580 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 582 reg = <0x09850000 0x1000>, 583 <0x09860000 0x1000>; 584 }; 585 586 frame@9870000 { 587 frame-number = <1>; 588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 589 reg = <0x09870000 0x1000>; 590 status = "disabled"; 591 }; 592 593 frame@9880000 { 594 frame-number = <2>; 595 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 596 reg = <0x09880000 0x1000>; 597 status = "disabled"; 598 }; 599 600 frame@9890000 { 601 frame-number = <3>; 602 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 603 reg = <0x09890000 0x1000>; 604 status = "disabled"; 605 }; 606 607 frame@98a0000 { 608 frame-number = <4>; 609 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 610 reg = <0x098a0000 0x1000>; 611 status = "disabled"; 612 }; 613 614 frame@98b0000 { 615 frame-number = <5>; 616 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 617 reg = <0x098b0000 0x1000>; 618 status = "disabled"; 619 }; 620 621 frame@98c0000 { 622 frame-number = <6>; 623 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 624 reg = <0x098c0000 0x1000>; 625 status = "disabled"; 626 }; 627 }; 628 629 spmi_bus: qcom,spmi@400f000 { 630 compatible = "qcom,spmi-pmic-arb"; 631 reg = <0x400f000 0x1000>, 632 <0x4400000 0x800000>, 633 <0x4c00000 0x800000>, 634 <0x5800000 0x200000>, 635 <0x400a000 0x002100>; 636 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 637 interrupt-names = "periph_irq"; 638 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 639 qcom,ee = <0>; 640 qcom,channel = <0>; 641 #address-cells = <2>; 642 #size-cells = <0>; 643 interrupt-controller; 644 #interrupt-cells = <4>; 645 }; 646 647 ufsphy: phy@627000 { 648 compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; 649 reg = <0x627000 0xda8>; 650 reg-names = "phy_mem"; 651 #phy-cells = <0>; 652 653 vdda-phy-supply = <&pm8994_l28>; 654 vdda-pll-supply = <&pm8994_l12>; 655 656 vdda-phy-max-microamp = <18380>; 657 vdda-pll-max-microamp = <9440>; 658 659 vddp-ref-clk-supply = <&pm8994_l25>; 660 vddp-ref-clk-max-microamp = <100>; 661 vddp-ref-clk-always-on; 662 663 clock-names = "ref_clk_src", "ref_clk"; 664 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 665 <&gcc GCC_UFS_CLKREF_CLK>; 666 status = "disabled"; 667 }; 668 669 ufshc@624000 { 670 compatible = "qcom,ufshc"; 671 reg = <0x624000 0x2500>; 672 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 673 674 phys = <&ufsphy>; 675 phy-names = "ufsphy"; 676 677 vcc-supply = <&pm8994_l20>; 678 vccq-supply = <&pm8994_l25>; 679 vccq2-supply = <&pm8994_s4>; 680 681 vcc-max-microamp = <600000>; 682 vccq-max-microamp = <450000>; 683 vccq2-max-microamp = <450000>; 684 685 power-domains = <&gcc UFS_GDSC>; 686 687 clock-names = 688 "core_clk_src", 689 "core_clk", 690 "bus_clk", 691 "bus_aggr_clk", 692 "iface_clk", 693 "core_clk_unipro_src", 694 "core_clk_unipro", 695 "core_clk_ice", 696 "ref_clk", 697 "tx_lane0_sync_clk", 698 "rx_lane0_sync_clk"; 699 clocks = 700 <&gcc UFS_AXI_CLK_SRC>, 701 <&gcc GCC_UFS_AXI_CLK>, 702 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 703 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 704 <&gcc GCC_UFS_AHB_CLK>, 705 <&gcc UFS_ICE_CORE_CLK_SRC>, 706 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 707 <&gcc GCC_UFS_ICE_CORE_CLK>, 708 <&rpmcc RPM_SMD_LN_BB_CLK>, 709 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 710 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 711 freq-table-hz = 712 <100000000 200000000>, 713 <0 0>, 714 <0 0>, 715 <0 0>, 716 <0 0>, 717 <150000000 300000000>, 718 <0 0>, 719 <0 0>, 720 <0 0>, 721 <0 0>, 722 <0 0>; 723 724 lanes-per-direction = <1>; 725 status = "disabled"; 726 727 ufs_variant { 728 compatible = "qcom,ufs_variant"; 729 }; 730 }; 731 732 mmcc: clock-controller@8c0000 { 733 compatible = "qcom,mmcc-msm8996"; 734 #clock-cells = <1>; 735 #reset-cells = <1>; 736 #power-domain-cells = <1>; 737 reg = <0x8c0000 0x40000>; 738 assigned-clocks = <&mmcc MMPLL9_PLL>, 739 <&mmcc MMPLL1_PLL>, 740 <&mmcc MMPLL3_PLL>, 741 <&mmcc MMPLL4_PLL>, 742 <&mmcc MMPLL5_PLL>; 743 assigned-clock-rates = <624000000>, 744 <810000000>, 745 <980000000>, 746 <960000000>, 747 <825000000>; 748 }; 749 750 qfprom@74000 { 751 compatible = "qcom,qfprom"; 752 reg = <0x74000 0x8ff>; 753 #address-cells = <1>; 754 #size-cells = <1>; 755 756 qusb2p_hstx_trim: hstx_trim@24e { 757 reg = <0x24e 0x2>; 758 bits = <5 4>; 759 }; 760 761 qusb2s_hstx_trim: hstx_trim@24f { 762 reg = <0x24f 0x1>; 763 bits = <1 4>; 764 }; 765 }; 766 767 phy@34000 { 768 compatible = "qcom,msm8996-qmp-pcie-phy"; 769 reg = <0x34000 0x488>; 770 #clock-cells = <1>; 771 #address-cells = <1>; 772 #size-cells = <1>; 773 ranges; 774 775 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 776 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 777 <&gcc GCC_PCIE_CLKREF_CLK>; 778 clock-names = "aux", "cfg_ahb", "ref"; 779 780 vdda-phy-supply = <&pm8994_l28>; 781 vdda-pll-supply = <&pm8994_l12>; 782 783 resets = <&gcc GCC_PCIE_PHY_BCR>, 784 <&gcc GCC_PCIE_PHY_COM_BCR>, 785 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 786 reset-names = "phy", "common", "cfg"; 787 status = "disabled"; 788 789 pciephy_0: lane@35000 { 790 reg = <0x035000 0x130>, 791 <0x035200 0x200>, 792 <0x035400 0x1dc>; 793 #phy-cells = <0>; 794 795 clock-output-names = "pcie_0_pipe_clk_src"; 796 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 797 clock-names = "pipe0"; 798 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 799 reset-names = "lane0"; 800 }; 801 802 pciephy_1: lane@36000 { 803 reg = <0x036000 0x130>, 804 <0x036200 0x200>, 805 <0x036400 0x1dc>; 806 #phy-cells = <0>; 807 808 clock-output-names = "pcie_1_pipe_clk_src"; 809 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 810 clock-names = "pipe1"; 811 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 812 reset-names = "lane1"; 813 }; 814 815 pciephy_2: lane@37000 { 816 reg = <0x037000 0x130>, 817 <0x037200 0x200>, 818 <0x037400 0x1dc>; 819 #phy-cells = <0>; 820 821 clock-output-names = "pcie_2_pipe_clk_src"; 822 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 823 clock-names = "pipe2"; 824 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 825 reset-names = "lane2"; 826 }; 827 }; 828 829 phy@7410000 { 830 compatible = "qcom,msm8996-qmp-usb3-phy"; 831 reg = <0x7410000 0x1c4>; 832 #clock-cells = <1>; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 ranges; 836 837 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 838 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 839 <&gcc GCC_USB3_CLKREF_CLK>; 840 clock-names = "aux", "cfg_ahb", "ref"; 841 842 vdda-phy-supply = <&pm8994_l28>; 843 vdda-pll-supply = <&pm8994_l12>; 844 845 resets = <&gcc GCC_USB3_PHY_BCR>, 846 <&gcc GCC_USB3PHY_PHY_BCR>; 847 reset-names = "phy", "common"; 848 status = "disabled"; 849 850 ssusb_phy_0: lane@7410200 { 851 reg = <0x7410200 0x200>, 852 <0x7410400 0x130>, 853 <0x7410600 0x1a8>; 854 #phy-cells = <0>; 855 856 clock-output-names = "usb3_phy_pipe_clk_src"; 857 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 858 clock-names = "pipe0"; 859 }; 860 }; 861 862 hsusb_phy1: phy@7411000 { 863 compatible = "qcom,msm8996-qusb2-phy"; 864 reg = <0x7411000 0x180>; 865 #phy-cells = <0>; 866 867 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 868 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 869 clock-names = "cfg_ahb", "ref"; 870 871 vdda-pll-supply = <&pm8994_l12>; 872 vdda-phy-dpdm-supply = <&pm8994_l24>; 873 874 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 875 nvmem-cells = <&qusb2p_hstx_trim>; 876 status = "disabled"; 877 }; 878 879 hsusb_phy2: phy@7412000 { 880 compatible = "qcom,msm8996-qusb2-phy"; 881 reg = <0x7412000 0x180>; 882 #phy-cells = <0>; 883 884 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 885 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 886 clock-names = "cfg_ahb", "ref"; 887 888 vdda-pll-supply = <&pm8994_l12>; 889 vdda-phy-dpdm-supply = <&pm8994_l24>; 890 891 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 892 nvmem-cells = <&qusb2s_hstx_trim>; 893 status = "disabled"; 894 }; 895 896 usb2: usb@7600000 { 897 compatible = "qcom,dwc3"; 898 #address-cells = <1>; 899 #size-cells = <1>; 900 ranges; 901 902 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 903 <&gcc GCC_USB20_MASTER_CLK>, 904 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 905 <&gcc GCC_USB20_SLEEP_CLK>, 906 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 907 908 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 909 <&gcc GCC_USB20_MASTER_CLK>; 910 assigned-clock-rates = <19200000>, <60000000>; 911 912 power-domains = <&gcc USB30_GDSC>; 913 status = "disabled"; 914 915 dwc3@7600000 { 916 compatible = "snps,dwc3"; 917 reg = <0x7600000 0xcc00>; 918 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 919 phys = <&hsusb_phy2>; 920 phy-names = "usb2-phy"; 921 }; 922 }; 923 924 usb3: usb@6a00000 { 925 compatible = "qcom,dwc3"; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 ranges; 929 930 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 931 <&gcc GCC_USB30_MASTER_CLK>, 932 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 933 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 934 <&gcc GCC_USB30_SLEEP_CLK>, 935 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 936 937 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 938 <&gcc GCC_USB30_MASTER_CLK>; 939 assigned-clock-rates = <19200000>, <120000000>; 940 941 power-domains = <&gcc USB30_GDSC>; 942 status = "disabled"; 943 944 dwc3@6a00000 { 945 compatible = "snps,dwc3"; 946 reg = <0x6a00000 0xcc00>; 947 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 948 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 949 phy-names = "usb2-phy", "usb3-phy"; 950 }; 951 }; 952 953 agnoc@0 { 954 power-domains = <&gcc AGGRE0_NOC_GDSC>; 955 compatible = "simple-pm-bus"; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 ranges; 959 960 pcie0: pcie@600000 { 961 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 962 status = "disabled"; 963 power-domains = <&gcc PCIE0_GDSC>; 964 bus-range = <0x00 0xff>; 965 num-lanes = <1>; 966 967 reg = <0x00600000 0x2000>, 968 <0x0c000000 0xf1d>, 969 <0x0c000f20 0xa8>, 970 <0x0c100000 0x100000>; 971 reg-names = "parf", "dbi", "elbi","config"; 972 973 phys = <&pciephy_0>; 974 phy-names = "pciephy"; 975 976 #address-cells = <3>; 977 #size-cells = <2>; 978 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 979 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 980 981 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-names = "msi"; 983 #interrupt-cells = <1>; 984 interrupt-map-mask = <0 0 0 0x7>; 985 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 986 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 987 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 988 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 989 990 pinctrl-names = "default", "sleep"; 991 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 992 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 993 994 995 vdda-supply = <&pm8994_l28>; 996 997 linux,pci-domain = <0>; 998 999 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1000 <&gcc GCC_PCIE_0_AUX_CLK>, 1001 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1002 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1003 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1004 1005 clock-names = "pipe", 1006 "aux", 1007 "cfg", 1008 "bus_master", 1009 "bus_slave"; 1010 1011 }; 1012 1013 pcie1: pcie@608000 { 1014 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1015 power-domains = <&gcc PCIE1_GDSC>; 1016 bus-range = <0x00 0xff>; 1017 num-lanes = <1>; 1018 1019 status = "disabled"; 1020 1021 reg = <0x00608000 0x2000>, 1022 <0x0d000000 0xf1d>, 1023 <0x0d000f20 0xa8>, 1024 <0x0d100000 0x100000>; 1025 1026 reg-names = "parf", "dbi", "elbi","config"; 1027 1028 phys = <&pciephy_1>; 1029 phy-names = "pciephy"; 1030 1031 #address-cells = <3>; 1032 #size-cells = <2>; 1033 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1034 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1035 1036 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1037 interrupt-names = "msi"; 1038 #interrupt-cells = <1>; 1039 interrupt-map-mask = <0 0 0 0x7>; 1040 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1041 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1042 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1043 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1044 1045 pinctrl-names = "default", "sleep"; 1046 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 1047 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 1048 1049 1050 vdda-supply = <&pm8994_l28>; 1051 linux,pci-domain = <1>; 1052 1053 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1054 <&gcc GCC_PCIE_1_AUX_CLK>, 1055 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1056 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1057 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1058 1059 clock-names = "pipe", 1060 "aux", 1061 "cfg", 1062 "bus_master", 1063 "bus_slave"; 1064 }; 1065 1066 pcie2: pcie@610000 { 1067 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1068 power-domains = <&gcc PCIE2_GDSC>; 1069 bus-range = <0x00 0xff>; 1070 num-lanes = <1>; 1071 status = "disabled"; 1072 reg = <0x00610000 0x2000>, 1073 <0x0e000000 0xf1d>, 1074 <0x0e000f20 0xa8>, 1075 <0x0e100000 0x100000>; 1076 1077 reg-names = "parf", "dbi", "elbi","config"; 1078 1079 phys = <&pciephy_2>; 1080 phy-names = "pciephy"; 1081 1082 #address-cells = <3>; 1083 #size-cells = <2>; 1084 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1085 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1086 1087 device_type = "pci"; 1088 1089 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1090 interrupt-names = "msi"; 1091 #interrupt-cells = <1>; 1092 interrupt-map-mask = <0 0 0 0x7>; 1093 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1094 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1095 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1096 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1097 1098 pinctrl-names = "default", "sleep"; 1099 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 1100 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 1101 1102 vdda-supply = <&pm8994_l28>; 1103 1104 linux,pci-domain = <2>; 1105 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1106 <&gcc GCC_PCIE_2_AUX_CLK>, 1107 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1108 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1109 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1110 1111 clock-names = "pipe", 1112 "aux", 1113 "cfg", 1114 "bus_master", 1115 "bus_slave"; 1116 }; 1117 }; 1118 }; 1119 1120 adsp-pil { 1121 compatible = "qcom,msm8996-adsp-pil"; 1122 1123 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 1124 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1125 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1126 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1127 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1128 interrupt-names = "wdog", "fatal", "ready", 1129 "handover", "stop-ack"; 1130 1131 clocks = <&xo_board>; 1132 clock-names = "xo"; 1133 1134 memory-region = <&adsp_region>; 1135 1136 qcom,smem-states = <&adsp_smp2p_out 0>; 1137 qcom,smem-state-names = "stop"; 1138 1139 smd-edge { 1140 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1141 1142 label = "lpass"; 1143 qcom,ipc = <&apcs 16 8>; 1144 qcom,smd-edge = <1>; 1145 qcom,remote-pid = <2>; 1146 }; 1147 }; 1148 1149 adsp-smp2p { 1150 compatible = "qcom,smp2p"; 1151 qcom,smem = <443>, <429>; 1152 1153 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 1154 1155 qcom,ipc = <&apcs 16 10>; 1156 1157 qcom,local-pid = <0>; 1158 qcom,remote-pid = <2>; 1159 1160 adsp_smp2p_out: master-kernel { 1161 qcom,entry-name = "master-kernel"; 1162 #qcom,smem-state-cells = <1>; 1163 }; 1164 1165 adsp_smp2p_in: slave-kernel { 1166 qcom,entry-name = "slave-kernel"; 1167 1168 interrupt-controller; 1169 #interrupt-cells = <2>; 1170 }; 1171 }; 1172 1173 modem-smp2p { 1174 compatible = "qcom,smp2p"; 1175 qcom,smem = <435>, <428>; 1176 1177 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1178 1179 qcom,ipc = <&apcs 16 14>; 1180 1181 qcom,local-pid = <0>; 1182 qcom,remote-pid = <1>; 1183 1184 modem_smp2p_out: master-kernel { 1185 qcom,entry-name = "master-kernel"; 1186 #qcom,smem-state-cells = <1>; 1187 }; 1188 1189 modem_smp2p_in: slave-kernel { 1190 qcom,entry-name = "slave-kernel"; 1191 1192 interrupt-controller; 1193 #interrupt-cells = <2>; 1194 }; 1195 }; 1196 1197 smp2p-slpi { 1198 compatible = "qcom,smp2p"; 1199 qcom,smem = <481>, <430>; 1200 1201 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 1202 1203 qcom,ipc = <&apcs 16 26>; 1204 1205 qcom,local-pid = <0>; 1206 qcom,remote-pid = <3>; 1207 1208 slpi_smp2p_in: slave-kernel { 1209 qcom,entry-name = "slave-kernel"; 1210 interrupt-controller; 1211 #interrupt-cells = <2>; 1212 }; 1213 1214 slpi_smp2p_out: master-kernel { 1215 qcom,entry-name = "master-kernel"; 1216 #qcom,smem-state-cells = <1>; 1217 }; 1218 }; 1219 1220}; 1221#include "msm8996-pins.dtsi" 1222
