1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (C) 2013 Samsung Electronics Co., Ltd.
4 // Tomasz Figa <t.figa@samsung.com>
5 // Copyright (C) 2008 Openmoko, Inc.
6 // Copyright (C) 2004-2008 Simtec Electronics
7 // Ben Dooks <ben@simtec.co.uk>
8 // http://armlinux.simtec.co.uk/
9 //
10 // Samsung common power management (suspend to RAM) debug support
11
12 #include <linux/serial_core.h>
13 #include <linux/serial_s3c.h>
14 #include <linux/io.h>
15
16 #include <asm/mach/map.h>
17
18 #include <plat/cpu.h>
19 #include <plat/pm-common.h>
20
21 #ifdef CONFIG_SAMSUNG_ATAGS
22 #include <plat/pm.h>
23 #include <mach/pm-core.h>
24 #else
s3c_pm_debug_init_uart(void)25 static inline void s3c_pm_debug_init_uart(void) {}
s3c_pm_arch_update_uart(void __iomem * regs,struct pm_uart_save * save)26 static inline void s3c_pm_arch_update_uart(void __iomem *regs,
27 struct pm_uart_save *save) {}
28 #endif
29
30 static struct pm_uart_save uart_save;
31
32 extern void printascii(const char *);
33
s3c_pm_dbg(const char * fmt,...)34 void s3c_pm_dbg(const char *fmt, ...)
35 {
36 va_list va;
37 char buff[256];
38
39 va_start(va, fmt);
40 vsnprintf(buff, sizeof(buff), fmt, va);
41 va_end(va);
42
43 printascii(buff);
44 }
45
s3c_pm_debug_init(void)46 void s3c_pm_debug_init(void)
47 {
48 /* restart uart clocks so we can use them to output */
49 s3c_pm_debug_init_uart();
50 }
51
s3c_pm_uart_base(void)52 static inline void __iomem *s3c_pm_uart_base(void)
53 {
54 unsigned long paddr;
55 unsigned long vaddr;
56
57 debug_ll_addr(&paddr, &vaddr);
58
59 return (void __iomem *)vaddr;
60 }
61
s3c_pm_save_uarts(void)62 void s3c_pm_save_uarts(void)
63 {
64 void __iomem *regs = s3c_pm_uart_base();
65 struct pm_uart_save *save = &uart_save;
66
67 save->ulcon = __raw_readl(regs + S3C2410_ULCON);
68 save->ucon = __raw_readl(regs + S3C2410_UCON);
69 save->ufcon = __raw_readl(regs + S3C2410_UFCON);
70 save->umcon = __raw_readl(regs + S3C2410_UMCON);
71 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
72
73 if (!soc_is_s3c2410())
74 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
75
76 S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
77 regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
78 }
79
s3c_pm_restore_uarts(void)80 void s3c_pm_restore_uarts(void)
81 {
82 void __iomem *regs = s3c_pm_uart_base();
83 struct pm_uart_save *save = &uart_save;
84
85 s3c_pm_arch_update_uart(regs, save);
86
87 __raw_writel(save->ulcon, regs + S3C2410_ULCON);
88 __raw_writel(save->ucon, regs + S3C2410_UCON);
89 __raw_writel(save->ufcon, regs + S3C2410_UFCON);
90 __raw_writel(save->umcon, regs + S3C2410_UMCON);
91 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
92
93 if (!soc_is_s3c2410())
94 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
95 }
96
