1 /*
2 * RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7
3 * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
4 *
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/io.h>
13 #include <linux/regmap.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_platform.h>
18
19 #define SIRFSOC_CPUIOBRG_CTRL 0x00
20 #define SIRFSOC_CPUIOBRG_WRBE 0x04
21 #define SIRFSOC_CPUIOBRG_ADDR 0x08
22 #define SIRFSOC_CPUIOBRG_DATA 0x0c
23
24 /*
25 * suspend asm codes will access this address to make system deepsleep
26 * after DRAM becomes self-refresh
27 */
28 void __iomem *sirfsoc_rtciobrg_base;
29 static DEFINE_SPINLOCK(rtciobrg_lock);
30
31 /*
32 * symbols without lock are only used by suspend asm codes
33 * and these symbols are not exported too
34 */
sirfsoc_rtc_iobrg_wait_sync(void)35 void sirfsoc_rtc_iobrg_wait_sync(void)
36 {
37 while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL))
38 cpu_relax();
39 }
40
sirfsoc_rtc_iobrg_besyncing(void)41 void sirfsoc_rtc_iobrg_besyncing(void)
42 {
43 unsigned long flags;
44
45 spin_lock_irqsave(&rtciobrg_lock, flags);
46
47 sirfsoc_rtc_iobrg_wait_sync();
48
49 spin_unlock_irqrestore(&rtciobrg_lock, flags);
50 }
51 EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing);
52
__sirfsoc_rtc_iobrg_readl(u32 addr)53 u32 __sirfsoc_rtc_iobrg_readl(u32 addr)
54 {
55 sirfsoc_rtc_iobrg_wait_sync();
56
57 writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);
58 writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);
59 writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);
60
61 sirfsoc_rtc_iobrg_wait_sync();
62
63 return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);
64 }
65
sirfsoc_rtc_iobrg_readl(u32 addr)66 u32 sirfsoc_rtc_iobrg_readl(u32 addr)
67 {
68 unsigned long flags, val;
69
70 /* TODO: add hwspinlock to sync with M3 */
71 spin_lock_irqsave(&rtciobrg_lock, flags);
72
73 val = __sirfsoc_rtc_iobrg_readl(addr);
74
75 spin_unlock_irqrestore(&rtciobrg_lock, flags);
76
77 return val;
78 }
79 EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl);
80
sirfsoc_rtc_iobrg_pre_writel(u32 val,u32 addr)81 void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr)
82 {
83 sirfsoc_rtc_iobrg_wait_sync();
84
85 writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);
86 writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);
87
88 writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);
89 }
90
sirfsoc_rtc_iobrg_writel(u32 val,u32 addr)91 void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
92 {
93 unsigned long flags;
94
95 /* TODO: add hwspinlock to sync with M3 */
96 spin_lock_irqsave(&rtciobrg_lock, flags);
97
98 sirfsoc_rtc_iobrg_pre_writel(val, addr);
99
100 writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);
101
102 sirfsoc_rtc_iobrg_wait_sync();
103
104 spin_unlock_irqrestore(&rtciobrg_lock, flags);
105 }
106 EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
107
108
regmap_iobg_regwrite(void * context,unsigned int reg,unsigned int val)109 static int regmap_iobg_regwrite(void *context, unsigned int reg,
110 unsigned int val)
111 {
112 sirfsoc_rtc_iobrg_writel(val, reg);
113 return 0;
114 }
115
regmap_iobg_regread(void * context,unsigned int reg,unsigned int * val)116 static int regmap_iobg_regread(void *context, unsigned int reg,
117 unsigned int *val)
118 {
119 *val = (u32)sirfsoc_rtc_iobrg_readl(reg);
120 return 0;
121 }
122
123 static struct regmap_bus regmap_iobg = {
124 .reg_write = regmap_iobg_regwrite,
125 .reg_read = regmap_iobg_regread,
126 };
127
128 /**
129 * devm_regmap_init_iobg(): Initialise managed register map
130 *
131 * @iobg: Device that will be interacted with
132 * @config: Configuration for register map
133 *
134 * The return value will be an ERR_PTR() on error or a valid pointer
135 * to a struct regmap. The regmap will be automatically freed by the
136 * device management code.
137 */
devm_regmap_init_iobg(struct device * dev,const struct regmap_config * config)138 struct regmap *devm_regmap_init_iobg(struct device *dev,
139 const struct regmap_config *config)
140 {
141 const struct regmap_bus *bus = ®map_iobg;
142
143 return devm_regmap_init(dev, bus, dev, config);
144 }
145 EXPORT_SYMBOL_GPL(devm_regmap_init_iobg);
146
147 static const struct of_device_id rtciobrg_ids[] = {
148 { .compatible = "sirf,prima2-rtciobg" },
149 {}
150 };
151
sirfsoc_rtciobrg_probe(struct platform_device * op)152 static int sirfsoc_rtciobrg_probe(struct platform_device *op)
153 {
154 struct device_node *np = op->dev.of_node;
155
156 sirfsoc_rtciobrg_base = of_iomap(np, 0);
157 if (!sirfsoc_rtciobrg_base)
158 panic("unable to map rtc iobrg registers\n");
159
160 return 0;
161 }
162
163 static struct platform_driver sirfsoc_rtciobrg_driver = {
164 .probe = sirfsoc_rtciobrg_probe,
165 .driver = {
166 .name = "sirfsoc-rtciobrg",
167 .of_match_table = rtciobrg_ids,
168 },
169 };
170
sirfsoc_rtciobrg_init(void)171 static int __init sirfsoc_rtciobrg_init(void)
172 {
173 return platform_driver_register(&sirfsoc_rtciobrg_driver);
174 }
175 postcore_initcall(sirfsoc_rtciobrg_init);
176
177 MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>");
178 MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
179 MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
180 MODULE_LICENSE("GPL v2");
181
