1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * arch/arm/mach-ixp4xx/ixdp425-setup.c
4 *
5 * IXDP425/IXCDP1100 board-setup
6 *
7 * Copyright (C) 2003-2005 MontaVista Software, Inc.
8 *
9 * Author: Deepak Saxena <dsaxena@plexity.net>
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/serial.h>
16 #include <linux/tty.h>
17 #include <linux/serial_8250.h>
18 #include <linux/gpio/machine.h>
19 #include <linux/io.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
22 #include <linux/mtd/partitions.h>
23 #include <linux/delay.h>
24 #include <linux/gpio.h>
25 #include <asm/types.h>
26 #include <asm/setup.h>
27 #include <asm/memory.h>
28 #include <mach/hardware.h>
29 #include <asm/mach-types.h>
30 #include <asm/irq.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/flash.h>
33
34 #define IXDP425_SDA_PIN 7
35 #define IXDP425_SCL_PIN 6
36
37 /* NAND Flash pins */
38 #define IXDP425_NAND_NCE_PIN 12
39
40 #define IXDP425_NAND_CMD_BYTE 0x01
41 #define IXDP425_NAND_ADDR_BYTE 0x02
42
43 static struct flash_platform_data ixdp425_flash_data = {
44 .map_name = "cfi_probe",
45 .width = 2,
46 };
47
48 static struct resource ixdp425_flash_resource = {
49 .flags = IORESOURCE_MEM,
50 };
51
52 static struct platform_device ixdp425_flash = {
53 .name = "IXP4XX-Flash",
54 .id = 0,
55 .dev = {
56 .platform_data = &ixdp425_flash_data,
57 },
58 .num_resources = 1,
59 .resource = &ixdp425_flash_resource,
60 };
61
62 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
63 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
64
65 static struct mtd_partition ixdp425_partitions[] = {
66 {
67 .name = "ixp400 NAND FS 0",
68 .offset = 0,
69 .size = SZ_8M
70 }, {
71 .name = "ixp400 NAND FS 1",
72 .offset = MTDPART_OFS_APPEND,
73 .size = MTDPART_SIZ_FULL
74 },
75 };
76
77 static void
ixdp425_flash_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)78 ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
79 {
80 struct nand_chip *this = mtd_to_nand(mtd);
81 int offset = (int)nand_get_controller_data(this);
82
83 if (ctrl & NAND_CTRL_CHANGE) {
84 if (ctrl & NAND_NCE) {
85 gpio_set_value(IXDP425_NAND_NCE_PIN, 0);
86 udelay(5);
87 } else
88 gpio_set_value(IXDP425_NAND_NCE_PIN, 1);
89
90 offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
91 offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
92 nand_set_controller_data(this, (void *)offset);
93 }
94
95 if (cmd != NAND_CMD_NONE)
96 writeb(cmd, this->IO_ADDR_W + offset);
97 }
98
99 static struct platform_nand_data ixdp425_flash_nand_data = {
100 .chip = {
101 .nr_chips = 1,
102 .chip_delay = 30,
103 .partitions = ixdp425_partitions,
104 .nr_partitions = ARRAY_SIZE(ixdp425_partitions),
105 },
106 .ctrl = {
107 .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
108 }
109 };
110
111 static struct resource ixdp425_flash_nand_resource = {
112 .flags = IORESOURCE_MEM,
113 };
114
115 static struct platform_device ixdp425_flash_nand = {
116 .name = "gen_nand",
117 .id = -1,
118 .dev = {
119 .platform_data = &ixdp425_flash_nand_data,
120 },
121 .num_resources = 1,
122 .resource = &ixdp425_flash_nand_resource,
123 };
124 #endif /* CONFIG_MTD_NAND_PLATFORM */
125
126 static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
127 .dev_id = "i2c-gpio.0",
128 .table = {
129 GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
130 NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
131 GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
132 NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
133 },
134 };
135
136 static struct platform_device ixdp425_i2c_gpio = {
137 .name = "i2c-gpio",
138 .id = 0,
139 .dev = {
140 .platform_data = NULL,
141 },
142 };
143
144 static struct resource ixdp425_uart_resources[] = {
145 {
146 .start = IXP4XX_UART1_BASE_PHYS,
147 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
148 .flags = IORESOURCE_MEM
149 },
150 {
151 .start = IXP4XX_UART2_BASE_PHYS,
152 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
153 .flags = IORESOURCE_MEM
154 }
155 };
156
157 static struct plat_serial8250_port ixdp425_uart_data[] = {
158 {
159 .mapbase = IXP4XX_UART1_BASE_PHYS,
160 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
161 .irq = IRQ_IXP4XX_UART1,
162 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
163 .iotype = UPIO_MEM,
164 .regshift = 2,
165 .uartclk = IXP4XX_UART_XTAL,
166 },
167 {
168 .mapbase = IXP4XX_UART2_BASE_PHYS,
169 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
170 .irq = IRQ_IXP4XX_UART2,
171 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
172 .iotype = UPIO_MEM,
173 .regshift = 2,
174 .uartclk = IXP4XX_UART_XTAL,
175 },
176 { },
177 };
178
179 static struct platform_device ixdp425_uart = {
180 .name = "serial8250",
181 .id = PLAT8250_DEV_PLATFORM,
182 .dev.platform_data = ixdp425_uart_data,
183 .num_resources = 2,
184 .resource = ixdp425_uart_resources
185 };
186
187 /* Built-in 10/100 Ethernet MAC interfaces */
188 static struct eth_plat_info ixdp425_plat_eth[] = {
189 {
190 .phy = 0,
191 .rxq = 3,
192 .txreadyq = 20,
193 }, {
194 .phy = 1,
195 .rxq = 4,
196 .txreadyq = 21,
197 }
198 };
199
200 static struct platform_device ixdp425_eth[] = {
201 {
202 .name = "ixp4xx_eth",
203 .id = IXP4XX_ETH_NPEB,
204 .dev.platform_data = ixdp425_plat_eth,
205 }, {
206 .name = "ixp4xx_eth",
207 .id = IXP4XX_ETH_NPEC,
208 .dev.platform_data = ixdp425_plat_eth + 1,
209 }
210 };
211
212 static struct platform_device *ixdp425_devices[] __initdata = {
213 &ixdp425_i2c_gpio,
214 &ixdp425_flash,
215 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
216 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
217 &ixdp425_flash_nand,
218 #endif
219 &ixdp425_uart,
220 &ixdp425_eth[0],
221 &ixdp425_eth[1],
222 };
223
ixdp425_init(void)224 static void __init ixdp425_init(void)
225 {
226 ixp4xx_sys_init();
227
228 ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
229 ixdp425_flash_resource.end =
230 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
231
232 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
233 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
234 ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
235 ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
236
237 gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");
238 gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);
239
240 /* Configure expansion bus for NAND Flash */
241 *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
242 IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
243 IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
244 IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
245 IXP4XX_EXP_BUS_WR_EN |
246 IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
247 #endif
248
249 if (cpu_is_ixp43x()) {
250 ixdp425_uart.num_resources = 1;
251 ixdp425_uart_data[1].flags = 0;
252 }
253
254 gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);
255 platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
256 }
257
258 #ifdef CONFIG_ARCH_IXDP425
259 MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
260 /* Maintainer: MontaVista Software, Inc. */
261 .map_io = ixp4xx_map_io,
262 .init_early = ixp4xx_init_early,
263 .init_irq = ixp4xx_init_irq,
264 .init_time = ixp4xx_timer_init,
265 .atag_offset = 0x100,
266 .init_machine = ixdp425_init,
267 #if defined(CONFIG_PCI)
268 .dma_zone_size = SZ_64M,
269 #endif
270 .restart = ixp4xx_restart,
271 MACHINE_END
272 #endif
273
274 #ifdef CONFIG_MACH_IXDP465
275 MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
276 /* Maintainer: MontaVista Software, Inc. */
277 .map_io = ixp4xx_map_io,
278 .init_early = ixp4xx_init_early,
279 .init_irq = ixp4xx_init_irq,
280 .init_time = ixp4xx_timer_init,
281 .atag_offset = 0x100,
282 .init_machine = ixdp425_init,
283 #if defined(CONFIG_PCI)
284 .dma_zone_size = SZ_64M,
285 #endif
286 MACHINE_END
287 #endif
288
289 #ifdef CONFIG_ARCH_PRPMC1100
290 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
291 /* Maintainer: MontaVista Software, Inc. */
292 .map_io = ixp4xx_map_io,
293 .init_early = ixp4xx_init_early,
294 .init_irq = ixp4xx_init_irq,
295 .init_time = ixp4xx_timer_init,
296 .atag_offset = 0x100,
297 .init_machine = ixdp425_init,
298 #if defined(CONFIG_PCI)
299 .dma_zone_size = SZ_64M,
300 #endif
301 MACHINE_END
302 #endif
303
304 #ifdef CONFIG_MACH_KIXRP435
305 MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
306 /* Maintainer: MontaVista Software, Inc. */
307 .map_io = ixp4xx_map_io,
308 .init_early = ixp4xx_init_early,
309 .init_irq = ixp4xx_init_irq,
310 .init_time = ixp4xx_timer_init,
311 .atag_offset = 0x100,
312 .init_machine = ixdp425_init,
313 #if defined(CONFIG_PCI)
314 .dma_zone_size = SZ_64M,
315 #endif
316 MACHINE_END
317 #endif
318
