1 /* 2 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h 3 * 4 * Register definitions for IXP4xx chipset. This file contains 5 * register location and bit definitions only. Platform specific 6 * definitions and helper function declarations are in platform.h 7 * and machine-name.h. 8 * 9 * Copyright (C) 2002 Intel Corporation. 10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 */ 17 18 #ifndef _ASM_ARM_IXP4XX_H_ 19 #define _ASM_ARM_IXP4XX_H_ 20 21 /* 22 * IXP4xx Linux Memory Map: 23 * 24 * Phy Size Virt Description 25 * ========================================================================= 26 * 27 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM 28 * 29 * 0x48000000 0x04000000 ioremap'd PCI Memory Space 30 * 31 * 0x50000000 0x10000000 ioremap'd EXP BUS 32 * 33 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals 34 * 35 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG 36 * 37 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG 38 * 39 * 0x60000000 0x00004000 0xFEF15000 QMgr 40 */ 41 42 /* 43 * Queue Manager 44 */ 45 #define IXP4XX_QMGR_BASE_PHYS 0x60000000 46 #define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000) 47 #define IXP4XX_QMGR_REGION_SIZE 0x00004000 48 49 /* 50 * Peripheral space, including debug UART. Must be section-aligned so that 51 * it can be used with the low-level debug code. 52 */ 53 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 54 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) 55 #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 56 57 /* 58 * PCI Config registers 59 */ 60 #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 61 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) 62 #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 63 64 /* 65 * Expansion BUS Configuration registers 66 */ 67 #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 68 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 69 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 70 71 #define IXP4XX_EXP_CS0_OFFSET 0x00 72 #define IXP4XX_EXP_CS1_OFFSET 0x04 73 #define IXP4XX_EXP_CS2_OFFSET 0x08 74 #define IXP4XX_EXP_CS3_OFFSET 0x0C 75 #define IXP4XX_EXP_CS4_OFFSET 0x10 76 #define IXP4XX_EXP_CS5_OFFSET 0x14 77 #define IXP4XX_EXP_CS6_OFFSET 0x18 78 #define IXP4XX_EXP_CS7_OFFSET 0x1C 79 #define IXP4XX_EXP_CFG0_OFFSET 0x20 80 #define IXP4XX_EXP_CFG1_OFFSET 0x24 81 #define IXP4XX_EXP_CFG2_OFFSET 0x28 82 #define IXP4XX_EXP_CFG3_OFFSET 0x2C 83 84 /* 85 * Expansion Bus Controller registers. 86 */ 87 #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) 88 89 #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) 90 #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) 91 #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 92 #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) 93 #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) 94 #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) 95 #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) 96 #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) 97 98 #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 99 #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 100 #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 101 #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) 102 103 104 /* 105 * Peripheral Space Register Region Base Addresses 106 */ 107 #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) 108 #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) 109 #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) 110 #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) 111 #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) 112 #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) 113 #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) 114 #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) 115 #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) 116 #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) 117 #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) 118 #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) 119 /* ixp46X only */ 120 #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) 121 #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) 122 #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) 123 #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) 124 #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) 125 #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) 126 #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) 127 128 129 #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) 130 #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) 131 #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) 132 #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) 133 #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) 134 #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) 135 #define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000) 136 #define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000) 137 #define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000) 138 #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) 139 #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) 140 #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) 141 /* ixp46X only */ 142 #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) 143 #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) 144 #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) 145 #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) 146 #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) 147 #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) 148 #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) 149 150 /* 151 * Constants to make it easy to access Interrupt Controller registers 152 */ 153 #define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */ 154 #define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */ 155 #define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ 156 #define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */ 157 #define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */ 158 #define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */ 159 #define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ 160 #define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ 161 162 /* 163 * IXP465-only 164 */ 165 #define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */ 166 #define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */ 167 #define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */ 168 #define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */ 169 #define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */ 170 #define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */ 171 172 173 /* 174 * Interrupt Controller Register Definitions. 175 */ 176 177 #define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x))) 178 179 #define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET) 180 #define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET) 181 #define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET) 182 #define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET) 183 #define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET) 184 #define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET) 185 #define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 186 #define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET) 187 #define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET) 188 #define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET) 189 #define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET) 190 #define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET) 191 #define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET) 192 #define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET) 193 194 /* 195 * Constants to make it easy to access GPIO registers 196 */ 197 #define IXP4XX_GPIO_GPOUTR_OFFSET 0x00 198 #define IXP4XX_GPIO_GPOER_OFFSET 0x04 199 #define IXP4XX_GPIO_GPINR_OFFSET 0x08 200 #define IXP4XX_GPIO_GPISR_OFFSET 0x0C 201 #define IXP4XX_GPIO_GPIT1R_OFFSET 0x10 202 #define IXP4XX_GPIO_GPIT2R_OFFSET 0x14 203 #define IXP4XX_GPIO_GPCLKR_OFFSET 0x18 204 #define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C 205 206 /* 207 * GPIO Register Definitions. 208 * [Only perform 32bit reads/writes] 209 */ 210 #define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x))) 211 212 #define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET) 213 #define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET) 214 #define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET) 215 #define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET) 216 #define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET) 217 #define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET) 218 #define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET) 219 #define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET) 220 221 /* 222 * GPIO register bit definitions 223 */ 224 225 /* Interrupt styles 226 */ 227 #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0 228 #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1 229 #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2 230 #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3 231 #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4 232 233 /* 234 * Mask used to clear interrupt styles 235 */ 236 #define IXP4XX_GPIO_STYLE_CLEAR 0x7 237 #define IXP4XX_GPIO_STYLE_SIZE 3 238 239 /* 240 * Constants to make it easy to access Timer Control/Status registers 241 */ 242 #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ 243 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ 244 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ 245 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ 246 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ 247 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ 248 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ 249 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ 250 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ 251 252 /* 253 * Operating System Timer Register Definitions. 254 */ 255 256 #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) 257 258 #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) 259 #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) 260 #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) 261 #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) 262 #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) 263 #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) 264 #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) 265 #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) 266 #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) 267 268 /* 269 * Timer register values and bit definitions 270 */ 271 #define IXP4XX_OST_ENABLE 0x00000001 272 #define IXP4XX_OST_ONE_SHOT 0x00000002 273 /* Low order bits of reload value ignored */ 274 #define IXP4XX_OST_RELOAD_MASK 0x00000003 275 #define IXP4XX_OST_DISABLED 0x00000000 276 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 277 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 278 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 279 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 280 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 281 282 #define IXP4XX_WDT_KEY 0x0000482E 283 284 #define IXP4XX_WDT_RESET_ENABLE 0x00000001 285 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 286 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 287 288 289 /* 290 * Constants to make it easy to access PCI Control/Status registers 291 */ 292 #define PCI_NP_AD_OFFSET 0x00 293 #define PCI_NP_CBE_OFFSET 0x04 294 #define PCI_NP_WDATA_OFFSET 0x08 295 #define PCI_NP_RDATA_OFFSET 0x0c 296 #define PCI_CRP_AD_CBE_OFFSET 0x10 297 #define PCI_CRP_WDATA_OFFSET 0x14 298 #define PCI_CRP_RDATA_OFFSET 0x18 299 #define PCI_CSR_OFFSET 0x1c 300 #define PCI_ISR_OFFSET 0x20 301 #define PCI_INTEN_OFFSET 0x24 302 #define PCI_DMACTRL_OFFSET 0x28 303 #define PCI_AHBMEMBASE_OFFSET 0x2c 304 #define PCI_AHBIOBASE_OFFSET 0x30 305 #define PCI_PCIMEMBASE_OFFSET 0x34 306 #define PCI_AHBDOORBELL_OFFSET 0x38 307 #define PCI_PCIDOORBELL_OFFSET 0x3C 308 #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 309 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 310 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 311 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C 312 #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 313 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 314 315 /* 316 * PCI Control/Status Registers 317 */ 318 #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) 319 320 #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) 321 #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) 322 #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) 323 #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) 324 #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) 325 #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) 326 #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) 327 #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 328 #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET) 329 #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) 330 #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) 331 #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) 332 #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) 333 #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) 334 #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) 335 #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) 336 #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) 337 #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) 338 #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) 339 #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) 340 #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) 341 #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) 342 343 /* 344 * PCI register values and bit definitions 345 */ 346 347 /* CSR bit definitions */ 348 #define PCI_CSR_HOST 0x00000001 349 #define PCI_CSR_ARBEN 0x00000002 350 #define PCI_CSR_ADS 0x00000004 351 #define PCI_CSR_PDS 0x00000008 352 #define PCI_CSR_ABE 0x00000010 353 #define PCI_CSR_DBT 0x00000020 354 #define PCI_CSR_ASE 0x00000100 355 #define PCI_CSR_IC 0x00008000 356 357 /* ISR (Interrupt status) Register bit definitions */ 358 #define PCI_ISR_PSE 0x00000001 359 #define PCI_ISR_PFE 0x00000002 360 #define PCI_ISR_PPE 0x00000004 361 #define PCI_ISR_AHBE 0x00000008 362 #define PCI_ISR_APDC 0x00000010 363 #define PCI_ISR_PADC 0x00000020 364 #define PCI_ISR_ADB 0x00000040 365 #define PCI_ISR_PDB 0x00000080 366 367 /* INTEN (Interrupt Enable) Register bit definitions */ 368 #define PCI_INTEN_PSE 0x00000001 369 #define PCI_INTEN_PFE 0x00000002 370 #define PCI_INTEN_PPE 0x00000004 371 #define PCI_INTEN_AHBE 0x00000008 372 #define PCI_INTEN_APDC 0x00000010 373 #define PCI_INTEN_PADC 0x00000020 374 #define PCI_INTEN_ADB 0x00000040 375 #define PCI_INTEN_PDB 0x00000080 376 377 /* 378 * Shift value for byte enable on NP cmd/byte enable register 379 */ 380 #define IXP4XX_PCI_NP_CBE_BESL 4 381 382 /* 383 * PCI commands supported by NP access unit 384 */ 385 #define NP_CMD_IOREAD 0x2 386 #define NP_CMD_IOWRITE 0x3 387 #define NP_CMD_CONFIGREAD 0xa 388 #define NP_CMD_CONFIGWRITE 0xb 389 #define NP_CMD_MEMREAD 0x6 390 #define NP_CMD_MEMWRITE 0x7 391 392 /* 393 * Constants for CRP access into local config space 394 */ 395 #define CRP_AD_CBE_BESL 20 396 #define CRP_AD_CBE_WRITE 0x00010000 397 398 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 399 400 /* "fuse" bits of IXP_EXP_CFG2 */ 401 /* All IXP4xx CPUs */ 402 #define IXP4XX_FEATURE_RCOMP (1 << 0) 403 #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) 404 #define IXP4XX_FEATURE_HASH (1 << 2) 405 #define IXP4XX_FEATURE_AES (1 << 3) 406 #define IXP4XX_FEATURE_DES (1 << 4) 407 #define IXP4XX_FEATURE_HDLC (1 << 5) 408 #define IXP4XX_FEATURE_AAL (1 << 6) 409 #define IXP4XX_FEATURE_HSS (1 << 7) 410 #define IXP4XX_FEATURE_UTOPIA (1 << 8) 411 #define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) 412 #define IXP4XX_FEATURE_NPEC_ETH (1 << 10) 413 #define IXP4XX_FEATURE_RESET_NPEA (1 << 11) 414 #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) 415 #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) 416 #define IXP4XX_FEATURE_PCI (1 << 14) 417 #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) 418 #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) 419 #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ 420 IXP4XX_FEATURE_USB_DEVICE | \ 421 IXP4XX_FEATURE_HASH | \ 422 IXP4XX_FEATURE_AES | \ 423 IXP4XX_FEATURE_DES | \ 424 IXP4XX_FEATURE_HDLC | \ 425 IXP4XX_FEATURE_AAL | \ 426 IXP4XX_FEATURE_HSS | \ 427 IXP4XX_FEATURE_UTOPIA | \ 428 IXP4XX_FEATURE_NPEB_ETH0 | \ 429 IXP4XX_FEATURE_NPEC_ETH | \ 430 IXP4XX_FEATURE_RESET_NPEA | \ 431 IXP4XX_FEATURE_RESET_NPEB | \ 432 IXP4XX_FEATURE_RESET_NPEC | \ 433 IXP4XX_FEATURE_PCI | \ 434 IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ 435 IXP4XX_FEATURE_XSCALE_MAX_FREQ) 436 437 438 /* IXP43x/46x CPUs */ 439 #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) 440 #define IXP4XX_FEATURE_USB_HOST (1 << 18) 441 #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) 442 #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ 443 IXP4XX_FEATURE_ECC_TIMESYNC | \ 444 IXP4XX_FEATURE_USB_HOST | \ 445 IXP4XX_FEATURE_NPEA_ETH) 446 447 /* IXP46x CPU (including IXP455) only */ 448 #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) 449 #define IXP4XX_FEATURE_RSA (1 << 21) 450 #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ 451 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ 452 IXP4XX_FEATURE_RSA) 453 454 #endif 455
