1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
4 // http://www.samsung.com
5 //
6 // EXYNOS - Suspend support
7 //
8 // Based on arch/arm/mach-s3c2410/pm.c
9 // Copyright (c) 2006 Simtec Electronics
10 // Ben Dooks <ben@simtec.co.uk>
11
12 #include <linux/init.h>
13 #include <linux/suspend.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_address.h>
21 #include <linux/err.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/soc/samsung/exynos-pmu.h>
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
25
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28 #include <asm/firmware.h>
29 #include <asm/mcpm.h>
30 #include <asm/smp_scu.h>
31 #include <asm/suspend.h>
32
33 #include <plat/pm-common.h>
34
35 #include "common.h"
36
37 #define REG_TABLE_END (-1U)
38
39 #define EXYNOS5420_CPU_STATE 0x28
40
41 /**
42 * struct exynos_wkup_irq - PMU IRQ to mask mapping
43 * @hwirq: Hardware IRQ signal of the PMU
44 * @mask: Mask in PMU wake-up mask register
45 */
46 struct exynos_wkup_irq {
47 unsigned int hwirq;
48 u32 mask;
49 };
50
51 struct exynos_pm_data {
52 const struct exynos_wkup_irq *wkup_irq;
53 unsigned int wake_disable_mask;
54
55 void (*pm_prepare)(void);
56 void (*pm_resume_prepare)(void);
57 void (*pm_resume)(void);
58 int (*pm_suspend)(void);
59 int (*cpu_suspend)(unsigned long);
60 };
61
62 static const struct exynos_pm_data *pm_data __ro_after_init;
63
64 static int exynos5420_cpu_state;
65 static unsigned int exynos_pmu_spare3;
66
67 /*
68 * GIC wake-up support
69 */
70
71 static u32 exynos_irqwake_intmask = 0xffffffff;
72
73 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
74 { 73, BIT(1) }, /* RTC alarm */
75 { 74, BIT(2) }, /* RTC tick */
76 { /* sentinel */ },
77 };
78
79 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
80 { 44, BIT(1) }, /* RTC alarm */
81 { 45, BIT(2) }, /* RTC tick */
82 { /* sentinel */ },
83 };
84
85 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
86 { 43, BIT(1) }, /* RTC alarm */
87 { 44, BIT(2) }, /* RTC tick */
88 { /* sentinel */ },
89 };
90
exynos_irq_set_wake(struct irq_data * data,unsigned int state)91 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
92 {
93 const struct exynos_wkup_irq *wkup_irq;
94
95 if (!pm_data->wkup_irq)
96 return -ENOENT;
97 wkup_irq = pm_data->wkup_irq;
98
99 while (wkup_irq->mask) {
100 if (wkup_irq->hwirq == data->hwirq) {
101 if (!state)
102 exynos_irqwake_intmask |= wkup_irq->mask;
103 else
104 exynos_irqwake_intmask &= ~wkup_irq->mask;
105 return 0;
106 }
107 ++wkup_irq;
108 }
109
110 return -ENOENT;
111 }
112
113 static struct irq_chip exynos_pmu_chip = {
114 .name = "PMU",
115 .irq_eoi = irq_chip_eoi_parent,
116 .irq_mask = irq_chip_mask_parent,
117 .irq_unmask = irq_chip_unmask_parent,
118 .irq_retrigger = irq_chip_retrigger_hierarchy,
119 .irq_set_wake = exynos_irq_set_wake,
120 #ifdef CONFIG_SMP
121 .irq_set_affinity = irq_chip_set_affinity_parent,
122 #endif
123 };
124
exynos_pmu_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)125 static int exynos_pmu_domain_translate(struct irq_domain *d,
126 struct irq_fwspec *fwspec,
127 unsigned long *hwirq,
128 unsigned int *type)
129 {
130 if (is_of_node(fwspec->fwnode)) {
131 if (fwspec->param_count != 3)
132 return -EINVAL;
133
134 /* No PPI should point to this domain */
135 if (fwspec->param[0] != 0)
136 return -EINVAL;
137
138 *hwirq = fwspec->param[1];
139 *type = fwspec->param[2];
140 return 0;
141 }
142
143 return -EINVAL;
144 }
145
exynos_pmu_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)146 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
147 unsigned int virq,
148 unsigned int nr_irqs, void *data)
149 {
150 struct irq_fwspec *fwspec = data;
151 struct irq_fwspec parent_fwspec;
152 irq_hw_number_t hwirq;
153 int i;
154
155 if (fwspec->param_count != 3)
156 return -EINVAL; /* Not GIC compliant */
157 if (fwspec->param[0] != 0)
158 return -EINVAL; /* No PPI should point to this domain */
159
160 hwirq = fwspec->param[1];
161
162 for (i = 0; i < nr_irqs; i++)
163 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
164 &exynos_pmu_chip, NULL);
165
166 parent_fwspec = *fwspec;
167 parent_fwspec.fwnode = domain->parent->fwnode;
168 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
169 &parent_fwspec);
170 }
171
172 static const struct irq_domain_ops exynos_pmu_domain_ops = {
173 .translate = exynos_pmu_domain_translate,
174 .alloc = exynos_pmu_domain_alloc,
175 .free = irq_domain_free_irqs_common,
176 };
177
exynos_pmu_irq_init(struct device_node * node,struct device_node * parent)178 static int __init exynos_pmu_irq_init(struct device_node *node,
179 struct device_node *parent)
180 {
181 struct irq_domain *parent_domain, *domain;
182
183 if (!parent) {
184 pr_err("%pOF: no parent, giving up\n", node);
185 return -ENODEV;
186 }
187
188 parent_domain = irq_find_host(parent);
189 if (!parent_domain) {
190 pr_err("%pOF: unable to obtain parent domain\n", node);
191 return -ENXIO;
192 }
193
194 pmu_base_addr = of_iomap(node, 0);
195
196 if (!pmu_base_addr) {
197 pr_err("%pOF: failed to find exynos pmu register\n", node);
198 return -ENOMEM;
199 }
200
201 domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
202 node, &exynos_pmu_domain_ops,
203 NULL);
204 if (!domain) {
205 iounmap(pmu_base_addr);
206 pmu_base_addr = NULL;
207 return -ENOMEM;
208 }
209
210 /*
211 * Clear the OF_POPULATED flag set in of_irq_init so that
212 * later the Exynos PMU platform device won't be skipped.
213 */
214 of_node_clear_flag(node, OF_POPULATED);
215
216 return 0;
217 }
218
219 #define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
220
221 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
222 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
223 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
224 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
225 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
226
exynos_cpu_do_idle(void)227 static int exynos_cpu_do_idle(void)
228 {
229 /* issue the standby signal into the pm unit. */
230 cpu_do_idle();
231
232 pr_info("Failed to suspend the system\n");
233 return 1; /* Aborting suspend */
234 }
exynos_flush_cache_all(void)235 static void exynos_flush_cache_all(void)
236 {
237 flush_cache_all();
238 outer_flush_all();
239 }
240
exynos_cpu_suspend(unsigned long arg)241 static int exynos_cpu_suspend(unsigned long arg)
242 {
243 exynos_flush_cache_all();
244 return exynos_cpu_do_idle();
245 }
246
exynos3250_cpu_suspend(unsigned long arg)247 static int exynos3250_cpu_suspend(unsigned long arg)
248 {
249 flush_cache_all();
250 return exynos_cpu_do_idle();
251 }
252
exynos5420_cpu_suspend(unsigned long arg)253 static int exynos5420_cpu_suspend(unsigned long arg)
254 {
255 /* MCPM works with HW CPU identifiers */
256 unsigned int mpidr = read_cpuid_mpidr();
257 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
258 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
259
260 writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
261
262 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
263 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
264 mcpm_cpu_suspend();
265 }
266
267 pr_info("Failed to suspend the system\n");
268
269 /* return value != 0 means failure */
270 return 1;
271 }
272
exynos_pm_set_wakeup_mask(void)273 static void exynos_pm_set_wakeup_mask(void)
274 {
275 /* Set wake-up mask registers */
276 pmu_raw_writel(exynos_get_eint_wake_mask(), EXYNOS_EINT_WAKEUP_MASK);
277 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
278 }
279
exynos_pm_enter_sleep_mode(void)280 static void exynos_pm_enter_sleep_mode(void)
281 {
282 /* Set value of power down register for sleep mode */
283 exynos_sys_powerdown_conf(SYS_SLEEP);
284 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
285 }
286
exynos_pm_prepare(void)287 static void exynos_pm_prepare(void)
288 {
289 exynos_set_delayed_reset_assertion(false);
290
291 /* Set wake-up mask registers */
292 exynos_pm_set_wakeup_mask();
293
294 exynos_pm_enter_sleep_mode();
295
296 /* ensure at least INFORM0 has the resume address */
297 pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
298 }
299
exynos3250_pm_prepare(void)300 static void exynos3250_pm_prepare(void)
301 {
302 unsigned int tmp;
303
304 /* Set wake-up mask registers */
305 exynos_pm_set_wakeup_mask();
306
307 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
308 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
309 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
310
311 exynos_pm_enter_sleep_mode();
312
313 /* ensure at least INFORM0 has the resume address */
314 pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
315 }
316
exynos5420_pm_prepare(void)317 static void exynos5420_pm_prepare(void)
318 {
319 unsigned int tmp;
320
321 /* Set wake-up mask registers */
322 exynos_pm_set_wakeup_mask();
323
324 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
325 /*
326 * The cpu state needs to be saved and restored so that the
327 * secondary CPUs will enter low power start. Though the U-Boot
328 * is setting the cpu state with low power flag, the kernel
329 * needs to restore it back in case, the primary cpu fails to
330 * suspend for any reason.
331 */
332 exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
333 EXYNOS5420_CPU_STATE);
334
335 exynos_pm_enter_sleep_mode();
336
337 /* ensure at least INFORM0 has the resume address */
338 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
339 pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
340
341 tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
342 tmp &= ~EXYNOS_L2_USE_RETENTION;
343 pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
344
345 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
346 tmp |= EXYNOS5420_UFS;
347 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
348
349 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
350 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
351 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
352
353 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
354 tmp |= EXYNOS5420_EMULATION;
355 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
356
357 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
358 tmp |= EXYNOS5420_EMULATION;
359 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
360 }
361
362
exynos_pm_suspend(void)363 static int exynos_pm_suspend(void)
364 {
365 exynos_pm_central_suspend();
366
367 /* Setting SEQ_OPTION register */
368 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
369 S5P_CENTRAL_SEQ_OPTION);
370
371 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
372 exynos_cpu_save_register();
373
374 return 0;
375 }
376
exynos5420_pm_suspend(void)377 static int exynos5420_pm_suspend(void)
378 {
379 u32 this_cluster;
380
381 exynos_pm_central_suspend();
382
383 /* Setting SEQ_OPTION register */
384
385 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
386 if (!this_cluster)
387 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
388 S5P_CENTRAL_SEQ_OPTION);
389 else
390 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
391 S5P_CENTRAL_SEQ_OPTION);
392 return 0;
393 }
394
exynos_pm_resume(void)395 static void exynos_pm_resume(void)
396 {
397 u32 cpuid = read_cpuid_part();
398
399 if (exynos_pm_central_resume())
400 goto early_wakeup;
401
402 if (cpuid == ARM_CPU_PART_CORTEX_A9)
403 exynos_scu_enable();
404
405 if (call_firmware_op(resume) == -ENOSYS
406 && cpuid == ARM_CPU_PART_CORTEX_A9)
407 exynos_cpu_restore_register();
408
409 early_wakeup:
410
411 /* Clear SLEEP mode set in INFORM1 */
412 pmu_raw_writel(0x0, S5P_INFORM1);
413 exynos_set_delayed_reset_assertion(true);
414 }
415
exynos3250_pm_resume(void)416 static void exynos3250_pm_resume(void)
417 {
418 u32 cpuid = read_cpuid_part();
419
420 if (exynos_pm_central_resume())
421 goto early_wakeup;
422
423 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
424
425 if (call_firmware_op(resume) == -ENOSYS
426 && cpuid == ARM_CPU_PART_CORTEX_A9)
427 exynos_cpu_restore_register();
428
429 early_wakeup:
430
431 /* Clear SLEEP mode set in INFORM1 */
432 pmu_raw_writel(0x0, S5P_INFORM1);
433 }
434
exynos5420_prepare_pm_resume(void)435 static void exynos5420_prepare_pm_resume(void)
436 {
437 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
438 WARN_ON(mcpm_cpu_powered_up());
439 }
440
exynos5420_pm_resume(void)441 static void exynos5420_pm_resume(void)
442 {
443 unsigned long tmp;
444
445 /* Restore the CPU0 low power state register */
446 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
447 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
448 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
449
450 /* Restore the sysram cpu state register */
451 writel_relaxed(exynos5420_cpu_state,
452 sysram_base_addr + EXYNOS5420_CPU_STATE);
453
454 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
455 S5P_CENTRAL_SEQ_OPTION);
456
457 if (exynos_pm_central_resume())
458 goto early_wakeup;
459
460 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
461
462 early_wakeup:
463
464 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
465 tmp &= ~EXYNOS5420_UFS;
466 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
467
468 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
469 tmp &= ~EXYNOS5420_EMULATION;
470 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
471
472 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
473 tmp &= ~EXYNOS5420_EMULATION;
474 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
475
476 /* Clear SLEEP mode set in INFORM1 */
477 pmu_raw_writel(0x0, S5P_INFORM1);
478 }
479
480 /*
481 * Suspend Ops
482 */
483
exynos_suspend_enter(suspend_state_t state)484 static int exynos_suspend_enter(suspend_state_t state)
485 {
486 int ret;
487
488 s3c_pm_debug_init();
489
490 S3C_PMDBG("%s: suspending the system...\n", __func__);
491
492 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
493 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
494
495 if (exynos_irqwake_intmask == -1U
496 && exynos_get_eint_wake_mask() == -1U) {
497 pr_err("%s: No wake-up sources!\n", __func__);
498 pr_err("%s: Aborting sleep\n", __func__);
499 return -EINVAL;
500 }
501
502 s3c_pm_save_uarts();
503 if (pm_data->pm_prepare)
504 pm_data->pm_prepare();
505 flush_cache_all();
506 s3c_pm_check_store();
507
508 ret = call_firmware_op(suspend);
509 if (ret == -ENOSYS)
510 ret = cpu_suspend(0, pm_data->cpu_suspend);
511 if (ret)
512 return ret;
513
514 if (pm_data->pm_resume_prepare)
515 pm_data->pm_resume_prepare();
516 s3c_pm_restore_uarts();
517
518 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
519 pmu_raw_readl(S5P_WAKEUP_STAT));
520
521 s3c_pm_check_restore();
522
523 S3C_PMDBG("%s: resuming the system...\n", __func__);
524
525 return 0;
526 }
527
exynos_suspend_prepare(void)528 static int exynos_suspend_prepare(void)
529 {
530 int ret;
531
532 /*
533 * REVISIT: It would be better if struct platform_suspend_ops
534 * .prepare handler get the suspend_state_t as a parameter to
535 * avoid hard-coding the suspend to mem state. It's safe to do
536 * it now only because the suspend_valid_only_mem function is
537 * used as the .valid callback used to check if a given state
538 * is supported by the platform anyways.
539 */
540 ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
541 if (ret) {
542 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
543 return ret;
544 }
545
546 s3c_pm_check_prepare();
547
548 return 0;
549 }
550
exynos_suspend_finish(void)551 static void exynos_suspend_finish(void)
552 {
553 int ret;
554
555 s3c_pm_check_cleanup();
556
557 ret = regulator_suspend_finish();
558 if (ret)
559 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
560 }
561
562 static const struct platform_suspend_ops exynos_suspend_ops = {
563 .enter = exynos_suspend_enter,
564 .prepare = exynos_suspend_prepare,
565 .finish = exynos_suspend_finish,
566 .valid = suspend_valid_only_mem,
567 };
568
569 static const struct exynos_pm_data exynos3250_pm_data = {
570 .wkup_irq = exynos3250_wkup_irq,
571 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
572 .pm_suspend = exynos_pm_suspend,
573 .pm_resume = exynos3250_pm_resume,
574 .pm_prepare = exynos3250_pm_prepare,
575 .cpu_suspend = exynos3250_cpu_suspend,
576 };
577
578 static const struct exynos_pm_data exynos4_pm_data = {
579 .wkup_irq = exynos4_wkup_irq,
580 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
581 .pm_suspend = exynos_pm_suspend,
582 .pm_resume = exynos_pm_resume,
583 .pm_prepare = exynos_pm_prepare,
584 .cpu_suspend = exynos_cpu_suspend,
585 };
586
587 static const struct exynos_pm_data exynos5250_pm_data = {
588 .wkup_irq = exynos5250_wkup_irq,
589 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
590 .pm_suspend = exynos_pm_suspend,
591 .pm_resume = exynos_pm_resume,
592 .pm_prepare = exynos_pm_prepare,
593 .cpu_suspend = exynos_cpu_suspend,
594 };
595
596 static const struct exynos_pm_data exynos5420_pm_data = {
597 .wkup_irq = exynos5250_wkup_irq,
598 .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
599 .pm_resume_prepare = exynos5420_prepare_pm_resume,
600 .pm_resume = exynos5420_pm_resume,
601 .pm_suspend = exynos5420_pm_suspend,
602 .pm_prepare = exynos5420_pm_prepare,
603 .cpu_suspend = exynos5420_cpu_suspend,
604 };
605
606 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
607 {
608 .compatible = "samsung,exynos3250-pmu",
609 .data = &exynos3250_pm_data,
610 }, {
611 .compatible = "samsung,exynos4210-pmu",
612 .data = &exynos4_pm_data,
613 }, {
614 .compatible = "samsung,exynos4412-pmu",
615 .data = &exynos4_pm_data,
616 }, {
617 .compatible = "samsung,exynos5250-pmu",
618 .data = &exynos5250_pm_data,
619 }, {
620 .compatible = "samsung,exynos5420-pmu",
621 .data = &exynos5420_pm_data,
622 },
623 { /*sentinel*/ },
624 };
625
626 static struct syscore_ops exynos_pm_syscore_ops;
627
exynos_pm_init(void)628 void __init exynos_pm_init(void)
629 {
630 const struct of_device_id *match;
631 struct device_node *np;
632 u32 tmp;
633
634 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
635 if (!np) {
636 pr_err("Failed to find PMU node\n");
637 return;
638 }
639
640 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
641 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
642 return;
643 }
644
645 pm_data = (const struct exynos_pm_data *) match->data;
646
647 /* All wakeup disable */
648 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
649 tmp |= pm_data->wake_disable_mask;
650 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
651
652 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
653 exynos_pm_syscore_ops.resume = pm_data->pm_resume;
654
655 register_syscore_ops(&exynos_pm_syscore_ops);
656 suspend_set_ops(&exynos_suspend_ops);
657 }
658
