1 /*
2 * TI DA830/OMAP L137 chip specific setup
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2009 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/clk-provider.h>
12 #include <linux/clk/davinci.h>
13 #include <linux/gpio.h>
14 #include <linux/init.h>
15 #include <linux/platform_data/gpio-davinci.h>
16
17 #include <asm/mach/map.h>
18
19 #include <mach/common.h>
20 #include <mach/cputype.h>
21 #include <mach/da8xx.h>
22 #include <mach/irqs.h>
23 #include <mach/time.h>
24
25 #include "mux.h"
26
27 /* Offsets of the 8 compare registers on the da830 */
28 #define DA830_CMP12_0 0x60
29 #define DA830_CMP12_1 0x64
30 #define DA830_CMP12_2 0x68
31 #define DA830_CMP12_3 0x6c
32 #define DA830_CMP12_4 0x70
33 #define DA830_CMP12_5 0x74
34 #define DA830_CMP12_6 0x78
35 #define DA830_CMP12_7 0x7c
36
37 #define DA830_REF_FREQ 24000000
38
39 /*
40 * Device specific mux setup
41 *
42 * soc description mux mode mode mux dbg
43 * reg offset mask mode
44 */
45 static const struct mux_config da830_pins[] = {
46 #ifdef CONFIG_DAVINCI_MUX
47 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
48 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
49 MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false)
50 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
51 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
52 MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false)
53 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
54 MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false)
55 MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false)
56 MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false)
57 MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false)
58 MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false)
59 MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false)
60 MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false)
61 MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false)
62 MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false)
63 MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false)
64 MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false)
65 MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false)
66 MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false)
67 MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false)
68 MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false)
69 MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false)
70 MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false)
71 MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false)
72 MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false)
73 MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false)
74 MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false)
75 MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false)
76 MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false)
77 MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false)
78 MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false)
79 MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false)
80 MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false)
81 MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false)
82 MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false)
83 MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false)
84 MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false)
85 MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false)
86 MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false)
87 MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false)
88 MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false)
89 MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false)
90 MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false)
91 MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false)
92 MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false)
93 MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false)
94 MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false)
95 MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false)
96 MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false)
97 MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false)
98 MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false)
99 MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false)
100 MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false)
101 MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false)
102 MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false)
103 MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false)
104 MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false)
105 MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false)
106 MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false)
107 MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false)
108 MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false)
109 MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false)
110 MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false)
111 MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false)
112 MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false)
113 MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false)
114 MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false)
115 MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false)
116 MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false)
117 MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false)
118 MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false)
119 MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false)
120 MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false)
121 MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false)
122 MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false)
123 MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false)
124 MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false)
125 MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false)
126 MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false)
127 MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false)
128 MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false)
129 MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false)
130 MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false)
131 MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false)
132 MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false)
133 MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false)
134 MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false)
135 MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false)
136 MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false)
137 MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false)
138 MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false)
139 MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false)
140 MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false)
141 MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false)
142 MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false)
143 MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false)
144 MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false)
145 MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false)
146 MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false)
147 MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false)
148 MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false)
149 MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false)
150 MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false)
151 MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false)
152 MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false)
153 MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false)
154 MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false)
155 MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false)
156 MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false)
157 MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false)
158 MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false)
159 MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false)
160 MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false)
161 MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false)
162 MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false)
163 MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false)
164 MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false)
165 MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false)
166 MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false)
167 MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false)
168 MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false)
169 MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false)
170 MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false)
171 MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false)
172 MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false)
173 MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false)
174 MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false)
175 MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false)
176 MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false)
177 MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false)
178 MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false)
179 MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false)
180 MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false)
181 MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false)
182 MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false)
183 MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false)
184 MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false)
185 MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false)
186 MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false)
187 MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false)
188 MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false)
189 MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false)
190 MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false)
191 MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false)
192 MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false)
193 MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false)
194 MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false)
195 MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false)
196 MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false)
197 MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false)
198 MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false)
199 MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false)
200 MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false)
201 MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false)
202 MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false)
203 MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false)
204 MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false)
205 MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false)
206 MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false)
207 MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false)
208 MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false)
209 MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false)
210 MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false)
211 MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false)
212 MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false)
213 MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false)
214 MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false)
215 MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false)
216 MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false)
217 MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false)
218 MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false)
219 MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false)
220 MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false)
221 MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false)
222 MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false)
223 MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false)
224 MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false)
225 MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false)
226 MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false)
227 MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false)
228 MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false)
229 MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false)
230 MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false)
231 MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false)
232 MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false)
233 MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false)
234 MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false)
235 MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false)
236 MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false)
237 MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false)
238 MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false)
239 MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false)
240 MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false)
241 MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false)
242 MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false)
243 MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false)
244 MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false)
245 MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false)
246 MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false)
247 MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false)
248 MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false)
249 MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false)
250 MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false)
251 MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false)
252 MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false)
253 MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false)
254 MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false)
255 MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false)
256 MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false)
257 MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false)
258 MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false)
259 MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false)
260 MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false)
261 MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false)
262 MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false)
263 MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false)
264 MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false)
265 MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false)
266 MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false)
267 MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false)
268 MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false)
269 MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false)
270 MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false)
271 MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false)
272 MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false)
273 MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false)
274 MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false)
275 MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false)
276 MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false)
277 MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false)
278 MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false)
279 MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false)
280 MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false)
281 MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false)
282 MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false)
283 MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false)
284 MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false)
285 MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false)
286 MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false)
287 MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false)
288 MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false)
289 MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false)
290 MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false)
291 MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false)
292 MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false)
293 MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false)
294 MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false)
295 MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false)
296 MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false)
297 MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false)
298 MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false)
299 MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false)
300 MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false)
301 MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false)
302 MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false)
303 MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false)
304 MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false)
305 MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false)
306 MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false)
307 MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false)
308 MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false)
309 MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false)
310 MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false)
311 MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false)
312 MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false)
313 MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false)
314 MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false)
315 MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false)
316 MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false)
317 MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false)
318 MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false)
319 MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false)
320 MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false)
321 MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false)
322 MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false)
323 MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false)
324 MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false)
325 MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false)
326 MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false)
327 MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false)
328 MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false)
329 MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false)
330 MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false)
331 MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false)
332 MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false)
333 MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false)
334 MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false)
335 MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false)
336 MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false)
337 MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false)
338 MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false)
339 MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false)
340 MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false)
341 MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false)
342 MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false)
343 MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false)
344 MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false)
345 MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false)
346 MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false)
347 MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false)
348 MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false)
349 MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false)
350 MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false)
351 MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false)
352 MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false)
353 MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false)
354 MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false)
355 MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false)
356 MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false)
357 MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false)
358 MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false)
359 MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false)
360 MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false)
361 MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false)
362 MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false)
363 MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false)
364 MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false)
365 MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false)
366 MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false)
367 MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false)
368 MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false)
369 MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false)
370 MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false)
371 MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false)
372 MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false)
373 MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false)
374 MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false)
375 MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false)
376 MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false)
377 MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false)
378 MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false)
379 MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false)
380 MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false)
381 MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false)
382 MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false)
383 MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false)
384 MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false)
385 MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false)
386 MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false)
387 MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false)
388 MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false)
389 MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false)
390 MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false)
391 MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false)
392 MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false)
393 MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false)
394 MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false)
395 MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false)
396 MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false)
397 MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false)
398 MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false)
399 MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false)
400 MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false)
401 MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false)
402 MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false)
403 MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false)
404 MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false)
405 MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false)
406 MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false)
407 MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false)
408 MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false)
409 MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false)
410 MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false)
411 MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false)
412 MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false)
413 MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false)
414 MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false)
415 MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false)
416 MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false)
417 MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false)
418 MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false)
419 MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false)
420 MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false)
421 MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false)
422 MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false)
423 MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false)
424 MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false)
425 MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false)
426 MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false)
427 MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false)
428 MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false)
429 MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false)
430 MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false)
431 MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false)
432 MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false)
433 MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false)
434 MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false)
435 MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false)
436 MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false)
437 MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false)
438 MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false)
439 MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false)
440 MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false)
441 MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false)
442 MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false)
443 MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false)
444 MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false)
445 MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false)
446 MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false)
447 MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false)
448 #endif
449 };
450
451 const short da830_emif25_pins[] __initconst = {
452 DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
453 DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
454 DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
455 DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
456 DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
457 DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
458 DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
459 DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
460 DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
461 DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
462 DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
463 -1
464 };
465
466 const short da830_spi0_pins[] __initconst = {
467 DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
468 DA830_NSPI0_SCS_0,
469 -1
470 };
471
472 const short da830_spi1_pins[] __initconst = {
473 DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
474 DA830_NSPI1_SCS_0,
475 -1
476 };
477
478 const short da830_mmc_sd_pins[] __initconst = {
479 DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
480 DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
481 DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
482 DA830_MMCSD_CMD,
483 -1
484 };
485
486 const short da830_uart0_pins[] __initconst = {
487 DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
488 -1
489 };
490
491 const short da830_uart1_pins[] __initconst = {
492 DA830_UART1_RXD, DA830_UART1_TXD,
493 -1
494 };
495
496 const short da830_uart2_pins[] __initconst = {
497 DA830_UART2_RXD, DA830_UART2_TXD,
498 -1
499 };
500
501 const short da830_usb20_pins[] __initconst = {
502 DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
503 -1
504 };
505
506 const short da830_usb11_pins[] __initconst = {
507 DA830_USB_REFCLKIN,
508 -1
509 };
510
511 const short da830_uhpi_pins[] __initconst = {
512 DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
513 DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
514 DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
515 DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
516 DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
517 DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
518 DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
519 -1
520 };
521
522 const short da830_cpgmac_pins[] __initconst = {
523 DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
524 DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
525 DA830_MDIO_D,
526 -1
527 };
528
529 const short da830_emif3c_pins[] __initconst = {
530 DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
531 DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
532 DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
533 DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
534 DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
535 DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
536 DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
537 DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
538 DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
539 DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
540 DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
541 DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
542 DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
543 DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
544 DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
545 -1
546 };
547
548 const short da830_mcasp0_pins[] __initconst = {
549 DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
550 DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
551 DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
552 DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
553 DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
554 DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
555 -1
556 };
557
558 const short da830_mcasp1_pins[] __initconst = {
559 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
560 DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
561 DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
562 DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
563 DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
564 -1
565 };
566
567 const short da830_mcasp2_pins[] __initconst = {
568 DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
569 DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
570 DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
571 -1
572 };
573
574 const short da830_i2c0_pins[] __initconst = {
575 DA830_I2C0_SDA, DA830_I2C0_SCL,
576 -1
577 };
578
579 const short da830_i2c1_pins[] __initconst = {
580 DA830_I2C1_SCL, DA830_I2C1_SDA,
581 -1
582 };
583
584 const short da830_lcdcntl_pins[] __initconst = {
585 DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
586 DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
587 DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
588 DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
589 DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
590 DA830_LCD_MCLK,
591 -1
592 };
593
594 const short da830_pwm_pins[] __initconst = {
595 DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
596 DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
597 DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
598 -1
599 };
600
601 const short da830_ecap0_pins[] __initconst = {
602 DA830_ECAP0_APWM0,
603 -1
604 };
605
606 const short da830_ecap1_pins[] __initconst = {
607 DA830_ECAP1_APWM1,
608 -1
609 };
610
611 const short da830_ecap2_pins[] __initconst = {
612 DA830_ECAP2_APWM2,
613 -1
614 };
615
616 const short da830_eqep0_pins[] __initconst = {
617 DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
618 -1
619 };
620
621 const short da830_eqep1_pins[] __initconst = {
622 DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
623 -1
624 };
625
626 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
627 static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
628 [IRQ_DA8XX_COMMTX] = 7,
629 [IRQ_DA8XX_COMMRX] = 7,
630 [IRQ_DA8XX_NINT] = 7,
631 [IRQ_DA8XX_EVTOUT0] = 7,
632 [IRQ_DA8XX_EVTOUT1] = 7,
633 [IRQ_DA8XX_EVTOUT2] = 7,
634 [IRQ_DA8XX_EVTOUT3] = 7,
635 [IRQ_DA8XX_EVTOUT4] = 7,
636 [IRQ_DA8XX_EVTOUT5] = 7,
637 [IRQ_DA8XX_EVTOUT6] = 7,
638 [IRQ_DA8XX_EVTOUT7] = 7,
639 [IRQ_DA8XX_CCINT0] = 7,
640 [IRQ_DA8XX_CCERRINT] = 7,
641 [IRQ_DA8XX_TCERRINT0] = 7,
642 [IRQ_DA8XX_AEMIFINT] = 7,
643 [IRQ_DA8XX_I2CINT0] = 7,
644 [IRQ_DA8XX_MMCSDINT0] = 7,
645 [IRQ_DA8XX_MMCSDINT1] = 7,
646 [IRQ_DA8XX_ALLINT0] = 7,
647 [IRQ_DA8XX_RTC] = 7,
648 [IRQ_DA8XX_SPINT0] = 7,
649 [IRQ_DA8XX_TINT12_0] = 7,
650 [IRQ_DA8XX_TINT34_0] = 7,
651 [IRQ_DA8XX_TINT12_1] = 7,
652 [IRQ_DA8XX_TINT34_1] = 7,
653 [IRQ_DA8XX_UARTINT0] = 7,
654 [IRQ_DA8XX_KEYMGRINT] = 7,
655 [IRQ_DA830_MPUERR] = 7,
656 [IRQ_DA8XX_CHIPINT0] = 7,
657 [IRQ_DA8XX_CHIPINT1] = 7,
658 [IRQ_DA8XX_CHIPINT2] = 7,
659 [IRQ_DA8XX_CHIPINT3] = 7,
660 [IRQ_DA8XX_TCERRINT1] = 7,
661 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
662 [IRQ_DA8XX_C0_RX_PULSE] = 7,
663 [IRQ_DA8XX_C0_TX_PULSE] = 7,
664 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
665 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
666 [IRQ_DA8XX_C1_RX_PULSE] = 7,
667 [IRQ_DA8XX_C1_TX_PULSE] = 7,
668 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
669 [IRQ_DA8XX_MEMERR] = 7,
670 [IRQ_DA8XX_GPIO0] = 7,
671 [IRQ_DA8XX_GPIO1] = 7,
672 [IRQ_DA8XX_GPIO2] = 7,
673 [IRQ_DA8XX_GPIO3] = 7,
674 [IRQ_DA8XX_GPIO4] = 7,
675 [IRQ_DA8XX_GPIO5] = 7,
676 [IRQ_DA8XX_GPIO6] = 7,
677 [IRQ_DA8XX_GPIO7] = 7,
678 [IRQ_DA8XX_GPIO8] = 7,
679 [IRQ_DA8XX_I2CINT1] = 7,
680 [IRQ_DA8XX_LCDINT] = 7,
681 [IRQ_DA8XX_UARTINT1] = 7,
682 [IRQ_DA8XX_MCASPINT] = 7,
683 [IRQ_DA8XX_ALLINT1] = 7,
684 [IRQ_DA8XX_SPINT1] = 7,
685 [IRQ_DA8XX_UHPI_INT1] = 7,
686 [IRQ_DA8XX_USB_INT] = 7,
687 [IRQ_DA8XX_IRQN] = 7,
688 [IRQ_DA8XX_RWAKEUP] = 7,
689 [IRQ_DA8XX_UARTINT2] = 7,
690 [IRQ_DA8XX_DFTSSINT] = 7,
691 [IRQ_DA8XX_EHRPWM0] = 7,
692 [IRQ_DA8XX_EHRPWM0TZ] = 7,
693 [IRQ_DA8XX_EHRPWM1] = 7,
694 [IRQ_DA8XX_EHRPWM1TZ] = 7,
695 [IRQ_DA830_EHRPWM2] = 7,
696 [IRQ_DA830_EHRPWM2TZ] = 7,
697 [IRQ_DA8XX_ECAP0] = 7,
698 [IRQ_DA8XX_ECAP1] = 7,
699 [IRQ_DA8XX_ECAP2] = 7,
700 [IRQ_DA830_EQEP0] = 7,
701 [IRQ_DA830_EQEP1] = 7,
702 [IRQ_DA830_T12CMPINT0_0] = 7,
703 [IRQ_DA830_T12CMPINT1_0] = 7,
704 [IRQ_DA830_T12CMPINT2_0] = 7,
705 [IRQ_DA830_T12CMPINT3_0] = 7,
706 [IRQ_DA830_T12CMPINT4_0] = 7,
707 [IRQ_DA830_T12CMPINT5_0] = 7,
708 [IRQ_DA830_T12CMPINT6_0] = 7,
709 [IRQ_DA830_T12CMPINT7_0] = 7,
710 [IRQ_DA830_T12CMPINT0_1] = 7,
711 [IRQ_DA830_T12CMPINT1_1] = 7,
712 [IRQ_DA830_T12CMPINT2_1] = 7,
713 [IRQ_DA830_T12CMPINT3_1] = 7,
714 [IRQ_DA830_T12CMPINT4_1] = 7,
715 [IRQ_DA830_T12CMPINT5_1] = 7,
716 [IRQ_DA830_T12CMPINT6_1] = 7,
717 [IRQ_DA830_T12CMPINT7_1] = 7,
718 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
719 };
720
721 static struct map_desc da830_io_desc[] = {
722 {
723 .virtual = IO_VIRT,
724 .pfn = __phys_to_pfn(IO_PHYS),
725 .length = IO_SIZE,
726 .type = MT_DEVICE
727 },
728 {
729 .virtual = DA8XX_CP_INTC_VIRT,
730 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
731 .length = DA8XX_CP_INTC_SIZE,
732 .type = MT_DEVICE
733 },
734 };
735
736 /* Contents of JTAG ID register used to identify exact cpu type */
737 static struct davinci_id da830_ids[] = {
738 {
739 .variant = 0x0,
740 .part_no = 0xb7df,
741 .manufacturer = 0x017, /* 0x02f >> 1 */
742 .cpu_id = DAVINCI_CPU_ID_DA830,
743 .name = "da830/omap-l137 rev1.0",
744 },
745 {
746 .variant = 0x8,
747 .part_no = 0xb7df,
748 .manufacturer = 0x017,
749 .cpu_id = DAVINCI_CPU_ID_DA830,
750 .name = "da830/omap-l137 rev1.1",
751 },
752 {
753 .variant = 0x9,
754 .part_no = 0xb7df,
755 .manufacturer = 0x017,
756 .cpu_id = DAVINCI_CPU_ID_DA830,
757 .name = "da830/omap-l137 rev2.0",
758 },
759 };
760
761 static struct davinci_gpio_platform_data da830_gpio_platform_data = {
762 .ngpio = 128,
763 };
764
da830_register_gpio(void)765 int __init da830_register_gpio(void)
766 {
767 return da8xx_register_gpio(&da830_gpio_platform_data);
768 }
769
770 static struct davinci_timer_instance da830_timer_instance[2] = {
771 {
772 .base = DA8XX_TIMER64P0_BASE,
773 .bottom_irq = IRQ_DA8XX_TINT12_0,
774 .top_irq = IRQ_DA8XX_TINT34_0,
775 .cmp_off = DA830_CMP12_0,
776 .cmp_irq = IRQ_DA830_T12CMPINT0_0,
777 },
778 {
779 .base = DA8XX_TIMER64P1_BASE,
780 .bottom_irq = IRQ_DA8XX_TINT12_1,
781 .top_irq = IRQ_DA8XX_TINT34_1,
782 .cmp_off = DA830_CMP12_0,
783 .cmp_irq = IRQ_DA830_T12CMPINT0_1,
784 },
785 };
786
787 /*
788 * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource
789 * T0_TOP: Timer 0, top : Used by DSP
790 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
791 */
792 static struct davinci_timer_info da830_timer_info = {
793 .timers = da830_timer_instance,
794 .clockevent_id = T0_BOT,
795 .clocksource_id = T0_BOT,
796 };
797
798 static const struct davinci_soc_info davinci_soc_info_da830 = {
799 .io_desc = da830_io_desc,
800 .io_desc_num = ARRAY_SIZE(da830_io_desc),
801 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
802 .ids = da830_ids,
803 .ids_num = ARRAY_SIZE(da830_ids),
804 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
805 .pinmux_pins = da830_pins,
806 .pinmux_pins_num = ARRAY_SIZE(da830_pins),
807 .intc_base = DA8XX_CP_INTC_BASE,
808 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
809 .intc_irq_prios = da830_default_priorities,
810 .intc_irq_num = DA830_N_CP_INTC_IRQ,
811 .timer_info = &da830_timer_info,
812 .emac_pdata = &da8xx_emac_pdata,
813 };
814
da830_init(void)815 void __init da830_init(void)
816 {
817 davinci_common_init(&davinci_soc_info_da830);
818
819 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
820 WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
821 }
822
da830_init_time(void)823 void __init da830_init_time(void)
824 {
825 void __iomem *pll;
826 struct clk *clk;
827
828 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
829
830 pll = ioremap(DA8XX_PLL0_BASE, SZ_4K);
831
832 da830_pll_init(NULL, pll, NULL);
833
834 clk = clk_get(NULL, "timer0");
835
836 davinci_timer_init(clk);
837 }
838
839 static struct resource da830_psc0_resources[] = {
840 {
841 .start = DA8XX_PSC0_BASE,
842 .end = DA8XX_PSC0_BASE + SZ_4K - 1,
843 .flags = IORESOURCE_MEM,
844 },
845 };
846
847 static struct platform_device da830_psc0_device = {
848 .name = "da830-psc0",
849 .id = -1,
850 .resource = da830_psc0_resources,
851 .num_resources = ARRAY_SIZE(da830_psc0_resources),
852 };
853
854 static struct resource da830_psc1_resources[] = {
855 {
856 .start = DA8XX_PSC1_BASE,
857 .end = DA8XX_PSC1_BASE + SZ_4K - 1,
858 .flags = IORESOURCE_MEM,
859 },
860 };
861
862 static struct platform_device da830_psc1_device = {
863 .name = "da830-psc1",
864 .id = -1,
865 .resource = da830_psc1_resources,
866 .num_resources = ARRAY_SIZE(da830_psc1_resources),
867 };
868
da830_register_clocks(void)869 void __init da830_register_clocks(void)
870 {
871 /* PLL is registered in da830_init_time() */
872 platform_device_register(&da830_psc0_device);
873 platform_device_register(&da830_psc1_device);
874 }
875
