1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Joe.C <yingjoe.chen@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include "skeleton64.dtsi"
11
12/ {
13	compatible = "mediatek,mt8127";
14	interrupt-parent = <&sysirq>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		enable-method = "mediatek,mt81xx-tz-smp";
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a7";
24			reg = <0x0>;
25		};
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a7";
29			reg = <0x1>;
30		};
31		cpu@2 {
32			device_type = "cpu";
33			compatible = "arm,cortex-a7";
34			reg = <0x2>;
35		};
36		cpu@3 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a7";
39			reg = <0x3>;
40		};
41
42	};
43
44	reserved-memory {
45		#address-cells = <2>;
46		#size-cells = <2>;
47		ranges;
48
49		trustzone-bootinfo@80002000 {
50			compatible = "mediatek,trustzone-bootinfo";
51			reg = <0 0x80002000 0 0x1000>;
52		};
53	};
54
55	clocks {
56		#address-cells = <2>;
57		#size-cells = <2>;
58		compatible = "simple-bus";
59		ranges;
60
61		system_clk: dummy13m {
62			compatible = "fixed-clock";
63			clock-frequency = <13000000>;
64			#clock-cells = <0>;
65		};
66
67		rtc_clk: dummy32k {
68			compatible = "fixed-clock";
69			clock-frequency = <32000>;
70			#clock-cells = <0>;
71		};
72
73		uart_clk: dummy26m {
74			compatible = "fixed-clock";
75			clock-frequency = <26000000>;
76			#clock-cells = <0>;
77                };
78	};
79
80	timer {
81		compatible = "arm,armv7-timer";
82		interrupt-parent = <&gic>;
83		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
84					  IRQ_TYPE_LEVEL_LOW)>,
85			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
86					  IRQ_TYPE_LEVEL_LOW)>,
87			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
88					  IRQ_TYPE_LEVEL_LOW)>,
89			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
90					  IRQ_TYPE_LEVEL_LOW)>;
91		clock-frequency = <13000000>;
92		arm,cpu-registers-not-fw-configured;
93	};
94
95	soc {
96		#address-cells = <2>;
97		#size-cells = <2>;
98		compatible = "simple-bus";
99		ranges;
100
101		timer: timer@10008000 {
102			compatible = "mediatek,mt8127-timer",
103					"mediatek,mt6577-timer";
104			reg = <0 0x10008000 0 0x80>;
105			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
106			clocks = <&system_clk>, <&rtc_clk>;
107			clock-names = "system-clk", "rtc-clk";
108		};
109
110		sysirq: interrupt-controller@10200100 {
111			compatible = "mediatek,mt8127-sysirq",
112				     "mediatek,mt6577-sysirq";
113			interrupt-controller;
114			#interrupt-cells = <3>;
115			interrupt-parent = <&gic>;
116			reg = <0 0x10200100 0 0x1c>;
117		};
118
119		gic: interrupt-controller@10211000 {
120			compatible = "arm,cortex-a7-gic";
121			interrupt-controller;
122			#interrupt-cells = <3>;
123			interrupt-parent = <&gic>;
124			reg = <0 0x10211000 0 0x1000>,
125			      <0 0x10212000 0 0x2000>,
126			      <0 0x10214000 0 0x2000>,
127			      <0 0x10216000 0 0x2000>;
128		};
129
130		uart0: serial@11002000 {
131			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
132			reg = <0 0x11002000 0 0x400>;
133			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
134			clocks = <&uart_clk>;
135			status = "disabled";
136		};
137
138		uart1: serial@11003000 {
139			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
140			reg = <0 0x11003000 0 0x400>;
141			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
142			clocks = <&uart_clk>;
143			status = "disabled";
144		};
145
146		uart2: serial@11004000 {
147			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
148			reg = <0 0x11004000 0 0x400>;
149			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
150			clocks = <&uart_clk>;
151			status = "disabled";
152		};
153
154		uart3: serial@11005000 {
155			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
156			reg = <0 0x11005000 0 0x400>;
157			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
158			clocks = <&uart_clk>;
159			status = "disabled";
160		};
161	};
162};
163