1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Mars.C <mars.cheng@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include "skeleton.dtsi"
11
12/ {
13	compatible = "mediatek,mt6580";
14	#address-cells = <1>;
15	#size-cells = <1>;
16	interrupt-parent = <&sysirq>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a7";
25			reg = <0x0>;
26		};
27		cpu@1 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a7";
30			reg = <0x1>;
31		};
32		cpu@2 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a7";
35			reg = <0x2>;
36		};
37		cpu@3 {
38			device_type = "cpu";
39			compatible = "arm,cortex-a7";
40			reg = <0x3>;
41		};
42
43	};
44
45	system_clk: dummy13m {
46		compatible = "fixed-clock";
47		clock-frequency = <13000000>;
48		#clock-cells = <0>;
49	};
50
51	rtc_clk: dummy32k {
52		compatible = "fixed-clock";
53		clock-frequency = <32000>;
54		#clock-cells = <0>;
55	};
56
57	uart_clk: dummy26m {
58		compatible = "fixed-clock";
59		clock-frequency = <26000000>;
60		#clock-cells = <0>;
61	};
62
63	timer: timer@10008000 {
64		compatible = "mediatek,mt6580-timer",
65			     "mediatek,mt6577-timer";
66		reg = <0x10008000 0x80>;
67		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
68		clocks = <&system_clk>, <&rtc_clk>;
69		clock-names = "system-clk", "rtc-clk";
70	};
71
72	sysirq: interrupt-controller@10200100 {
73		compatible = "mediatek,mt6580-sysirq",
74			     "mediatek,mt6577-sysirq";
75		interrupt-controller;
76		#interrupt-cells = <3>;
77		interrupt-parent = <&gic>;
78		reg = <0x10200100 0x1c>;
79	};
80
81	gic: interrupt-controller@10211000 {
82		compatible = "arm,cortex-a7-gic";
83		interrupt-controller;
84		#interrupt-cells = <3>;
85		interrupt-parent = <&gic>;
86		reg = <0x10211000 0x1000>,
87		      <0x10212000 0x2000>,
88		      <0x10214000 0x2000>,
89		      <0x10216000 0x2000>;
90	};
91
92	uart0: serial@11005000 {
93		compatible = "mediatek,mt6580-uart",
94			     "mediatek,mt6577-uart";
95		reg = <0x11005000 0x400>;
96		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
97		clocks = <&uart_clk>;
98		status = "disabled";
99	};
100
101	uart1: serial@11006000 {
102		compatible = "mediatek,mt6580-uart",
103			     "mediatek,mt6577-uart";
104		reg = <0x11006000 0x400>;
105		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
106		clocks = <&uart_clk>;
107		status = "disabled";
108	};
109};
110