1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2014 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6
7#include "imx6sx.dtsi"
8
9/ {
10	model = "Freescale i.MX6 SoloX Sabre Auto Board";
11	compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
12
13	memory@80000000 {
14		reg = <0x80000000 0x80000000>;
15	};
16
17	leds {
18		compatible = "gpio-leds";
19		pinctrl-names = "default";
20		pinctrl-0 = <&pinctrl_led>;
21
22		user {
23			label = "debug";
24			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
25			linux,default-trigger = "heartbeat";
26		};
27	};
28
29	vcc_sd3: regulator-vcc-sd3 {
30		compatible = "regulator-fixed";
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_vcc_sd3>;
33		regulator-name = "VCC_SD3";
34		regulator-min-microvolt = <3000000>;
35		regulator-max-microvolt = <3000000>;
36		gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
37		enable-active-high;
38	};
39};
40
41&anaclk2 {
42	clock-frequency = <24576000>;
43};
44
45&fec1 {
46	pinctrl-names = "default";
47	pinctrl-0 = <&pinctrl_enet1>;
48	phy-mode = "rgmii";
49	phy-handle = <&ethphy1>;
50	fsl,magic-packet;
51	status = "okay";
52
53	mdio {
54		#address-cells = <1>;
55		#size-cells = <0>;
56
57		ethphy0: ethernet-phy@0 {
58			compatible = "ethernet-phy-ieee802.3-c22";
59			reg = <0>;
60		};
61
62		ethphy1: ethernet-phy@1 {
63			compatible = "ethernet-phy-ieee802.3-c22";
64			reg = <1>;
65		};
66	};
67};
68
69&fec2 {
70	pinctrl-names = "default";
71	pinctrl-0 = <&pinctrl_enet2>;
72	phy-mode = "rgmii";
73	phy-handle = <&ethphy0>;
74	fsl,magic-packet;
75	status = "okay";
76};
77
78&uart1 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_uart1>;
81	status = "okay";
82};
83
84&usdhc3 {
85	pinctrl-names = "default", "state_100mhz", "state_200mhz";
86	pinctrl-0 = <&pinctrl_usdhc3>;
87	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
88	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
89	bus-width = <8>;
90	cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
91	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
92	keep-power-in-suspend;
93	wakeup-source;
94	vmmc-supply = <&vcc_sd3>;
95	status = "okay";
96};
97
98&usdhc4 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_usdhc4>;
101	bus-width = <8>;
102	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
103	no-1-8-v;
104	keep-power-in-suspend;
105	wakeup-source;
106	status = "okay";
107};
108
109&iomuxc {
110	pinctrl_egalax_int: egalax-intgrp {
111		fsl,pins = <
112			MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22      0x10b0
113		>;
114	};
115
116	pinctrl_enet1: enet1grp {
117		fsl,pins = <
118			MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
119			MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
120			MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
121			MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
122			MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
123			MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
124			MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
125			MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
126			MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
127			MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
128			MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
129			MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
130			MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
131			MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
132		>;
133	};
134
135	pinctrl_enet2: enet2grp {
136		fsl,pins = <
137			MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
138			MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
139			MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
140			MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
141			MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
142			MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
143			MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
144			MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
145			MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
146			MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
147			MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
148			MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
149		>;
150	};
151
152	pinctrl_i2c2: i2c2grp {
153		fsl,pins = <
154			MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
155			MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
156		>;
157	};
158
159	pinctrl_i2c3: i2c3grp {
160		fsl,pins = <
161			MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
162			MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
163		>;
164	};
165
166	pinctrl_led: ledgrp {
167		fsl,pins = <
168			MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
169		>;
170	};
171
172	pinctrl_uart1: uart1grp {
173		fsl,pins = <
174			MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
175			MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
176		>;
177	};
178
179	pinctrl_usdhc3: usdhc3grp {
180		fsl,pins = <
181			MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17059
182			MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x10059
183			MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x17059
184			MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x17059
185			MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x17059
186			MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x17059
187			MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x17059
188			MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x17059
189			MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x17059
190			MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x17059
191			MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x17059 /* CD */
192			MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x17059 /* WP */
193		>;
194	};
195
196	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
197		fsl,pins = <
198			MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170b9
199			MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100b9
200			MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170b9
201			MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170b9
202			MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170b9
203			MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170b9
204			MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170b9
205			MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170b9
206			MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170b9
207			MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170b9
208		>;
209	};
210
211	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
212		fsl,pins = <
213			MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170f9
214			MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100f9
215			MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170f9
216			MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170f9
217			MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170f9
218			MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170f9
219			MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170f9
220			MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170f9
221			MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170f9
222			MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170f9
223		>;
224	};
225
226	pinctrl_usdhc4: usdhc4grp {
227		fsl,pins = <
228			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
229			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
230			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
231			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
232			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
233			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
234			MX6SX_PAD_SD4_DATA7__GPIO6_IO_21	0x17059 /* CD */
235			MX6SX_PAD_SD4_DATA6__GPIO6_IO_20	0x17059 /* WP */
236		>;
237	};
238
239	pinctrl_vcc_sd3: vccsd3grp {
240		fsl,pins = <
241			MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
242		>;
243	};
244
245	pinctrl_wdog: wdoggrp {
246		fsl,pins = <
247			MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY	0x30b0
248		>;
249	};
250};
251
252&i2c2 {
253	clock-frequency = <100000>;
254	pinctrl-names = "default";
255	pinctrl-0 = <&pinctrl_i2c2>;
256	status = "okay";
257
258	touchscreen@4 {
259		compatible = "eeti,egalax_ts";
260		reg = <0x04>;
261		pinctrl-names = "default";
262		pinctrl-0 = <&pinctrl_egalax_int>;
263		interrupt-parent = <&gpio6>;
264		interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
265		wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
266	};
267
268	pfuze100: pmic@8 {
269		compatible = "fsl,pfuze100";
270		reg = <0x08>;
271
272		regulators {
273			sw1a_reg: sw1ab {
274				regulator-min-microvolt = <300000>;
275				regulator-max-microvolt = <1875000>;
276				regulator-boot-on;
277				regulator-always-on;
278				regulator-ramp-delay = <6250>;
279			};
280
281			sw1c_reg: sw1c {
282				regulator-min-microvolt = <300000>;
283				regulator-max-microvolt = <1875000>;
284				regulator-boot-on;
285				regulator-always-on;
286				regulator-ramp-delay = <6250>;
287			};
288
289			sw2_reg: sw2 {
290				regulator-min-microvolt = <800000>;
291				regulator-max-microvolt = <3300000>;
292				regulator-boot-on;
293				regulator-always-on;
294			};
295
296			sw3a_reg: sw3a {
297				regulator-min-microvolt = <400000>;
298				regulator-max-microvolt = <1975000>;
299				regulator-boot-on;
300				regulator-always-on;
301			};
302
303			sw3b_reg: sw3b {
304				regulator-min-microvolt = <400000>;
305				regulator-max-microvolt = <1975000>;
306				regulator-boot-on;
307				regulator-always-on;
308			};
309
310			sw4_reg: sw4 {
311				regulator-min-microvolt = <800000>;
312				regulator-max-microvolt = <3300000>;
313				regulator-always-on;
314			};
315
316			swbst_reg: swbst {
317				regulator-min-microvolt = <5000000>;
318				regulator-max-microvolt = <5150000>;
319			};
320
321			snvs_reg: vsnvs {
322				regulator-min-microvolt = <1000000>;
323				regulator-max-microvolt = <3000000>;
324				regulator-boot-on;
325				regulator-always-on;
326			};
327
328			vref_reg: vrefddr {
329				regulator-boot-on;
330				regulator-always-on;
331			};
332
333			vgen1_reg: vgen1 {
334				regulator-min-microvolt = <800000>;
335				regulator-max-microvolt = <1550000>;
336				regulator-always-on;
337			};
338
339			vgen2_reg: vgen2 {
340				regulator-min-microvolt = <800000>;
341				regulator-max-microvolt = <1550000>;
342			};
343
344			vgen3_reg: vgen3 {
345				regulator-min-microvolt = <1800000>;
346				regulator-max-microvolt = <3300000>;
347				regulator-always-on;
348			};
349
350			vgen4_reg: vgen4 {
351				regulator-min-microvolt = <1800000>;
352				regulator-max-microvolt = <3300000>;
353				regulator-always-on;
354			};
355
356			vgen5_reg: vgen5 {
357				regulator-min-microvolt = <1800000>;
358				regulator-max-microvolt = <3300000>;
359				regulator-always-on;
360			};
361
362			vgen6_reg: vgen6 {
363				regulator-min-microvolt = <1800000>;
364				regulator-max-microvolt = <3300000>;
365				regulator-always-on;
366			};
367		};
368	};
369
370	max7322: gpio@68 {
371		compatible = "maxim,max7322";
372		reg = <0x68>;
373		gpio-controller;
374		#gpio-cells = <2>;
375	};
376};
377
378&i2c3 {
379	clock-frequency = <100000>;
380	pinctrl-names = "default";
381	pinctrl-0 = <&pinctrl_i2c3>;
382	status = "okay";
383
384	max7310_a: gpio@30 {
385		compatible = "maxim,max7310";
386		reg = <0x30>;
387		gpio-controller;
388		#gpio-cells = <2>;
389	};
390
391	max7310_b: gpio@32 {
392		compatible = "maxim,max7310";
393		reg = <0x32>;
394		gpio-controller;
395		#gpio-cells = <2>;
396	};
397};
398
399&wdog1 {
400	pinctrl-names = "default";
401	pinctrl-0 = <&pinctrl_wdog>;
402	fsl,ext-reset-output;
403};
404