1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP. 5 * 6 */ 7 8#include <dt-bindings/clock/imx6sll-clock.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include "imx6sll-pinfunc.h" 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 aliases { 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 gpio3 = &gpio4; 22 gpio4 = &gpio5; 23 gpio5 = &gpio6; 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 mmc0 = &usdhc1; 28 mmc1 = &usdhc2; 29 mmc2 = &usdhc3; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 spi0 = &ecspi1; 36 spi1 = &ecspi2; 37 spi3 = &ecspi3; 38 spi4 = &ecspi4; 39 usbphy0 = &usbphy1; 40 usbphy1 = &usbphy2; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 compatible = "arm,cortex-a9"; 49 device_type = "cpu"; 50 reg = <0>; 51 next-level-cache = <&L2>; 52 operating-points = < 53 /* kHz uV */ 54 996000 1275000 55 792000 1175000 56 396000 1075000 57 198000 975000 58 >; 59 fsl,soc-operating-points = < 60 /* ARM kHz SOC-PU uV */ 61 996000 1175000 62 792000 1175000 63 396000 1175000 64 198000 1175000 65 >; 66 clock-latency = <61036>; /* two CLK32 periods */ 67 clocks = <&clks IMX6SLL_CLK_ARM>, 68 <&clks IMX6SLL_CLK_PLL2_PFD2>, 69 <&clks IMX6SLL_CLK_STEP>, 70 <&clks IMX6SLL_CLK_PLL1_SW>, 71 <&clks IMX6SLL_CLK_PLL1_SYS>; 72 clock-names = "arm", "pll2_pfd2_396m", "step", 73 "pll1_sw", "pll1_sys"; 74 }; 75 }; 76 77 intc: interrupt-controller@a01000 { 78 compatible = "arm,cortex-a9-gic"; 79 #interrupt-cells = <3>; 80 interrupt-controller; 81 reg = <0x00a01000 0x1000>, 82 <0x00a00100 0x100>; 83 interrupt-parent = <&intc>; 84 }; 85 86 ckil: clock-ckil { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <32768>; 90 clock-output-names = "ckil"; 91 }; 92 93 osc: clock-osc-24m { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <24000000>; 97 clock-output-names = "osc"; 98 }; 99 100 ipp_di0: clock-ipp-di0 { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <0>; 104 clock-output-names = "ipp_di0"; 105 }; 106 107 ipp_di1: clock-ipp-di1 { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <0>; 111 clock-output-names = "ipp_di1"; 112 }; 113 114 tempmon: temperature-sensor { 115 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; 116 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 117 interrupt-parent = <&gpc>; 118 fsl,tempmon = <&anatop>; 119 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 120 nvmem-cell-names = "calib", "temp_grade"; 121 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; 122 }; 123 124 soc { 125 #address-cells = <1>; 126 #size-cells = <1>; 127 compatible = "simple-bus"; 128 interrupt-parent = <&gpc>; 129 ranges; 130 131 ocram: sram@900000 { 132 compatible = "mmio-sram"; 133 reg = <0x00900000 0x20000>; 134 }; 135 136 L2: l2-cache@a02000 { 137 compatible = "arm,pl310-cache"; 138 reg = <0x00a02000 0x1000>; 139 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 140 cache-unified; 141 cache-level = <2>; 142 arm,tag-latency = <4 2 3>; 143 arm,data-latency = <4 2 3>; 144 }; 145 146 aips1: aips-bus@2000000 { 147 compatible = "fsl,aips-bus", "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 reg = <0x02000000 0x100000>; 151 ranges; 152 153 spba: spba-bus@2000000 { 154 compatible = "fsl,spba-bus", "simple-bus"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 reg = <0x02000000 0x40000>; 158 ranges; 159 160 spdif: spdif@2004000 { 161 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; 162 reg = <0x02004000 0x4000>; 163 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 164 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; 165 dma-names = "rx", "tx"; 166 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, 167 <&clks IMX6SLL_CLK_OSC>, 168 <&clks IMX6SLL_CLK_SPDIF>, 169 <&clks IMX6SLL_CLK_DUMMY>, 170 <&clks IMX6SLL_CLK_DUMMY>, 171 <&clks IMX6SLL_CLK_DUMMY>, 172 <&clks IMX6SLL_CLK_IPG>, 173 <&clks IMX6SLL_CLK_DUMMY>, 174 <&clks IMX6SLL_CLK_DUMMY>, 175 <&clks IMX6SLL_CLK_SPBA>; 176 clock-names = "core", "rxtx0", 177 "rxtx1", "rxtx2", 178 "rxtx3", "rxtx4", 179 "rxtx5", "rxtx6", 180 "rxtx7", "dma"; 181 status = "disabled"; 182 }; 183 184 ecspi1: spi@2008000 { 185 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 186 reg = <0x02008000 0x4000>; 187 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 188 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 189 dma-names = "rx", "tx"; 190 clocks = <&clks IMX6SLL_CLK_ECSPI1>, 191 <&clks IMX6SLL_CLK_ECSPI1>; 192 clock-names = "ipg", "per"; 193 status = "disabled"; 194 }; 195 196 ecspi2: spi@200c000 { 197 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 198 reg = <0x0200c000 0x4000>; 199 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 200 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 201 dma-names = "rx", "tx"; 202 clocks = <&clks IMX6SLL_CLK_ECSPI2>, 203 <&clks IMX6SLL_CLK_ECSPI2>; 204 clock-names = "ipg", "per"; 205 status = "disabled"; 206 }; 207 208 ecspi3: spi@2010000 { 209 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 210 reg = <0x02010000 0x4000>; 211 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 212 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 213 dma-names = "rx", "tx"; 214 clocks = <&clks IMX6SLL_CLK_ECSPI3>, 215 <&clks IMX6SLL_CLK_ECSPI3>; 216 clock-names = "ipg", "per"; 217 status = "disabled"; 218 }; 219 220 ecspi4: spi@2014000 { 221 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 222 reg = <0x02014000 0x4000>; 223 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 224 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 225 dma-names = "rx", "tx"; 226 clocks = <&clks IMX6SLL_CLK_ECSPI4>, 227 <&clks IMX6SLL_CLK_ECSPI4>; 228 clock-names = "ipg", "per"; 229 status = "disabled"; 230 }; 231 232 uart4: serial@2018000 { 233 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 234 "fsl,imx21-uart"; 235 reg = <0x02018000 0x4000>; 236 interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 237 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 238 dma-names = "rx", "tx"; 239 clocks = <&clks IMX6SLL_CLK_UART4_IPG>, 240 <&clks IMX6SLL_CLK_UART4_SERIAL>; 241 clock-names = "ipg", "per"; 242 status = "disabled"; 243 }; 244 245 uart1: serial@2020000 { 246 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 247 "fsl,imx21-uart"; 248 reg = <0x02020000 0x4000>; 249 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 250 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 251 dma-names = "rx", "tx"; 252 clocks = <&clks IMX6SLL_CLK_UART1_IPG>, 253 <&clks IMX6SLL_CLK_UART1_SERIAL>; 254 clock-names = "ipg", "per"; 255 status = "disabled"; 256 }; 257 258 uart2: serial@2024000 { 259 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 260 "fsl,imx21-uart"; 261 reg = <0x02024000 0x4000>; 262 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 263 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 264 dma-names = "rx", "tx"; 265 clocks = <&clks IMX6SLL_CLK_UART2_IPG>, 266 <&clks IMX6SLL_CLK_UART2_SERIAL>; 267 clock-names = "ipg", "per"; 268 status = "disabled"; 269 }; 270 271 ssi1: ssi-controller@2028000 { 272 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 273 reg = <0x02028000 0x4000>; 274 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 275 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; 276 dma-names = "rx", "tx"; 277 fsl,fifo-depth = <15>; 278 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, 279 <&clks IMX6SLL_CLK_SSI1>; 280 clock-names = "ipg", "baud"; 281 status = "disabled"; 282 }; 283 284 ssi2: ssi-controller@202c000 { 285 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 286 reg = <0x0202c000 0x4000>; 287 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 288 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; 289 dma-names = "rx", "tx"; 290 fsl,fifo-depth = <15>; 291 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, 292 <&clks IMX6SLL_CLK_SSI2>; 293 clock-names = "ipg", "baud"; 294 status = "disabled"; 295 }; 296 297 ssi3: ssi-controller@2030000 { 298 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 299 reg = <0x02030000 0x4000>; 300 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 301 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; 302 dma-names = "rx", "tx"; 303 fsl,fifo-depth = <15>; 304 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, 305 <&clks IMX6SLL_CLK_SSI3>; 306 clock-names = "ipg", "baud"; 307 status = "disabled"; 308 }; 309 310 uart3: serial@2034000 { 311 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 312 "fsl,imx21-uart"; 313 reg = <0x02034000 0x4000>; 314 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 315 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 316 dma-name = "rx", "tx"; 317 clocks = <&clks IMX6SLL_CLK_UART3_IPG>, 318 <&clks IMX6SLL_CLK_UART3_SERIAL>; 319 clock-names = "ipg", "per"; 320 status = "disabled"; 321 }; 322 }; 323 324 pwm1: pwm@2080000 { 325 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 326 reg = <0x02080000 0x4000>; 327 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clks IMX6SLL_CLK_PWM1>, 329 <&clks IMX6SLL_CLK_PWM1>; 330 clock-names = "ipg", "per"; 331 #pwm-cells = <2>; 332 }; 333 334 pwm2: pwm@2084000 { 335 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 336 reg = <0x02084000 0x4000>; 337 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&clks IMX6SLL_CLK_PWM2>, 339 <&clks IMX6SLL_CLK_PWM2>; 340 clock-names = "ipg", "per"; 341 #pwm-cells = <2>; 342 }; 343 344 pwm3: pwm@2088000 { 345 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 346 reg = <0x02088000 0x4000>; 347 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clks IMX6SLL_CLK_PWM3>, 349 <&clks IMX6SLL_CLK_PWM3>; 350 clock-names = "ipg", "per"; 351 #pwm-cells = <2>; 352 }; 353 354 pwm4: pwm@208c000 { 355 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 356 reg = <0x0208c000 0x4000>; 357 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clks IMX6SLL_CLK_PWM4>, 359 <&clks IMX6SLL_CLK_PWM4>; 360 clock-names = "ipg", "per"; 361 #pwm-cells = <2>; 362 }; 363 364 gpt1: timer@2098000 { 365 compatible = "fsl,imx6sl-gpt"; 366 reg = <0x02098000 0x4000>; 367 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&clks IMX6SLL_CLK_GPT_BUS>, 369 <&clks IMX6SLL_CLK_GPT_SERIAL>; 370 clock-names = "ipg", "per"; 371 }; 372 373 gpio1: gpio@209c000 { 374 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 375 reg = <0x0209c000 0x4000>; 376 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 }; 383 384 gpio2: gpio@20a0000 { 385 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 386 reg = <0x020a0000 0x4000>; 387 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 }; 394 395 gpio3: gpio@20a4000 { 396 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 397 reg = <0x020a4000 0x4000>; 398 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 }; 405 406 gpio4: gpio@20a8000 { 407 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 408 reg = <0x020a8000 0x4000>; 409 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 interrupt-controller; 414 #interrupt-cells = <2>; 415 }; 416 417 gpio5: gpio@20ac000 { 418 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 419 reg = <0x020ac000 0x4000>; 420 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 422 gpio-controller; 423 #gpio-cells = <2>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 428 gpio6: gpio@20b0000 { 429 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 430 reg = <0x020b0000 0x4000>; 431 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 439 kpp: keypad@20b8000 { 440 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; 441 reg = <0x020b8000 0x4000>; 442 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clks IMX6SLL_CLK_KPP>; 444 status = "disabled"; 445 }; 446 447 wdog1: watchdog@20bc000 { 448 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; 449 reg = <0x020bc000 0x4000>; 450 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clks IMX6SLL_CLK_WDOG1>; 452 }; 453 454 wdog2: watchdog@20c0000 { 455 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; 456 reg = <0x020c0000 0x4000>; 457 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clks IMX6SLL_CLK_WDOG2>; 459 status = "disabled"; 460 }; 461 462 clks: clock-controller@20c4000 { 463 compatible = "fsl,imx6sll-ccm"; 464 reg = <0x020c4000 0x4000>; 465 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 467 #clock-cells = <1>; 468 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 469 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 470 471 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; 472 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; 473 }; 474 475 anatop: anatop@20c8000 { 476 compatible = "fsl,imx6sll-anatop", 477 "fsl,imx6q-anatop", 478 "syscon", "simple-bus"; 479 reg = <0x020c8000 0x4000>; 480 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 reg_3p0: regulator-3p0@20c8120 { 487 compatible = "fsl,anatop-regulator"; 488 reg = <0x20c8120>; 489 regulator-name = "vdd3p0"; 490 regulator-min-microvolt = <2625000>; 491 regulator-max-microvolt = <3400000>; 492 anatop-reg-offset = <0x120>; 493 anatop-vol-bit-shift = <8>; 494 anatop-vol-bit-width = <5>; 495 anatop-min-bit-val = <0>; 496 anatop-min-voltage = <2625000>; 497 anatop-max-voltage = <3400000>; 498 anatop-enable-bit = <0>; 499 }; 500 }; 501 502 usbphy1: usb-phy@20c9000 { 503 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", 504 "fsl,imx23-usbphy"; 505 reg = <0x020c9000 0x1000>; 506 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&clks IMX6SLL_CLK_USBPHY1>; 508 phy-3p0-supply = <®_3p0>; 509 fsl,anatop = <&anatop>; 510 }; 511 512 usbphy2: usb-phy@20ca000 { 513 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", 514 "fsl,imx23-usbphy"; 515 reg = <0x020ca000 0x1000>; 516 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clks IMX6SLL_CLK_USBPHY2>; 518 phy-reg_3p0-supply = <®_3p0>; 519 fsl,anatop = <&anatop>; 520 }; 521 522 snvs: snvs@20cc000 { 523 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 524 reg = <0x020cc000 0x4000>; 525 526 snvs_rtc: snvs-rtc-lp { 527 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 528 regmap = <&snvs>; 529 offset = <0x34>; 530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 532 }; 533 534 snvs_poweroff: snvs-poweroff { 535 compatible = "syscon-poweroff"; 536 regmap = <&snvs>; 537 offset = <0x38>; 538 mask = <0x61>; 539 }; 540 541 snvs_pwrkey: snvs-powerkey { 542 compatible = "fsl,sec-v4.0-pwrkey"; 543 regmap = <&snvs>; 544 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 545 linux,keycode = <KEY_POWER>; 546 wakeup-source; 547 }; 548 }; 549 550 src: reset-controller@20d8000 { 551 compatible = "fsl,imx6sll-src", "fsl,imx51-src"; 552 reg = <0x020d8000 0x4000>; 553 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 555 #reset-cells = <1>; 556 }; 557 558 gpc: interrupt-controller@20dc000 { 559 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; 560 reg = <0x020dc000 0x4000>; 561 interrupt-controller; 562 #interrupt-cells = <3>; 563 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-parent = <&intc>; 565 fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; 566 }; 567 568 iomuxc: pinctrl@20e0000 { 569 compatible = "fsl,imx6sll-iomuxc"; 570 reg = <0x020e0000 0x4000>; 571 }; 572 573 gpr: iomuxc-gpr@20e4000 { 574 compatible = "fsl,imx6sll-iomuxc-gpr", 575 "fsl,imx6q-iomuxc-gpr", "syscon"; 576 reg = <0x020e4000 0x4000>; 577 }; 578 579 csi: csi@20e8000 { 580 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; 581 reg = <0x020e8000 0x4000>; 582 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clks IMX6SLL_CLK_DUMMY>, 584 <&clks IMX6SLL_CLK_CSI>, 585 <&clks IMX6SLL_CLK_DUMMY>; 586 clock-names = "disp-axi", "csi_mclk", "disp_dcic"; 587 status = "disabled"; 588 }; 589 590 sdma: dma-controller@20ec000 { 591 compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; 592 reg = <0x020ec000 0x4000>; 593 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clks IMX6SLL_CLK_SDMA>, 595 <&clks IMX6SLL_CLK_SDMA>; 596 clock-names = "ipg", "ahb"; 597 #dma-cells = <3>; 598 iram = <&ocram>; 599 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 600 }; 601 602 lcdif: lcd-controller@20f8000 { 603 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; 604 reg = <0x020f8000 0x4000>; 605 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, 607 <&clks IMX6SLL_CLK_LCDIF_APB>, 608 <&clks IMX6SLL_CLK_DUMMY>; 609 clock-names = "pix", "axi", "disp_axi"; 610 status = "disabled"; 611 }; 612 613 dcp: dcp@20fc000 { 614 compatible = "fsl,imx28-dcp"; 615 reg = <0x020fc000 0x4000>; 616 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clks IMX6SLL_CLK_DCP>; 620 clock-names = "dcp"; 621 }; 622 }; 623 624 aips2: aips-bus@2100000 { 625 compatible = "fsl,aips-bus", "simple-bus"; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 reg = <0x02100000 0x100000>; 629 ranges; 630 631 usbotg1: usb@2184000 { 632 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", 633 "fsl,imx27-usb"; 634 reg = <0x02184000 0x200>; 635 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&clks IMX6SLL_CLK_USBOH3>; 637 fsl,usbphy = <&usbphy1>; 638 fsl,usbmisc = <&usbmisc 0>; 639 fsl,anatop = <&anatop>; 640 ahb-burst-config = <0x0>; 641 tx-burst-size-dword = <0x10>; 642 rx-burst-size-dword = <0x10>; 643 status = "disabled"; 644 }; 645 646 usbotg2: usb@2184200 { 647 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", 648 "fsl,imx27-usb"; 649 reg = <0x02184200 0x200>; 650 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clks IMX6SLL_CLK_USBOH3>; 652 fsl,usbphy = <&usbphy2>; 653 fsl,usbmisc = <&usbmisc 1>; 654 ahb-burst-config = <0x0>; 655 tx-burst-size-dword = <0x10>; 656 rx-burst-size-dword = <0x10>; 657 status = "disabled"; 658 }; 659 660 usbmisc: usbmisc@2184800 { 661 #index-cells = <1>; 662 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", 663 "fsl,imx6q-usbmisc"; 664 reg = <0x02184800 0x200>; 665 }; 666 667 usdhc1: mmc@2190000 { 668 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 669 reg = <0x02190000 0x4000>; 670 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&clks IMX6SLL_CLK_USDHC1>, 672 <&clks IMX6SLL_CLK_USDHC1>, 673 <&clks IMX6SLL_CLK_USDHC1>; 674 clock-names = "ipg", "ahb", "per"; 675 bus-width = <4>; 676 fsl,tuning-step = <2>; 677 fsl,tuning-start-tap = <20>; 678 status = "disabled"; 679 }; 680 681 usdhc2: mmc@2194000 { 682 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 683 reg = <0x02194000 0x4000>; 684 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&clks IMX6SLL_CLK_USDHC2>, 686 <&clks IMX6SLL_CLK_USDHC2>, 687 <&clks IMX6SLL_CLK_USDHC2>; 688 clock-names = "ipg", "ahb", "per"; 689 bus-width = <4>; 690 fsl,tuning-step = <2>; 691 fsl,tuning-start-tap = <20>; 692 status = "disabled"; 693 }; 694 695 usdhc3: mmc@2198000 { 696 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 697 reg = <0x02198000 0x4000>; 698 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&clks IMX6SLL_CLK_USDHC3>, 700 <&clks IMX6SLL_CLK_USDHC3>, 701 <&clks IMX6SLL_CLK_USDHC3>; 702 clock-names = "ipg", "ahb", "per"; 703 bus-width = <4>; 704 fsl,tuning-step = <2>; 705 fsl,tuning-start-tap = <20>; 706 status = "disabled"; 707 }; 708 709 i2c1: i2c@21a0000 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; 713 reg = <0x021a0000 0x4000>; 714 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&clks IMX6SLL_CLK_I2C1>; 716 status = "disabled"; 717 }; 718 719 i2c2: i2c@21a4000 { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 723 reg = <0x021a4000 0x4000>; 724 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clks IMX6SLL_CLK_I2C2>; 726 status = "disabled"; 727 }; 728 729 i2c3: i2c@21a8000 { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 733 reg = <0x021a8000 0x4000>; 734 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&clks IMX6SLL_CLK_I2C3>; 736 status = "disabled"; 737 }; 738 739 mmdc: memory-controller@21b0000 { 740 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; 741 reg = <0x021b0000 0x4000>; 742 }; 743 744 ocotp: ocotp-ctrl@21bc000 { 745 #address-cells = <1>; 746 #size-cells = <1>; 747 compatible = "fsl,imx6sll-ocotp", "syscon"; 748 reg = <0x021bc000 0x4000>; 749 clocks = <&clks IMX6SLL_CLK_OCOTP>; 750 751 tempmon_calib: calib@38 { 752 reg = <0x38 4>; 753 }; 754 755 tempmon_temp_grade: temp-grade@20 { 756 reg = <0x20 4>; 757 }; 758 }; 759 760 audmux: audmux@21d8000 { 761 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; 762 reg = <0x021d8000 0x4000>; 763 status = "disabled"; 764 }; 765 766 uart5: serial@21f4000 { 767 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", 768 "fsl,imx21-uart"; 769 reg = <0x021f4000 0x4000>; 770 interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 771 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 772 dma-names = "rx", "tx"; 773 clocks = <&clks IMX6SLL_CLK_UART5_IPG>, 774 <&clks IMX6SLL_CLK_UART5_SERIAL>; 775 clock-names = "ipg", "per"; 776 status = "disabled"; 777 }; 778 }; 779 }; 780}; 781
