1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11	chosen {
12		stdout-path = &uart1;
13	};
14
15	memory@10000000 {
16		reg = <0x10000000 0x40000000>;
17	};
18
19	regulators {
20		compatible = "simple-bus";
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		reg_usb_otg_vbus: regulator@0 {
25			compatible = "regulator-fixed";
26			reg = <0>;
27			regulator-name = "usb_otg_vbus";
28			regulator-min-microvolt = <5000000>;
29			regulator-max-microvolt = <5000000>;
30			gpio = <&gpio3 22 0>;
31			enable-active-high;
32			vin-supply = <&swbst_reg>;
33		};
34
35		reg_usb_h1_vbus: regulator@1 {
36			compatible = "regulator-fixed";
37			reg = <1>;
38			regulator-name = "usb_h1_vbus";
39			regulator-min-microvolt = <5000000>;
40			regulator-max-microvolt = <5000000>;
41			gpio = <&gpio1 29 0>;
42			enable-active-high;
43			vin-supply = <&swbst_reg>;
44		};
45
46		reg_audio: regulator@2 {
47			compatible = "regulator-fixed";
48			reg = <2>;
49			regulator-name = "wm8962-supply";
50			gpio = <&gpio4 10 0>;
51			enable-active-high;
52		};
53
54		reg_pcie: regulator@3 {
55			compatible = "regulator-fixed";
56			reg = <3>;
57			pinctrl-names = "default";
58			pinctrl-0 = <&pinctrl_pcie_reg>;
59			regulator-name = "MPCIE_3V3";
60			regulator-min-microvolt = <3300000>;
61			regulator-max-microvolt = <3300000>;
62			gpio = <&gpio3 19 0>;
63			enable-active-high;
64		};
65	};
66
67	gpio-keys {
68		compatible = "gpio-keys";
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_gpio_keys>;
71
72		power {
73			label = "Power Button";
74			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
75			wakeup-source;
76			linux,code = <KEY_POWER>;
77		};
78
79		volume-up {
80			label = "Volume Up";
81			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
82			wakeup-source;
83			linux,code = <KEY_VOLUMEUP>;
84		};
85
86		volume-down {
87			label = "Volume Down";
88			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
89			wakeup-source;
90			linux,code = <KEY_VOLUMEDOWN>;
91		};
92	};
93
94	sound {
95		compatible = "fsl,imx6q-sabresd-wm8962",
96			   "fsl,imx-audio-wm8962";
97		model = "wm8962-audio";
98		ssi-controller = <&ssi2>;
99		audio-codec = <&codec>;
100		audio-routing =
101			"Headphone Jack", "HPOUTL",
102			"Headphone Jack", "HPOUTR",
103			"Ext Spk", "SPKOUTL",
104			"Ext Spk", "SPKOUTR",
105			"AMIC", "MICBIAS",
106			"IN3R", "AMIC";
107		mux-int-port = <2>;
108		mux-ext-port = <3>;
109	};
110
111	backlight_lvds: backlight-lvds {
112		compatible = "pwm-backlight";
113		pwms = <&pwm1 0 5000000>;
114		brightness-levels = <0 4 8 16 32 64 128 255>;
115		default-brightness-level = <7>;
116		status = "okay";
117	};
118
119	leds {
120		compatible = "gpio-leds";
121		pinctrl-names = "default";
122		pinctrl-0 = <&pinctrl_gpio_leds>;
123
124		red {
125			gpios = <&gpio1 2 0>;
126			default-state = "on";
127		};
128	};
129
130	panel {
131		compatible = "hannstar,hsd100pxn1";
132		backlight = <&backlight_lvds>;
133
134		port {
135			panel_in: endpoint {
136				remote-endpoint = <&lvds0_out>;
137			};
138		};
139	};
140};
141
142&ipu1_csi0_from_ipu1_csi0_mux {
143	bus-width = <8>;
144	data-shift = <12>; /* Lines 19:12 used */
145	hsync-active = <1>;
146	vsync-active = <1>;
147};
148
149&ipu1_csi0_mux_from_parallel_sensor {
150	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
151};
152
153&ipu1_csi0 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_ipu1_csi0>;
156};
157
158&mipi_csi {
159	status = "okay";
160
161	port@0 {
162		reg = <0>;
163
164		mipi_csi2_in: endpoint {
165			remote-endpoint = <&ov5640_to_mipi_csi2>;
166			clock-lanes = <0>;
167			data-lanes = <1 2>;
168		};
169	};
170};
171
172&audmux {
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_audmux>;
175	status = "okay";
176};
177
178&clks {
179	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
180			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
181	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
182				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
183};
184
185&ecspi1 {
186	cs-gpios = <&gpio4 9 0>;
187	pinctrl-names = "default";
188	pinctrl-0 = <&pinctrl_ecspi1>;
189	status = "okay";
190
191	flash: m25p80@0 {
192		#address-cells = <1>;
193		#size-cells = <1>;
194		compatible = "st,m25p32", "jedec,spi-nor";
195		spi-max-frequency = <20000000>;
196		reg = <0>;
197	};
198};
199
200&fec {
201	pinctrl-names = "default";
202	pinctrl-0 = <&pinctrl_enet>;
203	phy-mode = "rgmii";
204	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
205	status = "okay";
206};
207
208&hdmi {
209	pinctrl-names = "default";
210	pinctrl-0 = <&pinctrl_hdmi_cec>;
211	ddc-i2c-bus = <&i2c2>;
212	status = "okay";
213};
214
215&i2c1 {
216	clock-frequency = <100000>;
217	pinctrl-names = "default";
218	pinctrl-0 = <&pinctrl_i2c1>;
219	status = "okay";
220
221	codec: wm8962@1a {
222		compatible = "wlf,wm8962";
223		reg = <0x1a>;
224		clocks = <&clks IMX6QDL_CLK_CKO>;
225		DCVDD-supply = <&reg_audio>;
226		DBVDD-supply = <&reg_audio>;
227		AVDD-supply = <&reg_audio>;
228		CPVDD-supply = <&reg_audio>;
229		MICVDD-supply = <&reg_audio>;
230		PLLVDD-supply = <&reg_audio>;
231		SPKVDD1-supply = <&reg_audio>;
232		SPKVDD2-supply = <&reg_audio>;
233		gpio-cfg = <
234			0x0000 /* 0:Default */
235			0x0000 /* 1:Default */
236			0x0013 /* 2:FN_DMICCLK */
237			0x0000 /* 3:Default */
238			0x8014 /* 4:FN_DMICCDAT */
239			0x0000 /* 5:Default */
240		>;
241	};
242
243	ov5642: camera@3c {
244		compatible = "ovti,ov5642";
245		pinctrl-names = "default";
246		pinctrl-0 = <&pinctrl_ov5642>;
247		clocks = <&clks IMX6QDL_CLK_CKO>;
248		clock-names = "xclk";
249		reg = <0x3c>;
250		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
251		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
252						rev B board is VGEN5 */
253		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
254		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
255		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
256		status = "disabled";
257
258		port {
259			ov5642_to_ipu1_csi0_mux: endpoint {
260				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
261				bus-width = <8>;
262				hsync-active = <1>;
263				vsync-active = <1>;
264			};
265		};
266	};
267};
268
269&i2c2 {
270	clock-frequency = <100000>;
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_i2c2>;
273	status = "okay";
274
275	ov5640: camera@3c {
276		compatible = "ovti,ov5640";
277		pinctrl-names = "default";
278		pinctrl-0 = <&pinctrl_ov5640>;
279		reg = <0x3c>;
280		clocks = <&clks IMX6QDL_CLK_CKO>;
281		clock-names = "xclk";
282		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
283		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
284						rev B board is VGEN5 */
285		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
286		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
287		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
288
289		port {
290			ov5640_to_mipi_csi2: endpoint {
291				remote-endpoint = <&mipi_csi2_in>;
292				clock-lanes = <0>;
293				data-lanes = <1 2>;
294			};
295		};
296	};
297
298	pmic: pfuze100@8 {
299		compatible = "fsl,pfuze100";
300		reg = <0x08>;
301
302		regulators {
303			sw1a_reg: sw1ab {
304				regulator-min-microvolt = <300000>;
305				regulator-max-microvolt = <1875000>;
306				regulator-boot-on;
307				regulator-always-on;
308				regulator-ramp-delay = <6250>;
309			};
310
311			sw1c_reg: sw1c {
312				regulator-min-microvolt = <300000>;
313				regulator-max-microvolt = <1875000>;
314				regulator-boot-on;
315				regulator-always-on;
316				regulator-ramp-delay = <6250>;
317			};
318
319			sw2_reg: sw2 {
320				regulator-min-microvolt = <800000>;
321				regulator-max-microvolt = <3300000>;
322				regulator-boot-on;
323				regulator-always-on;
324				regulator-ramp-delay = <6250>;
325			};
326
327			sw3a_reg: sw3a {
328				regulator-min-microvolt = <400000>;
329				regulator-max-microvolt = <1975000>;
330				regulator-boot-on;
331				regulator-always-on;
332			};
333
334			sw3b_reg: sw3b {
335				regulator-min-microvolt = <400000>;
336				regulator-max-microvolt = <1975000>;
337				regulator-boot-on;
338				regulator-always-on;
339			};
340
341			sw4_reg: sw4 {
342				regulator-min-microvolt = <800000>;
343				regulator-max-microvolt = <3300000>;
344				regulator-always-on;
345			};
346
347			swbst_reg: swbst {
348				regulator-min-microvolt = <5000000>;
349				regulator-max-microvolt = <5150000>;
350			};
351
352			snvs_reg: vsnvs {
353				regulator-min-microvolt = <1000000>;
354				regulator-max-microvolt = <3000000>;
355				regulator-boot-on;
356				regulator-always-on;
357			};
358
359			vref_reg: vrefddr {
360				regulator-boot-on;
361				regulator-always-on;
362			};
363
364			vgen1_reg: vgen1 {
365				regulator-min-microvolt = <800000>;
366				regulator-max-microvolt = <1550000>;
367			};
368
369			vgen2_reg: vgen2 {
370				regulator-min-microvolt = <800000>;
371				regulator-max-microvolt = <1550000>;
372			};
373
374			vgen3_reg: vgen3 {
375				regulator-min-microvolt = <1800000>;
376				regulator-max-microvolt = <3300000>;
377			};
378
379			vgen4_reg: vgen4 {
380				regulator-min-microvolt = <1800000>;
381				regulator-max-microvolt = <3300000>;
382				regulator-always-on;
383			};
384
385			vgen5_reg: vgen5 {
386				regulator-min-microvolt = <1800000>;
387				regulator-max-microvolt = <3300000>;
388				regulator-always-on;
389			};
390
391			vgen6_reg: vgen6 {
392				regulator-min-microvolt = <1800000>;
393				regulator-max-microvolt = <3300000>;
394				regulator-always-on;
395			};
396		};
397	};
398};
399
400&i2c3 {
401	clock-frequency = <100000>;
402	pinctrl-names = "default";
403	pinctrl-0 = <&pinctrl_i2c3>;
404	status = "okay";
405
406	egalax_ts@4 {
407		compatible = "eeti,egalax_ts";
408		reg = <0x04>;
409		interrupt-parent = <&gpio6>;
410		interrupts = <7 2>;
411		wakeup-gpios = <&gpio6 7 0>;
412	};
413};
414
415&iomuxc {
416	pinctrl-names = "default";
417	pinctrl-0 = <&pinctrl_hog>;
418
419	imx6qdl-sabresd {
420		pinctrl_hog: hoggrp {
421			fsl,pins = <
422				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
423				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
424				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
425				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
426				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
427				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
428				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
429				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
430				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
431			>;
432		};
433
434		pinctrl_audmux: audmuxgrp {
435			fsl,pins = <
436				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
437				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
438				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
439				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
440			>;
441		};
442
443		pinctrl_ecspi1: ecspi1grp {
444			fsl,pins = <
445				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
446				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
447				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
448				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
449			>;
450		};
451
452		pinctrl_enet: enetgrp {
453			fsl,pins = <
454				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
455				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
456				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
457				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
458				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
459				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
460				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
461				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
462				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
463				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
464				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
465				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
466				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
467				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
468				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
469				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
470			>;
471		};
472
473		pinctrl_gpio_keys: gpio_keysgrp {
474			fsl,pins = <
475				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
476				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
477				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
478			>;
479		};
480
481		pinctrl_hdmi_cec: hdmicecgrp {
482			fsl,pins = <
483				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
484			>;
485		};
486
487		pinctrl_i2c1: i2c1grp {
488			fsl,pins = <
489				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
490				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
491			>;
492		};
493
494		pinctrl_i2c2: i2c2grp {
495			fsl,pins = <
496				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
497				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
498			>;
499		};
500
501		pinctrl_i2c3: i2c3grp {
502			fsl,pins = <
503				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
504				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
505			>;
506		};
507
508		pinctrl_ipu1_csi0: ipu1csi0grp {
509			fsl,pins = <
510				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
511				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
512				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
513				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
514				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
515				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
516				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
517				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
518				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
519				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
520				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
521			>;
522		};
523
524		pinctrl_ov5640: ov5640grp {
525			fsl,pins = <
526				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
527				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
528			>;
529		};
530
531		pinctrl_ov5642: ov5642grp {
532			fsl,pins = <
533				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
534				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
535			>;
536		};
537
538		pinctrl_pcie: pciegrp {
539			fsl,pins = <
540				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
541			>;
542		};
543
544		pinctrl_pcie_reg: pciereggrp {
545			fsl,pins = <
546				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
547			>;
548		};
549
550		pinctrl_pwm1: pwm1grp {
551			fsl,pins = <
552				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
553			>;
554		};
555
556		pinctrl_uart1: uart1grp {
557			fsl,pins = <
558				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
559				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
560			>;
561		};
562
563		pinctrl_usbotg: usbotggrp {
564			fsl,pins = <
565				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
566			>;
567		};
568
569		pinctrl_usdhc2: usdhc2grp {
570			fsl,pins = <
571				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
572				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
573				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
574				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
575				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
576				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
577				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
578				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
579				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
580				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
581			>;
582		};
583
584		pinctrl_usdhc3: usdhc3grp {
585			fsl,pins = <
586				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
587				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
588				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
589				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
590				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
591				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
592				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
593				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
594				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
595				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
596			>;
597		};
598
599		pinctrl_usdhc4: usdhc4grp {
600			fsl,pins = <
601				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
602				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
603				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
604				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
605				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
606				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
607				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
608				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
609				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
610				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
611			>;
612		};
613
614		pinctrl_wdog: wdoggrp {
615			fsl,pins = <
616				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
617			>;
618		};
619	};
620
621	gpio_leds {
622		pinctrl_gpio_leds: gpioledsgrp {
623			fsl,pins = <
624				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
625			>;
626		};
627	};
628};
629
630&ldb {
631	status = "okay";
632
633	lvds-channel@1 {
634		fsl,data-mapping = "spwg";
635		fsl,data-width = <18>;
636		status = "okay";
637
638		port@4 {
639			reg = <4>;
640
641			lvds0_out: endpoint {
642				remote-endpoint = <&panel_in>;
643			};
644		};
645	};
646};
647
648&pcie {
649	pinctrl-names = "default";
650	pinctrl-0 = <&pinctrl_pcie>;
651	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
652	vpcie-supply = <&reg_pcie>;
653	status = "okay";
654};
655
656&pwm1 {
657	pinctrl-names = "default";
658	pinctrl-0 = <&pinctrl_pwm1>;
659	status = "okay";
660};
661
662&reg_arm {
663       vin-supply = <&sw1a_reg>;
664};
665
666&reg_pu {
667       vin-supply = <&sw1c_reg>;
668};
669
670&reg_soc {
671       vin-supply = <&sw1c_reg>;
672};
673
674&snvs_poweroff {
675	status = "okay";
676};
677
678&ssi2 {
679	status = "okay";
680};
681
682&uart1 {
683	pinctrl-names = "default";
684	pinctrl-0 = <&pinctrl_uart1>;
685	status = "okay";
686};
687
688&usbh1 {
689	vbus-supply = <&reg_usb_h1_vbus>;
690	status = "okay";
691};
692
693&usbotg {
694	vbus-supply = <&reg_usb_otg_vbus>;
695	pinctrl-names = "default";
696	pinctrl-0 = <&pinctrl_usbotg>;
697	disable-over-current;
698	status = "okay";
699};
700
701&usdhc2 {
702	pinctrl-names = "default";
703	pinctrl-0 = <&pinctrl_usdhc2>;
704	bus-width = <8>;
705	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
706	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
707	status = "okay";
708};
709
710&usdhc3 {
711	pinctrl-names = "default";
712	pinctrl-0 = <&pinctrl_usdhc3>;
713	bus-width = <8>;
714	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
715	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
716	status = "okay";
717};
718
719&usdhc4 {
720	pinctrl-names = "default";
721	pinctrl-0 = <&pinctrl_usdhc4>;
722	bus-width = <8>;
723	non-removable;
724	no-1-8-v;
725	status = "okay";
726};
727
728&wdog1 {
729	status = "disabled";
730};
731
732&wdog2 {
733	pinctrl-names = "default";
734	pinctrl-0 = <&pinctrl_wdog>;
735	fsl,ext-reset-output;
736	status = "okay";
737};
738