1/*
2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	model = "Phytec phyFLEX-i.MX6 Quad";
16	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
17
18	memory@10000000 {
19		reg = <0x10000000 0x80000000>;
20	};
21
22	regulators {
23		compatible = "simple-bus";
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		reg_usb_otg_vbus: regulator@0 {
28			compatible = "regulator-fixed";
29			reg = <0>;
30			regulator-name = "usb_otg_vbus";
31			regulator-min-microvolt = <5000000>;
32			regulator-max-microvolt = <5000000>;
33			gpio = <&gpio4 15 0>;
34			enable-active-high;
35		};
36
37		reg_usb_h1_vbus: regulator@1 {
38			compatible = "regulator-fixed";
39			reg = <1>;
40			regulator-name = "usb_h1_vbus";
41			regulator-min-microvolt = <5000000>;
42			regulator-max-microvolt = <5000000>;
43			gpio = <&gpio1 0 0>;
44			enable-active-high;
45		};
46	};
47
48	gpio_leds: leds {
49		compatible = "gpio-leds";
50
51		green {
52			label = "phyflex:green";
53			gpios = <&gpio1 30 0>;
54		};
55
56		red {
57			label = "phyflex:red";
58			gpios = <&gpio2 31 0>;
59		};
60	};
61};
62
63&audmux {
64	pinctrl-names = "default";
65	pinctrl-0 = <&pinctrl_audmux>;
66	status = "disabled";
67};
68
69&can1 {
70	pinctrl-names = "default";
71	pinctrl-0 = <&pinctrl_flexcan1>;
72	status = "disabled";
73};
74
75&ecspi3 {
76	pinctrl-names = "default";
77	pinctrl-0 = <&pinctrl_ecspi3>;
78	status = "okay";
79	cs-gpios = <&gpio4 24 0>;
80
81	flash@0 {
82		compatible = "m25p80", "jedec,spi-nor";
83		spi-max-frequency = <20000000>;
84		reg = <0>;
85	};
86};
87
88&fec {
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_enet>;
91	phy-mode = "rgmii";
92	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
93	phy-supply = <&vdd_eth_io_reg>;
94	status = "disabled";
95};
96
97&gpmi {
98	pinctrl-names = "default";
99	pinctrl-0 = <&pinctrl_gpmi_nand>;
100	nand-on-flash-bbt;
101	status = "okay";
102};
103
104&i2c1 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_i2c1>;
107	status = "okay";
108
109	eeprom@50 {
110		compatible = "atmel,24c32";
111		reg = <0x50>;
112	};
113
114	pmic@58 {
115		compatible = "dlg,da9063";
116		reg = <0x58>;
117		interrupt-parent = <&gpio2>;
118		interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
119
120		regulators {
121			vddcore_reg: bcore1 {
122				regulator-min-microvolt = <730000>;
123				regulator-max-microvolt = <1380000>;
124				regulator-always-on;
125			};
126
127			vddsoc_reg: bcore2 {
128				regulator-min-microvolt = <730000>;
129				regulator-max-microvolt = <1380000>;
130				regulator-always-on;
131			};
132
133			vdd_ddr3_reg: bpro {
134				regulator-min-microvolt = <1500000>;
135				regulator-max-microvolt = <1500000>;
136				regulator-always-on;
137			};
138
139			vdd_3v3_reg: bperi {
140				regulator-min-microvolt = <3300000>;
141				regulator-max-microvolt = <3300000>;
142				regulator-always-on;
143			};
144
145			vdd_buckmem_reg: bmem {
146				regulator-min-microvolt = <3300000>;
147				regulator-max-microvolt = <3300000>;
148				regulator-always-on;
149			};
150
151			vdd_eth_reg: bio {
152				regulator-min-microvolt = <1200000>;
153				regulator-max-microvolt = <1200000>;
154				regulator-always-on;
155			};
156
157			vdd_eth_io_reg: ldo4 {
158				regulator-min-microvolt = <2500000>;
159				regulator-max-microvolt = <2500000>;
160				regulator-always-on;
161			};
162
163			vdd_mx6_snvs_reg: ldo5 {
164				regulator-min-microvolt = <3000000>;
165				regulator-max-microvolt = <3000000>;
166				regulator-always-on;
167			};
168
169			vdd_3v3_pmic_io_reg: ldo6 {
170				regulator-min-microvolt = <3300000>;
171				regulator-max-microvolt = <3300000>;
172				regulator-always-on;
173			};
174
175			vdd_sd0_reg: ldo9 {
176				regulator-min-microvolt = <3300000>;
177				regulator-max-microvolt = <3300000>;
178			};
179
180			vdd_sd1_reg: ldo10 {
181				regulator-min-microvolt = <3300000>;
182				regulator-max-microvolt = <3300000>;
183			};
184
185			vdd_mx6_high_reg: ldo11 {
186				regulator-min-microvolt = <3000000>;
187				regulator-max-microvolt = <3000000>;
188				regulator-always-on;
189			};
190		};
191	};
192};
193
194&i2c2 {
195	pinctrl-names = "default";
196	pinctrl-0 = <&pinctrl_i2c2>;
197	clock-frequency = <100000>;
198};
199
200&i2c3 {
201	pinctrl-names = "default";
202	pinctrl-0 = <&pinctrl_i2c3>;
203	clock-frequency = <100000>;
204};
205
206&iomuxc {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_hog>;
209
210	imx6q-phytec-pfla02 {
211		pinctrl_hog: hoggrp {
212			fsl,pins = <
213				MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
214				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
215				MX6QDL_PAD_SD4_DAT1__GPIO2_IO09  0x80000000 /* PMIC interrupt */
216				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
217				MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
218			>;
219		};
220
221		pinctrl_ecspi3: ecspi3grp {
222			fsl,pins = <
223				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
224				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
225				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
226			>;
227		};
228
229		pinctrl_enet: enetgrp {
230			fsl,pins = <
231				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
232				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
233				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
234				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
235				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
236				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
237				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
238				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
239				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
240				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
241				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
242				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
243				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
244				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
245				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
246				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
247			>;
248		};
249
250		pinctrl_flexcan1: flexcan1grp {
251			fsl,pins = <
252				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
253				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
254			>;
255		};
256
257		pinctrl_gpmi_nand: gpminandgrp {
258			fsl,pins = <
259				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
260				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
261				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
262				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
263				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
264				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
265				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
266				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
267				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
268				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
269				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
270				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
271				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
272				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
273				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
274				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
275				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
276			>;
277		};
278
279		pinctrl_i2c1: i2c1grp {
280			fsl,pins = <
281				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
282				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
283			>;
284		};
285
286		pinctrl_i2c2: i2c2grp {
287			fsl,pins = <
288				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
289				MX6QDL_PAD_EIM_D16__I2C2_SDA		0x4001b8b1
290			>;
291		};
292
293		pinctrl_i2c3: i2c3grp {
294			fsl,pins = <
295				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
296				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
297			>;
298		};
299
300		pinctrl_pcie: pciegrp {
301			fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
302		};
303
304		pinctrl_uart3: uart3grp {
305			fsl,pins = <
306				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
307				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
308				MX6QDL_PAD_EIM_D30__UART3_RTS_B		0x1b0b1
309				MX6QDL_PAD_EIM_D31__UART3_CTS_B		0x1b0b1
310			>;
311		};
312
313		pinctrl_uart4: uart4grp {
314			fsl,pins = <
315				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
316				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
317			>;
318		};
319
320		pinctrl_usbh1: usbh1grp {
321			fsl,pins = <
322				MX6QDL_PAD_GPIO_0__USB_H1_PWR		0x80000000
323			>;
324		};
325
326		pinctrl_usbotg: usbotggrp {
327			fsl,pins = <
328				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
329				MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
330				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x80000000
331			>;
332		};
333
334		pinctrl_usdhc2: usdhc2grp {
335			fsl,pins = <
336				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
337				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
338				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
339				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
340				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
341				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
342			>;
343		};
344
345		pinctrl_usdhc3: usdhc3grp {
346			fsl,pins = <
347				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
348				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
349				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
350				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
351				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
352				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
353			>;
354		};
355
356		pinctrl_usdhc3_cdwp: usdhc3cdwp {
357			fsl,pins = <
358				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
359				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
360			>;
361		};
362
363		pinctrl_audmux: audmuxgrp {
364			fsl,pins = <
365				MX6QDL_PAD_DISP0_DAT16__AUD5_TXC	0x130b0
366				MX6QDL_PAD_DISP0_DAT17__AUD5_TXD	0x110b0
367				MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS	0x130b0
368				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD	0x130b0
369			>;
370		};
371	};
372};
373
374&pcie {
375	pinctrl-names = "default";
376	pinctrl-0 = <&pinctrl_pcie>;
377	reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
378	status = "disabled";
379};
380
381&reg_arm {
382	vin-supply = <&vddcore_reg>;
383};
384
385&reg_pu {
386	vin-supply = <&vddsoc_reg>;
387};
388
389&reg_soc {
390	vin-supply = <&vddsoc_reg>;
391};
392
393&uart3 {
394	pinctrl-names = "default";
395	pinctrl-0 = <&pinctrl_uart3>;
396	status = "disabled";
397};
398
399&uart4 {
400	pinctrl-names = "default";
401	pinctrl-0 = <&pinctrl_uart4>;
402	status = "disabled";
403};
404
405&usbh1 {
406	vbus-supply = <&reg_usb_h1_vbus>;
407	pinctrl-names = "default";
408	pinctrl-0 = <&pinctrl_usbh1>;
409	status = "disabled";
410};
411
412&usbotg {
413	vbus-supply = <&reg_usb_otg_vbus>;
414	pinctrl-names = "default";
415	pinctrl-0 = <&pinctrl_usbotg>;
416	disable-over-current;
417	status = "disabled";
418};
419
420&usdhc2 {
421	pinctrl-names = "default";
422	pinctrl-0 = <&pinctrl_usdhc2>;
423	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
424	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
425	status = "disabled";
426};
427
428&usdhc3 {
429	pinctrl-names = "default";
430	pinctrl-0 = <&pinctrl_usdhc3
431		     &pinctrl_usdhc3_cdwp>;
432	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
433	wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
434	status = "disabled";
435};
436