1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2015 Boundary Devices, Inc. 4 */ 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/input/input.h> 7 8/ { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 memory@10000000 { 14 reg = <0x10000000 0xF0000000>; 15 }; 16 17 regulators { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 reg_1p8v: regulator@0 { 23 compatible = "regulator-fixed"; 24 reg = <0>; 25 regulator-name = "1P8V"; 26 regulator-min-microvolt = <1800000>; 27 regulator-max-microvolt = <1800000>; 28 regulator-always-on; 29 }; 30 31 reg_2p5v: regulator@1 { 32 compatible = "regulator-fixed"; 33 reg = <1>; 34 regulator-name = "2P5V"; 35 regulator-min-microvolt = <2500000>; 36 regulator-max-microvolt = <2500000>; 37 regulator-always-on; 38 }; 39 40 reg_3p3v: regulator@2 { 41 compatible = "regulator-fixed"; 42 reg = <2>; 43 regulator-name = "3P3V"; 44 regulator-min-microvolt = <3300000>; 45 regulator-max-microvolt = <3300000>; 46 regulator-always-on; 47 }; 48 49 reg_usb_otg_vbus: regulator@3 { 50 compatible = "regulator-fixed"; 51 reg = <3>; 52 regulator-name = "usb_otg_vbus"; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 56 enable-active-high; 57 }; 58 59 reg_usb_h1_vbus: regulator@4 { 60 compatible = "regulator-fixed"; 61 reg = <4>; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_usbh1>; 64 regulator-name = "usb_h1_vbus"; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 68 enable-active-high; 69 }; 70 71 reg_wlan_vmmc: regulator@5 { 72 compatible = "regulator-fixed"; 73 reg = <5>; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_wlan_vmmc>; 76 regulator-name = "reg_wlan_vmmc"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 80 startup-delay-us = <70000>; 81 enable-active-high; 82 }; 83 84 reg_can_xcvr: regulator@6 { 85 compatible = "regulator-fixed"; 86 reg = <6>; 87 regulator-name = "CAN XCVR"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_can_xcvr>; 92 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 93 }; 94 }; 95 96 gpio-keys { 97 compatible = "gpio-keys"; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_gpio_keys>; 100 101 power { 102 label = "Power Button"; 103 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 104 linux,code = <KEY_POWER>; 105 wakeup-source; 106 }; 107 108 menu { 109 label = "Menu"; 110 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 111 linux,code = <KEY_MENU>; 112 }; 113 114 home { 115 label = "Home"; 116 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 117 linux,code = <KEY_HOME>; 118 }; 119 120 back { 121 label = "Back"; 122 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 123 linux,code = <KEY_BACK>; 124 }; 125 126 volume-up { 127 label = "Volume Up"; 128 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 129 linux,code = <KEY_VOLUMEUP>; 130 }; 131 132 volume-down { 133 label = "Volume Down"; 134 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 135 linux,code = <KEY_VOLUMEDOWN>; 136 }; 137 }; 138 139 i2c2mux { 140 compatible = "i2c-mux-gpio"; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_i2c2mux>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH 146 &gpio4 15 GPIO_ACTIVE_HIGH>; 147 i2c-parent = <&i2c2>; 148 idle-state = <0>; 149 150 i2c2mux@1 { 151 reg = <1>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 }; 155 156 i2c2mux@2 { 157 reg = <2>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 }; 161 }; 162 163 i2c3mux { 164 compatible = "i2c-mux-gpio"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c3mux>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; 170 i2c-parent = <&i2c3>; 171 idle-state = <0>; 172 173 i2c3mux@1 { 174 reg = <1>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 }; 178 }; 179 180 leds { 181 compatible = "gpio-leds"; 182 183 speaker-enable { 184 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 185 retain-state-suspended; 186 default-state = "off"; 187 }; 188 189 ttymxc4-rs232 { 190 gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; 191 retain-state-suspended; 192 default-state = "on"; 193 }; 194 }; 195 196 backlight_lcd: backlight-lcd { 197 compatible = "pwm-backlight"; 198 pwms = <&pwm1 0 5000000>; 199 brightness-levels = <0 4 8 16 32 64 128 255>; 200 default-brightness-level = <7>; 201 power-supply = <®_3p3v>; 202 status = "okay"; 203 }; 204 205 backlight_lvds0: backlight-lvds0 { 206 compatible = "pwm-backlight"; 207 pwms = <&pwm4 0 5000000>; 208 brightness-levels = <0 4 8 16 32 64 128 255>; 209 default-brightness-level = <7>; 210 power-supply = <®_3p3v>; 211 status = "okay"; 212 }; 213 214 backlight_lvds1: backlight-lvds1 { 215 compatible = "pwm-backlight"; 216 pwms = <&pwm2 0 5000000>; 217 brightness-levels = <0 4 8 16 32 64 128 255>; 218 default-brightness-level = <7>; 219 power-supply = <®_3p3v>; 220 status = "okay"; 221 }; 222 223 lcd_display: disp0 { 224 compatible = "fsl,imx-parallel-display"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interface-pix-fmt = "bgr666"; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_j15>; 230 status = "okay"; 231 232 port@0 { 233 reg = <0>; 234 235 lcd_display_in: endpoint { 236 remote-endpoint = <&ipu1_di0_disp0>; 237 }; 238 }; 239 240 port@1 { 241 reg = <1>; 242 243 lcd_display_out: endpoint { 244 remote-endpoint = <&lcd_panel_in>; 245 }; 246 }; 247 }; 248 249 panel-lcd { 250 compatible = "okaya,rs800480t-7x0gp"; 251 backlight = <&backlight_lcd>; 252 253 port { 254 lcd_panel_in: endpoint { 255 remote-endpoint = <&lcd_display_out>; 256 }; 257 }; 258 }; 259 260 panel-lvds0 { 261 compatible = "hannstar,hsd100pxn1"; 262 backlight = <&backlight_lvds0>; 263 264 port { 265 panel_in_lvds0: endpoint { 266 remote-endpoint = <&lvds0_out>; 267 }; 268 }; 269 }; 270 271 panel-lvds1 { 272 compatible = "hannstar,hsd100pxn1"; 273 backlight = <&backlight_lvds1>; 274 275 port { 276 panel_in_lvds1: endpoint { 277 remote-endpoint = <&lvds1_out>; 278 }; 279 }; 280 }; 281 282 sound { 283 compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", 284 "fsl,imx-audio-sgtl5000"; 285 model = "imx6q-nitrogen6_max-sgtl5000"; 286 ssi-controller = <&ssi1>; 287 audio-codec = <&codec>; 288 audio-routing = 289 "MIC_IN", "Mic Jack", 290 "Mic Jack", "Mic Bias", 291 "Headphone Jack", "HP_OUT"; 292 mux-int-port = <1>; 293 mux-ext-port = <3>; 294 }; 295}; 296 297&audmux { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_audmux>; 300 status = "okay"; 301}; 302 303&can1 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_can1>; 306 xceiver-supply = <®_can_xcvr>; 307 status = "okay"; 308}; 309 310&clks { 311 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 312 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 313 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 314 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 315}; 316 317&ecspi1 { 318 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_ecspi1>; 321 status = "okay"; 322 323 flash: m25p80@0 { 324 compatible = "microchip,sst25vf016b"; 325 spi-max-frequency = <20000000>; 326 reg = <0>; 327 }; 328}; 329 330&fec { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_enet>; 333 phy-mode = "rgmii"; 334 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 335 txen-skew-ps = <0>; 336 txc-skew-ps = <3000>; 337 rxdv-skew-ps = <0>; 338 rxc-skew-ps = <3000>; 339 rxd0-skew-ps = <0>; 340 rxd1-skew-ps = <0>; 341 rxd2-skew-ps = <0>; 342 rxd3-skew-ps = <0>; 343 txd0-skew-ps = <0>; 344 txd1-skew-ps = <0>; 345 txd2-skew-ps = <0>; 346 txd3-skew-ps = <0>; 347 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 348 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 349 fsl,err006687-workaround-present; 350 status = "okay"; 351}; 352 353&hdmi { 354 ddc-i2c-bus = <&i2c2>; 355 status = "okay"; 356}; 357 358&i2c1 { 359 clock-frequency = <100000>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_i2c1>; 362 status = "okay"; 363 364 codec: sgtl5000@a { 365 compatible = "fsl,sgtl5000"; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_sgtl5000>; 368 reg = <0x0a>; 369 clocks = <&clks IMX6QDL_CLK_CKO>; 370 VDDA-supply = <®_2p5v>; 371 VDDIO-supply = <®_3p3v>; 372 }; 373 374 rtc: rtc@68 { 375 compatible = "microcrystal,rv4162"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_rv4162>; 378 reg = <0x68>; 379 interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; 380 }; 381}; 382 383&i2c2 { 384 clock-frequency = <100000>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_i2c2>; 387 status = "okay"; 388}; 389 390&i2c3 { 391 clock-frequency = <100000>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_i2c3>; 394 status = "okay"; 395 396 touchscreen@4 { 397 compatible = "eeti,egalax_ts"; 398 reg = <0x04>; 399 interrupt-parent = <&gpio1>; 400 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 401 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 402 }; 403 404 touchscreen@38 { 405 compatible = "edt,edt-ft5x06"; 406 reg = <0x38>; 407 interrupt-parent = <&gpio1>; 408 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 409 wakeup-source; 410 }; 411}; 412 413&iomuxc { 414 imx6q-nitrogen6-max { 415 pinctrl_audmux: audmuxgrp { 416 fsl,pins = < 417 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 418 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 419 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 420 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 421 >; 422 }; 423 424 pinctrl_can1: can1grp { 425 fsl,pins = < 426 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 427 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 428 >; 429 }; 430 431 pinctrl_can_xcvr: can-xcvrgrp { 432 fsl,pins = < 433 /* Flexcan XCVR enable */ 434 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 435 >; 436 }; 437 438 pinctrl_ecspi1: ecspi1grp { 439 fsl,pins = < 440 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 441 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 442 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 443 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 444 >; 445 }; 446 447 pinctrl_enet: enetgrp { 448 fsl,pins = < 449 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 450 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 451 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 452 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 453 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 454 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 455 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 456 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 457 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 458 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 459 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 460 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 461 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 462 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 463 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 464 /* Phy reset */ 465 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 466 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 467 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 468 >; 469 }; 470 471 pinctrl_gpio_keys: gpio-keysgrp { 472 fsl,pins = < 473 /* Power Button */ 474 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 475 /* Menu Button */ 476 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 477 /* Home Button */ 478 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 479 /* Back Button */ 480 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 481 /* Volume Up Button */ 482 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 483 /* Volume Down Button */ 484 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 485 >; 486 }; 487 488 pinctrl_i2c1: i2c1grp { 489 fsl,pins = < 490 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 491 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 492 >; 493 }; 494 495 pinctrl_i2c2: i2c2grp { 496 fsl,pins = < 497 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 498 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 499 >; 500 }; 501 502 pinctrl_i2c2mux: i2c2muxgrp { 503 fsl,pins = < 504 /* ov5642 camera i2c enable */ 505 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 506 /* ov5640_mipi camera i2c enable */ 507 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 508 >; 509 }; 510 511 pinctrl_i2c3: i2c3grp { 512 fsl,pins = < 513 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 514 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 515 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 516 >; 517 }; 518 519 pinctrl_i2c3mux: i2c3muxgrp { 520 fsl,pins = < 521 /* PCIe I2C enable */ 522 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 523 >; 524 }; 525 526 pinctrl_j15: j15grp { 527 fsl,pins = < 528 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 529 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 530 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 531 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 532 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 533 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 534 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 535 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 536 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 537 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 538 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 539 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 540 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 541 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 542 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 543 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 544 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 545 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 546 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 547 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 548 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 549 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 550 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 551 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 552 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 553 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 554 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 555 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 556 >; 557 }; 558 559 pinctrl_pcie: pciegrp { 560 fsl,pins = < 561 /* PCIe reset */ 562 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 563 >; 564 }; 565 566 pinctrl_pwm1: pwm1grp { 567 fsl,pins = < 568 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 569 >; 570 }; 571 572 pinctrl_pwm2: pwm2grp { 573 fsl,pins = < 574 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 575 >; 576 }; 577 578 pinctrl_pwm3: pwm3grp { 579 fsl,pins = < 580 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 581 >; 582 }; 583 584 pinctrl_pwm4: pwm4grp { 585 fsl,pins = < 586 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 587 >; 588 }; 589 590 pinctrl_rv4162: rv4162grp { 591 fsl,pins = < 592 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 593 >; 594 }; 595 596 pinctrl_sgtl5000: sgtl5000grp { 597 fsl,pins = < 598 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 599 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 600 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 601 >; 602 }; 603 604 pinctrl_uart1: uart1grp { 605 fsl,pins = < 606 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 607 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 608 >; 609 }; 610 611 pinctrl_uart2: uart2grp { 612 fsl,pins = < 613 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 614 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 615 >; 616 }; 617 618 pinctrl_uart5: uart5grp { 619 fsl,pins = < 620 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 621 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 622 /* RS485 RX Enable: pull up */ 623 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 624 /* RS485 DEN: pull down */ 625 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 626 /* RS485/!RS232 Select: pull down (rs232) */ 627 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 628 /* ON: pull down */ 629 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 630 >; 631 }; 632 633 pinctrl_usbh1: usbh1grp { 634 fsl,pins = < 635 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 636 >; 637 }; 638 639 pinctrl_usbotg: usbotggrp { 640 fsl,pins = < 641 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 642 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 643 /* power enable, high active */ 644 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 645 >; 646 }; 647 648 pinctrl_usdhc2: usdhc2grp { 649 fsl,pins = < 650 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 651 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 652 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 653 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 654 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 655 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 656 >; 657 }; 658 659 pinctrl_usdhc3: usdhc3grp { 660 fsl,pins = < 661 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 662 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 663 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 664 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 665 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 666 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 667 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 668 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 669 >; 670 }; 671 672 pinctrl_usdhc4: usdhc4grp { 673 fsl,pins = < 674 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 675 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 676 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 677 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 678 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 679 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 680 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 681 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 682 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 683 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 684 >; 685 }; 686 687 pinctrl_wlan_vmmc: wlan-vmmcgrp { 688 fsl,pins = < 689 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 690 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 691 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 692 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 693 >; 694 }; 695 }; 696}; 697 698&ipu1_di0_disp0 { 699 remote-endpoint = <&lcd_display_in>; 700}; 701 702&ldb { 703 status = "okay"; 704 705 lvds-channel@0 { 706 status = "okay"; 707 708 port@4 { 709 reg = <4>; 710 711 lvds0_out: endpoint { 712 remote-endpoint = <&panel_in_lvds0>; 713 }; 714 }; 715 }; 716 717 lvds-channel@1 { 718 status = "okay"; 719 720 port@4 { 721 reg = <4>; 722 723 lvds1_out: endpoint { 724 remote-endpoint = <&panel_in_lvds1>; 725 }; 726 }; 727 }; 728}; 729 730&pcie { 731 pinctrl-names = "default"; 732 pinctrl-0 = <&pinctrl_pcie>; 733 reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; 734 status = "okay"; 735}; 736 737&pwm1 { 738 pinctrl-names = "default"; 739 pinctrl-0 = <&pinctrl_pwm1>; 740 status = "okay"; 741}; 742 743&pwm2 { 744 pinctrl-names = "default"; 745 pinctrl-0 = <&pinctrl_pwm2>; 746 status = "okay"; 747}; 748 749&pwm3 { 750 pinctrl-names = "default"; 751 pinctrl-0 = <&pinctrl_pwm3>; 752 status = "okay"; 753}; 754 755&pwm4 { 756 pinctrl-names = "default"; 757 pinctrl-0 = <&pinctrl_pwm4>; 758 status = "okay"; 759}; 760 761&ssi1 { 762 status = "okay"; 763}; 764 765&uart1 { 766 pinctrl-names = "default"; 767 pinctrl-0 = <&pinctrl_uart1>; 768 status = "okay"; 769}; 770 771&uart2 { 772 pinctrl-names = "default"; 773 pinctrl-0 = <&pinctrl_uart2>; 774 status = "okay"; 775}; 776 777&uart5 { 778 pinctrl-names = "default"; 779 pinctrl-0 = <&pinctrl_uart5>; 780 status = "okay"; 781}; 782 783&usbh1 { 784 vbus-supply = <®_usb_h1_vbus>; 785 status = "okay"; 786}; 787 788&usbotg { 789 vbus-supply = <®_usb_otg_vbus>; 790 pinctrl-names = "default"; 791 pinctrl-0 = <&pinctrl_usbotg>; 792 disable-over-current; 793 status = "okay"; 794}; 795 796&usdhc2 { 797 pinctrl-names = "default"; 798 pinctrl-0 = <&pinctrl_usdhc2>; 799 bus-width = <4>; 800 non-removable; 801 vmmc-supply = <®_wlan_vmmc>; 802 cap-power-off-card; 803 keep-power-in-suspend; 804 status = "okay"; 805 806 #address-cells = <1>; 807 #size-cells = <0>; 808 wlcore: wlcore@2 { 809 compatible = "ti,wl1271"; 810 reg = <2>; 811 interrupt-parent = <&gpio6>; 812 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 813 ref-clock-frequency = <38400000>; 814 }; 815}; 816 817&usdhc3 { 818 pinctrl-names = "default"; 819 pinctrl-0 = <&pinctrl_usdhc3>; 820 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 821 bus-width = <4>; 822 vmmc-supply = <®_3p3v>; 823 status = "okay"; 824}; 825 826&usdhc4 { 827 pinctrl-names = "default"; 828 pinctrl-0 = <&pinctrl_usdhc4>; 829 bus-width = <8>; 830 non-removable; 831 vmmc-supply = <®_1p8v>; 832 keep-power-in-suspend; 833 status = "okay"; 834}; 835
