1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49 50/ { 51 chosen { 52 stdout-path = &uart2; 53 }; 54 55 backlight { 56 compatible = "pwm-backlight"; 57 pwms = <&pwm1 0 5000000>; 58 brightness-levels = < 59 0 1 2 3 4 5 6 7 8 9 60 10 11 12 13 14 15 16 17 18 19 61 20 21 22 23 24 25 26 27 28 29 62 30 31 32 33 34 35 36 37 38 39 63 40 41 42 43 44 45 46 47 48 49 64 50 51 52 53 54 55 56 57 58 59 65 60 61 62 63 64 65 66 67 68 69 66 70 71 72 73 74 75 76 77 78 79 67 80 81 82 83 84 85 86 87 88 89 68 90 91 92 93 94 95 96 97 98 99 69 100 70 >; 71 default-brightness-level = <100>; 72 }; 73 74 leds { 75 compatible = "gpio-leds"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_gpio_leds>; 78 79 led0: user1 { 80 label = "user1"; 81 gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 82 default-state = "off"; 83 }; 84 }; 85 86 memory@10000000 { 87 reg = <0x10000000 0x40000000>; 88 }; 89 90 reg_5p0v: regulator-5p0v { 91 compatible = "regulator-fixed"; 92 regulator-name = "5P0V"; 93 regulator-min-microvolt = <5000000>; 94 regulator-max-microvolt = <5000000>; 95 regulator-always-on; 96 }; 97 98 reg_3p3v: regulator-3p3v { 99 compatible = "regulator-fixed"; 100 regulator-name = "3P3V"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-always-on; 104 }; 105 106 reg_2p5v: regulator-2p5v { 107 compatible = "regulator-fixed"; 108 regulator-name = "2P5V"; 109 regulator-min-microvolt = <2500000>; 110 regulator-max-microvolt = <2500000>; 111 regulator-always-on; 112 }; 113 114 reg_usb_h1_vbus: regulator-usb-h1-vbus { 115 compatible = "regulator-fixed"; 116 regulator-name = "usb_h1_vbus"; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 gpio = <&gpio3 30 0>; 120 enable-active-high; 121 }; 122 123 reg_usb_otg_vbus: regulator-usb-otg-vbus { 124 compatible = "regulator-fixed"; 125 regulator-name = "usb_otg_vbus"; 126 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>; 128 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 129 enable-active-high; 130 }; 131 132 reg_12p0: regulator-12p0v { 133 compatible = "regulator-fixed"; 134 regulator-name = "12P0V"; 135 regulator-min-microvolt = <12000000>; 136 regulator-max-microvolt = <12000000>; 137 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 }; 140 141 sound { 142 compatible = "fsl,imx-audio-tlv320"; 143 model = "imx-tlv320"; 144 ssi-controller = <&ssi1>; 145 audio-codec = <&tlv320aic3105>; 146 /* routing of sink, source */ 147 audio-routing = 148 /* TLV320 LINE1L pin <-> Mic Jack connector */ 149 "LINE1L", "Mic Jack", 150 /* board Headphone Jack <-> HPOUT */ 151 "Headphone Jack", "HPLOUT", 152 "Headphone Jack", "HPROUT", 153 "Mic Jack", "Mic Bias"; 154 mux-int-port = <1>; 155 mux-ext-port = <6>; 156 }; 157}; 158 159&audmux { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_audmux>; 162 status = "okay"; 163}; 164 165&clks { 166 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 167 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 168 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 169 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 170}; 171 172&fec { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_enet>; 175 phy-mode = "rgmii-id"; 176 status = "okay"; 177}; 178 179&i2c1 { 180 clock-frequency = <100000>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_i2c1>; 183 status = "okay"; 184 185 pca9555: gpio@23 { 186 compatible = "nxp,pca9555"; 187 reg = <0x23>; 188 gpio-controller; 189 #gpio-cells = <2>; 190 }; 191 192 eeprom1: eeprom@50 { 193 compatible = "atmel,24c02"; 194 reg = <0x50>; 195 pagesize = <16>; 196 }; 197 198 eeprom2: eeprom@51 { 199 compatible = "atmel,24c02"; 200 reg = <0x51>; 201 pagesize = <16>; 202 }; 203 204 eeprom3: eeprom@52 { 205 compatible = "atmel,24c02"; 206 reg = <0x52>; 207 pagesize = <16>; 208 }; 209 210 eeprom4: eeprom@53 { 211 compatible = "atmel,24c02"; 212 reg = <0x53>; 213 pagesize = <16>; 214 }; 215 216 dts1672: rtc@68 { 217 compatible = "dallas,ds1672"; 218 reg = <0x68>; 219 }; 220}; 221 222&i2c2 { 223 clock-frequency = <400000>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_i2c2>; 226 status = "okay"; 227 228 ltc3676: pmic@3c { 229 compatible = "lltc,ltc3676"; 230 reg = <0x3c>; 231 interrupt-parent = <&gpio1>; 232 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 233 234 regulators { 235 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ 236 reg_1p8v: sw1 { 237 regulator-name = "vdd1p8"; 238 regulator-min-microvolt = <1033310>; 239 regulator-max-microvolt = <2004000>; 240 lltc,fb-voltage-divider = <301000 200000>; 241 regulator-ramp-delay = <7000>; 242 regulator-boot-on; 243 regulator-always-on; 244 }; 245 246 /* VDD_DDR (1+R1/R2 = 2.105) */ 247 reg_vdd_ddr: sw2 { 248 regulator-name = "vddddr"; 249 regulator-min-microvolt = <868310>; 250 regulator-max-microvolt = <1684000>; 251 lltc,fb-voltage-divider = <221000 200000>; 252 regulator-ramp-delay = <7000>; 253 regulator-boot-on; 254 regulator-always-on; 255 }; 256 257 /* VDD_ARM (1+R1/R2 = 1.635) */ 258 reg_vdd_arm: sw3 { 259 regulator-name = "vddarm"; 260 regulator-min-microvolt = <674400>; 261 regulator-max-microvolt = <1308000>; 262 lltc,fb-voltage-divider = <127000 200000>; 263 regulator-ramp-delay = <7000>; 264 regulator-boot-on; 265 regulator-always-on; 266 linux,phandle = <®_vdd_arm>; 267 }; 268 269 /* VDD_SOC (1+R1/R2 = 1.635) */ 270 reg_vdd_soc: sw4 { 271 regulator-name = "vddsoc"; 272 regulator-min-microvolt = <674400>; 273 regulator-max-microvolt = <1308000>; 274 lltc,fb-voltage-divider = <127000 200000>; 275 regulator-ramp-delay = <7000>; 276 regulator-boot-on; 277 regulator-always-on; 278 linux,phandle = <®_vdd_soc>; 279 }; 280 281 /* VDD_1P0 (1+R1/R2 = 1.38): */ 282 reg_1p0v: ldo2 { 283 regulator-name = "vdd1p0"; 284 regulator-min-microvolt = <1002777>; 285 regulator-max-microvolt = <1002777>; 286 lltc,fb-voltage-divider = <100000 261000>; 287 regulator-boot-on; 288 regulator-always-on; 289 }; 290 291 /* VDD_HIGH (1+R1/R2 = 4.17) */ 292 reg_3p0v: ldo4 { 293 regulator-name = "vdd3p0"; 294 regulator-min-microvolt = <3023250>; 295 regulator-max-microvolt = <3023250>; 296 lltc,fb-voltage-divider = <634000 200000>; 297 regulator-boot-on; 298 regulator-always-on; 299 }; 300 }; 301 }; 302}; 303 304&i2c3 { 305 clock-frequency = <400000>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_i2c3>; 308 status = "okay"; 309 310 tlv320aic3105: codec@18 { 311 compatible = "ti,tlv320aic3x"; 312 reg = <0x18>; 313 gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>; 314 clocks = <&clks IMX6QDL_CLK_CKO>; 315 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ 316 /* Regulators */ 317 DRVDD-supply = <®_3p3v>; 318 AVDD-supply = <®_3p3v>; 319 IOVDD-supply = <®_3p3v>; 320 DVDD-supply = <®_1p8v>; 321 }; 322 323 accelerometer@1d { 324 compatible = "fsl,mma8451"; 325 reg = <0x1d>; 326 interrupt-parent = <&gpio7>; 327 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 328 interrupt-names = "INT2"; 329 }; 330 331 /* headphone detect */ 332 ts3a227e@3b { 333 compatible = "ti,ts3a227e"; 334 reg = <0x3b>; 335 interrupt-parent = <&gpio5>; 336 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 337 ti,micbias = <4>; /* 2.5V micbias */ 338 }; 339}; 340 341&ldb { 342 status = "okay"; 343 344 lvds-channel@0 { 345 fsl,data-mapping = "spwg"; 346 fsl,data-width = <18>; 347 status = "okay"; 348 349 display-timings { 350 native-mode = <&timing0>; 351 timing0: g101evn010 { 352 clock-frequency = <68930000>; 353 hactive = <1280>; 354 vactive = <800>; 355 hback-porch = <220>; 356 hfront-porch = <40>; 357 vback-porch = <21>; 358 vfront-porch = <7>; 359 hsync-len = <60>; 360 vsync-len = <10>; 361 }; 362 }; 363 }; 364}; 365 366&pwm1 { 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_pwm1>; 369 status = "okay"; 370}; 371 372&ssi1 { 373 status = "okay"; 374}; 375 376&uart1 { 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_uart1>; 379 status = "okay"; 380}; 381 382&uart2 { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_uart2>; 385 status = "okay"; 386}; 387 388&usbotg { 389 vbus-supply = <®_usb_otg_vbus>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_usbotg>; 392 disable-over-current; 393 status = "okay"; 394}; 395 396&usbh1 { 397 vbus-supply = <®_usb_h1_vbus>; 398 status = "okay"; 399}; 400 401&usdhc1 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_usdhc1_200mhz>; 404 vmmc-supply = <®_3p3v>; 405 non-removable; 406 bus-width = <4>; 407 status = "okay"; 408}; 409 410&usdhc2 { 411 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 412 pinctrl-0 = <&pinctrl_usdhc2>; 413 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 414 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 415 cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 416 vmmc-supply = <®_3p3v>; 417 max-frequency = <100000000>; 418 status = "okay"; 419}; 420 421&usdhc3 { 422 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 423 pinctrl-0 = <&pinctrl_usdhc3>; 424 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 425 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 426 non-removable; 427 vmmc-supply = <®_3p3v>; 428 keep-power-in-suspend; 429 status = "okay"; 430}; 431 432&wdog1 { 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_wdog>; 435 fsl,ext-reset-output; 436}; 437 438&iomuxc { 439 pinctrl_audmux: audmuxgrp { 440 fsl,pins = < 441 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 442 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 443 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 444 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 445 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ 446 >; 447 }; 448 449 pinctrl_enet: enetgrp { 450 fsl,pins = < 451 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 452 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 453 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 454 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 455 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 456 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 457 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 458 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 459 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 460 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 461 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 462 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 463 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 464 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 465 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 466 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 467 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ 468 >; 469 }; 470 471 pinctrl_gpio_leds: gpioledsgrp { 472 fsl,pins = < 473 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 474 >; 475 }; 476 477 pinctrl_i2c1: i2c1grp { 478 fsl,pins = < 479 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 480 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 481 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 482 >; 483 }; 484 485 pinctrl_i2c2: i2c2grp { 486 fsl,pins = < 487 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 488 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 489 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 490 >; 491 }; 492 493 pinctrl_i2c3: i2c3grp { 494 fsl,pins = < 495 /* I2C3 */ 496 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 497 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 498 499 /* Headphone Detect */ 500 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ 501 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ 502 503 /* Codec */ 504 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ 505 506 /* Touch Controller */ 507 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ 508 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ 509 510 /* Stow Sensor */ 511 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ 512 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ 513 >; 514 }; 515 516 pinctrl_pwm1: pwm1grp { 517 fsl,pins = < 518 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 519 >; 520 }; 521 522 pinctrl_uart1: uart1grp { 523 fsl,pins = < 524 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 525 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 526 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ 527 >; 528 }; 529 530 pinctrl_uart2: uart2grp { 531 fsl,pins = < 532 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 533 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 534 >; 535 }; 536 537 pinctrl_usbotg: usbotggrp { 538 fsl,pins = < 539 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 540 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ 541 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 542 >; 543 }; 544 545 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 546 fsl,pins = < 547 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ 548 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ 549 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ 550 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ 551 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ 552 553 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 554 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 555 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 556 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 557 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 558 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 559 >; 560 }; 561 562 pinctrl_usdhc2: usdhc2grp { 563 fsl,pins = < 564 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 565 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 566 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 567 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 568 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 569 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 570 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ 571 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 572 >; 573 }; 574 575 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 576 fsl,pins = < 577 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 578 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 579 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 580 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 581 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 582 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 583 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ 584 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 585 >; 586 }; 587 588 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 589 fsl,pins = < 590 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 591 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 592 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 593 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 594 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 595 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 596 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ 597 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 598 >; 599 }; 600 601 pinctrl_usdhc3: usdhc3grp { 602 fsl,pins = < 603 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 604 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 605 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 606 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 607 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 608 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 609 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 610 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 611 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 612 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 613 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 614 >; 615 }; 616 617 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 618 fsl,pins = < 619 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 620 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 621 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 622 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 623 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 624 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 625 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 626 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 627 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 628 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 629 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 630 >; 631 }; 632 633 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 634 fsl,pins = < 635 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 636 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 637 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 638 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 639 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 640 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 641 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 642 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 643 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 644 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 645 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 646 >; 647 }; 648 649 pinctrl_wdog: wdoggrp { 650 fsl,pins = < 651 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 652 >; 653 }; 654}; 655
