1/* 2 * Copyright 2014-2016 Toradex AG 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Copyright 2011 Linaro Ltd. 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * version 2 as published by the Free Software Foundation. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/gpio/gpio.h> 45 46/ { 47 model = "Toradex Colibri iMX6DL/S Module"; 48 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 49 50 backlight: backlight { 51 compatible = "pwm-backlight"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_gpio_bl_on>; 54 pwms = <&pwm3 0 5000000>; 55 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 56 status = "disabled"; 57 }; 58 59 reg_module_3v3: regulator-module-3v3 { 60 compatible = "regulator-fixed"; 61 regulator-name = "+V3.3"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 regulator-always-on; 65 }; 66 67 reg_module_3v3_audio: regulator-module-3v3-audio { 68 compatible = "regulator-fixed"; 69 regulator-name = "+V3.3_AUDIO"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 regulator-always-on; 73 }; 74 75 reg_usb_host_vbus: regulator-usb-host-vbus { 76 compatible = "regulator-fixed"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 79 regulator-name = "usb_host_vbus"; 80 regulator-min-microvolt = <5000000>; 81 regulator-max-microvolt = <5000000>; 82 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ 83 status = "disabled"; 84 }; 85 86 sound { 87 compatible = "fsl,imx-audio-sgtl5000"; 88 model = "imx6dl-colibri-sgtl5000"; 89 ssi-controller = <&ssi1>; 90 audio-codec = <&codec>; 91 audio-routing = 92 "Headphone Jack", "HP_OUT", 93 "LINE_IN", "Line In Jack", 94 "MIC_IN", "Mic Jack", 95 "Mic Jack", "Mic Bias"; 96 mux-int-port = <1>; 97 mux-ext-port = <5>; 98 }; 99 100 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 101 sound_spdif: sound-spdif { 102 compatible = "fsl,imx-audio-spdif"; 103 model = "imx-spdif"; 104 spdif-controller = <&spdif>; 105 spdif-in; 106 spdif-out; 107 status = "disabled"; 108 }; 109}; 110 111&audmux { 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 114 status = "okay"; 115}; 116 117/* Optional on SODIMM 55/63 */ 118&can1 { 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_flexcan1>; 121 status = "disabled"; 122}; 123 124/* Optional on SODIMM 178/188 */ 125&can2 { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_flexcan2>; 128 status = "disabled"; 129}; 130 131/* Colibri SSP */ 132&ecspi4 { 133 cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_ecspi4>; 136 status = "disabled"; 137}; 138 139&fec { 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_enet>; 142 phy-mode = "rmii"; 143 status = "okay"; 144}; 145 146&hdmi { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_hdmi_ddc>; 149 status = "disabled"; 150}; 151 152/* 153 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 154 * touch screen controller 155 */ 156&i2c2 { 157 clock-frequency = <100000>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_i2c2>; 160 status = "okay"; 161 162 pmic: pfuze100@8 { 163 compatible = "fsl,pfuze100"; 164 reg = <0x08>; 165 166 regulators { 167 sw1a_reg: sw1ab { 168 regulator-min-microvolt = <300000>; 169 regulator-max-microvolt = <1875000>; 170 regulator-boot-on; 171 regulator-always-on; 172 regulator-ramp-delay = <6250>; 173 }; 174 175 sw1c_reg: sw1c { 176 regulator-min-microvolt = <300000>; 177 regulator-max-microvolt = <1875000>; 178 regulator-boot-on; 179 regulator-always-on; 180 regulator-ramp-delay = <6250>; 181 }; 182 183 sw3a_reg: sw3a { 184 regulator-min-microvolt = <400000>; 185 regulator-max-microvolt = <1975000>; 186 regulator-boot-on; 187 regulator-always-on; 188 }; 189 190 swbst_reg: swbst { 191 regulator-min-microvolt = <5000000>; 192 regulator-max-microvolt = <5150000>; 193 regulator-boot-on; 194 regulator-always-on; 195 }; 196 197 snvs_reg: vsnvs { 198 regulator-min-microvolt = <1000000>; 199 regulator-max-microvolt = <3000000>; 200 regulator-boot-on; 201 regulator-always-on; 202 }; 203 204 vref_reg: vrefddr { 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 209 /* vgen1: unused */ 210 211 vgen2_reg: vgen2 { 212 regulator-min-microvolt = <800000>; 213 regulator-max-microvolt = <1550000>; 214 regulator-boot-on; 215 regulator-always-on; 216 }; 217 218 /* vgen3: unused */ 219 220 vgen4_reg: vgen4 { 221 regulator-min-microvolt = <1800000>; 222 regulator-max-microvolt = <1800000>; 223 regulator-boot-on; 224 regulator-always-on; 225 }; 226 227 vgen5_reg: vgen5 { 228 regulator-min-microvolt = <1800000>; 229 regulator-max-microvolt = <3300000>; 230 regulator-boot-on; 231 regulator-always-on; 232 }; 233 234 vgen6_reg: vgen6 { 235 regulator-min-microvolt = <1800000>; 236 regulator-max-microvolt = <3300000>; 237 regulator-boot-on; 238 regulator-always-on; 239 }; 240 }; 241 }; 242 243 codec: sgtl5000@a { 244 compatible = "fsl,sgtl5000"; 245 reg = <0x0a>; 246 clocks = <&clks IMX6QDL_CLK_CKO>; 247 VDDA-supply = <®_module_3v3_audio>; 248 VDDIO-supply = <®_module_3v3>; 249 VDDD-supply = <&vgen4_reg>; 250 lrclk-strength = <3>; 251 }; 252 253 /* STMPE811 touch screen controller */ 254 stmpe811@41 { 255 compatible = "st,stmpe811"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_touch_int>; 258 reg = <0x41>; 259 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 260 interrupt-parent = <&gpio6>; 261 interrupt-controller; 262 id = <0>; 263 blocks = <0x5>; 264 irq-trigger = <0x1>; 265 266 stmpe_touchscreen { 267 compatible = "st,stmpe-ts"; 268 /* 3.25 MHz ADC clock speed */ 269 st,adc-freq = <1>; 270 /* 8 sample average control */ 271 st,ave-ctrl = <3>; 272 /* 7 length fractional part in z */ 273 st,fraction-z = <7>; 274 /* 275 * 50 mA typical 80 mA max touchscreen drivers 276 * current limit value 277 */ 278 st,i-drive = <1>; 279 /* 12-bit ADC */ 280 st,mod-12b = <1>; 281 /* internal ADC reference */ 282 st,ref-sel = <0>; 283 /* ADC converstion time: 80 clocks */ 284 st,sample-time = <4>; 285 /* 1 ms panel driver settling time */ 286 st,settling = <3>; 287 /* 5 ms touch detect interrupt delay */ 288 st,touch-det-delay = <5>; 289 }; 290 }; 291}; 292 293/* 294 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 295 */ 296&i2c3 { 297 clock-frequency = <100000>; 298 pinctrl-names = "default", "recovery"; 299 pinctrl-0 = <&pinctrl_i2c3>; 300 pinctrl-1 = <&pinctrl_i2c3_recovery>; 301 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 302 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 303 status = "disabled"; 304}; 305 306/* Colibri PWM<B> */ 307&pwm1 { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_pwm1>; 310 status = "disabled"; 311}; 312 313/* Colibri PWM<D> */ 314&pwm2 { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_pwm2>; 317 status = "disabled"; 318}; 319 320/* Colibri PWM<A> */ 321&pwm3 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_pwm3>; 324 status = "disabled"; 325}; 326 327/* Colibri PWM<C> */ 328&pwm4 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_pwm4>; 331 status = "disabled"; 332}; 333 334/* Optional S/PDIF out on SODIMM 137 */ 335&spdif { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_spdif>; 338 status = "disabled"; 339}; 340 341&ssi1 { 342 status = "okay"; 343}; 344 345/* Colibri UART_A */ 346&uart1 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 349 fsl,dte-mode; 350 uart-has-rtscts; 351 status = "disabled"; 352}; 353 354/* Colibri UART_B */ 355&uart2 { 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_uart2_dte>; 358 fsl,dte-mode; 359 uart-has-rtscts; 360 status = "disabled"; 361}; 362 363/* Colibri UART_C */ 364&uart3 { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_uart3_dte>; 367 fsl,dte-mode; 368 status = "disabled"; 369}; 370 371&usbotg { 372 pinctrl-names = "default"; 373 disable-over-current; 374 dr_mode = "peripheral"; 375 status = "disabled"; 376}; 377 378/* Colibri MMC */ 379&usdhc1 { 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; 382 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ 383 disable-wp; 384 vqmmc-supply = <®_module_3v3>; 385 bus-width = <4>; 386 no-1-8-v; 387 status = "disabled"; 388}; 389 390/* eMMC */ 391&usdhc3 { 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_usdhc3>; 394 vqmmc-supply = <®_module_3v3>; 395 bus-width = <8>; 396 no-1-8-v; 397 non-removable; 398 status = "okay"; 399}; 400 401&weim { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 404 &pinctrl_weim_cs1 &pinctrl_weim_cs2 405 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 406 #address-cells = <2>; 407 #size-cells = <1>; 408 status = "disabled"; 409}; 410 411&iomuxc { 412 pinctrl_audmux: audmuxgrp { 413 fsl,pins = < 414 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 415 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 416 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 417 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 418 /* SGTL5000 sys_mclk */ 419 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 420 >; 421 }; 422 423 pinctrl_cam_mclk: cammclkgrp { 424 fsl,pins = < 425 /* Parallel Camera CAM sys_mclk */ 426 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 427 >; 428 }; 429 430 pinctrl_ecspi4: ecspi4grp { 431 fsl,pins = < 432 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 433 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 434 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 435 /* SPI CS */ 436 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 437 >; 438 }; 439 440 pinctrl_enet: enetgrp { 441 fsl,pins = < 442 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 443 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 444 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 445 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 446 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 447 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 448 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 449 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 450 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 451 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 452 >; 453 }; 454 455 pinctrl_flexcan1: flexcan1grp { 456 fsl,pins = < 457 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 458 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 459 >; 460 }; 461 462 pinctrl_flexcan2: flexcan2grp { 463 fsl,pins = < 464 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 465 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 466 >; 467 }; 468 469 pinctrl_gpio_bl_on: gpioblon { 470 fsl,pins = < 471 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 472 >; 473 }; 474 475 pinctrl_gpio_keys: gpiokeys { 476 fsl,pins = < 477 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 478 >; 479 }; 480 481 pinctrl_hdmi_ddc: hdmiddcgrp { 482 fsl,pins = < 483 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 484 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 485 >; 486 }; 487 488 pinctrl_i2c2: i2c2grp { 489 fsl,pins = < 490 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 491 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 492 >; 493 }; 494 495 pinctrl_i2c3: i2c3grp { 496 fsl,pins = < 497 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 498 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 499 >; 500 }; 501 502 pinctrl_i2c3_recovery: i2c3recoverygrp { 503 fsl,pins = < 504 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 505 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 506 >; 507 }; 508 509 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 510 fsl,pins = < 511 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 512 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 513 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 514 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 515 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 516 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 517 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 518 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 519 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 520 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 521 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 522 /* Disable PWM pins on camera interface */ 523 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 524 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 525 >; 526 }; 527 528 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 529 fsl,pins = < 530 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 531 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 532 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 533 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 534 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 535 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 536 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 537 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 538 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 539 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 540 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 541 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 542 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 543 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 544 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 545 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 546 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 547 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 548 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 549 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 550 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 551 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 552 >; 553 }; 554 555 pinctrl_mic_gnd: gpiomicgnd { 556 fsl,pins = < 557 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 558 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 559 >; 560 }; 561 562 pinctrl_mmc_cd: gpiommccd { 563 fsl,pins = < 564 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 565 >; 566 }; 567 568 pinctrl_pwm1: pwm1grp { 569 fsl,pins = < 570 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 571 >; 572 }; 573 574 pinctrl_pwm2: pwm2grp { 575 fsl,pins = < 576 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 577 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 578 >; 579 }; 580 581 pinctrl_pwm3: pwm3grp { 582 fsl,pins = < 583 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 584 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 585 >; 586 }; 587 588 pinctrl_pwm4: pwm4grp { 589 fsl,pins = < 590 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 591 >; 592 }; 593 594 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 595 fsl,pins = < 596 /* USBH_EN */ 597 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 598 >; 599 }; 600 601 pinctrl_spdif: spdifgrp { 602 fsl,pins = < 603 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 604 >; 605 }; 606 607 pinctrl_touch_int: gpiotouchintgrp { 608 fsl,pins = < 609 /* STMPE811 interrupt */ 610 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 611 >; 612 }; 613 614 pinctrl_uart1_dce: uart1dcegrp { 615 fsl,pins = < 616 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 617 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 618 >; 619 }; 620 621 /* DTE mode */ 622 pinctrl_uart1_dte: uart1dtegrp { 623 fsl,pins = < 624 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 625 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 626 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 627 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 628 >; 629 }; 630 631 /* Additional DTR, DSR, DCD */ 632 pinctrl_uart1_ctrl: uart1ctrlgrp { 633 fsl,pins = < 634 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 635 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 636 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 637 >; 638 }; 639 640 pinctrl_uart2_dte: uart2dtegrp { 641 fsl,pins = < 642 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 643 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 644 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 645 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 646 >; 647 }; 648 649 pinctrl_uart3_dte: uart3dtegrp { 650 fsl,pins = < 651 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 652 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 653 >; 654 }; 655 656 pinctrl_usbc_det: usbcdetgrp { 657 fsl,pins = < 658 /* USBC_DET */ 659 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 660 /* USBC_DET_EN */ 661 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 662 /* USBC_DET_OVERWRITE */ 663 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 664 >; 665 }; 666 667 pinctrl_usdhc1: usdhc1grp { 668 fsl,pins = < 669 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 670 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 671 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 672 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 673 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 674 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 675 >; 676 }; 677 678 pinctrl_usdhc3: usdhc3grp { 679 fsl,pins = < 680 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 681 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 682 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 683 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 684 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 685 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 686 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 687 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 688 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 689 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 690 /* eMMC reset */ 691 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 692 >; 693 }; 694 695 pinctrl_weim_cs0: weimcs0grp { 696 fsl,pins = < 697 /* nEXT_CS0 */ 698 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 699 >; 700 }; 701 702 pinctrl_weim_cs1: weimcs1grp { 703 fsl,pins = < 704 /* nEXT_CS1 */ 705 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 706 >; 707 }; 708 709 pinctrl_weim_cs2: weimcs2grp { 710 fsl,pins = < 711 /* nEXT_CS2 */ 712 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 713 >; 714 }; 715 716 pinctrl_weim_sram: weimsramgrp { 717 fsl,pins = < 718 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 719 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 720 /* Data */ 721 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 722 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 723 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 724 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 725 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 726 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 727 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 728 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 729 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 730 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 731 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 732 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 733 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 734 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 735 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 736 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 737 /* Address */ 738 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 739 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 740 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 741 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 742 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 743 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 744 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 745 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 746 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 747 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 748 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 749 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 750 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 751 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 752 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 753 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 754 >; 755 }; 756 757 pinctrl_weim_rdnwr: weimrdnwr { 758 fsl,pins = < 759 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 760 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 761 >; 762 }; 763 764 pinctrl_weim_npwe: weimnpwe { 765 fsl,pins = < 766 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 767 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 768 >; 769 }; 770 771 /* ADDRESS[16:18] [25] used as GPIO */ 772 pinctrl_weim_gpio_1: weimgpio-1 { 773 fsl,pins = < 774 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 775 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 776 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 777 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 778 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 779 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 780 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 781 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 782 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 783 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 784 >; 785 }; 786 787 /* ADDRESS[19:24] used as GPIO */ 788 pinctrl_weim_gpio_2: weimgpio-2 { 789 fsl,pins = < 790 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 791 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 792 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 793 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 794 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 795 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 796 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 797 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 798 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 799 >; 800 }; 801 802 /* DATA[16:31] used as GPIO */ 803 pinctrl_weim_gpio_3: weimgpio-3 { 804 fsl,pins = < 805 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 806 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 807 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 808 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 809 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 810 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 811 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 812 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 813 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 814 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 815 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 816 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 817 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 818 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 819 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 820 >; 821 }; 822 823 /* DQM[0:3] used as GPIO */ 824 pinctrl_weim_gpio_4: weimgpio-4 { 825 fsl,pins = < 826 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 827 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 828 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 829 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 830 >; 831 }; 832 833 /* RDY used as GPIO */ 834 pinctrl_weim_gpio_5: weimgpio-5 { 835 fsl,pins = < 836 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 837 >; 838 }; 839 840 /* ADDRESS[16] DATA[30] used as GPIO */ 841 pinctrl_weim_gpio_6: weimgpio-6 { 842 fsl,pins = < 843 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 844 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 845 >; 846 }; 847}; 848
