1/* 2 * support for the imx6 based aristainetos2 board 3 * 4 * Copyright (C) 2015 Heiko Schocher <hs@denx.de> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * version 2 as published by the Free Software Foundation. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43#include <dt-bindings/gpio/gpio.h> 44#include <dt-bindings/clock/imx6qdl-clock.h> 45 46/ { 47 backlight: backlight { 48 compatible = "pwm-backlight"; 49 pwms = <&pwm1 0 5000000>; 50 brightness-levels = <0 4 8 16 32 64 128 255>; 51 default-brightness-level = <7>; 52 enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; 53 }; 54 55 reg_2p5v: regulator-2p5v { 56 compatible = "regulator-fixed"; 57 regulator-name = "2P5V"; 58 regulator-min-microvolt = <2500000>; 59 regulator-max-microvolt = <2500000>; 60 regulator-always-on; 61 }; 62 63 reg_3p3v: regulator-3p3v { 64 compatible = "regulator-fixed"; 65 regulator-name = "3P3V"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 regulator-always-on; 69 }; 70 71 reg_usbh1_vbus: regulator-usbh1-vbus { 72 compatible = "regulator-fixed"; 73 enable-active-high; 74 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; 77 regulator-name = "usb_h1_vbus"; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 }; 81 82 reg_usbotg_vbus: regulator-usbotg-vbus { 83 compatible = "regulator-fixed"; 84 enable-active-high; 85 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; 88 regulator-name = "usb_otg_vbus"; 89 regulator-min-microvolt = <5000000>; 90 regulator-max-microvolt = <5000000>; 91 }; 92}; 93 94&audmux { 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_audmux>; 97 status = "okay"; 98}; 99 100&can1 { 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_flexcan1>; 103 status = "okay"; 104}; 105 106&can2 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_flexcan2>; 109 status = "okay"; 110}; 111 112&ecspi1 { 113 cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH 114 &gpio4 10 GPIO_ACTIVE_HIGH 115 &gpio4 11 GPIO_ACTIVE_HIGH>; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_ecspi1>; 118 status = "okay"; 119}; 120 121&ecspi2 { 122 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_ecspi2>; 125 status = "okay"; 126}; 127 128&ecspi4 { 129 cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_ecspi4>; 132 status = "okay"; 133 134 flash: m25p80@1 { 135 #address-cells = <1>; 136 #size-cells = <1>; 137 compatible = "micron,n25q128a11", "jedec,spi-nor"; 138 spi-max-frequency = <20000000>; 139 reg = <1>; 140 }; 141}; 142 143&i2c1 { 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_i2c1>; 146 status = "okay"; 147 148 pmic@58 { 149 compatible = "dlg,da9063"; 150 reg = <0x58>; 151 interrupt-parent = <&gpio1>; 152 interrupts = <04 0x8>; 153 154 regulators { 155 bcore1 { 156 regulator-name = "bcore1"; 157 regulator-always-on = <1>; 158 regulator-min-microvolt = <300000>; 159 regulator-max-microvolt = <3300000>; 160 }; 161 162 bcore2 { 163 regulator-name = "bcore2"; 164 regulator-always-on = <1>; 165 regulator-min-microvolt = <300000>; 166 regulator-max-microvolt = <3300000>; 167 }; 168 169 bpro { 170 regulator-name = "bpro"; 171 regulator-always-on = <1>; 172 regulator-min-microvolt = <300000>; 173 regulator-max-microvolt = <3300000>; 174 }; 175 176 bperi { 177 regulator-name = "bperi"; 178 regulator-always-on = <1>; 179 regulator-min-microvolt = <300000>; 180 regulator-max-microvolt = <3300000>; 181 }; 182 183 bmem { 184 regulator-name = "bmem"; 185 regulator-always-on = <1>; 186 regulator-min-microvolt = <300000>; 187 regulator-max-microvolt = <3300000>; 188 }; 189 190 ldo2 { 191 regulator-name = "ldo2"; 192 regulator-always-on = <1>; 193 regulator-min-microvolt = <300000>; 194 regulator-max-microvolt = <1800000>; 195 }; 196 197 ldo3 { 198 regulator-name = "ldo3"; 199 regulator-always-on = <1>; 200 regulator-min-microvolt = <300000>; 201 regulator-max-microvolt = <3300000>; 202 }; 203 204 ldo4 { 205 regulator-name = "ldo4"; 206 regulator-always-on = <1>; 207 regulator-min-microvolt = <300000>; 208 regulator-max-microvolt = <3300000>; 209 }; 210 211 ldo5 { 212 regulator-name = "ldo5"; 213 regulator-always-on = <1>; 214 regulator-min-microvolt = <300000>; 215 regulator-max-microvolt = <3300000>; 216 }; 217 218 ldo6 { 219 regulator-name = "ldo6"; 220 regulator-always-on = <1>; 221 regulator-min-microvolt = <300000>; 222 regulator-max-microvolt = <3300000>; 223 }; 224 225 ldo7 { 226 regulator-name = "ldo7"; 227 regulator-always-on = <1>; 228 regulator-min-microvolt = <300000>; 229 regulator-max-microvolt = <3300000>; 230 }; 231 232 ldo8 { 233 regulator-name = "ldo8"; 234 regulator-always-on = <1>; 235 regulator-min-microvolt = <300000>; 236 regulator-max-microvolt = <3300000>; 237 }; 238 239 ldo9 { 240 regulator-name = "ldo9"; 241 regulator-always-on = <1>; 242 regulator-min-microvolt = <300000>; 243 regulator-max-microvolt = <3300000>; 244 }; 245 246 ldo10 { 247 regulator-name = "ldo10"; 248 regulator-always-on = <1>; 249 regulator-min-microvolt = <300000>; 250 regulator-max-microvolt = <3300000>; 251 }; 252 253 ldo11 { 254 regulator-name = "ldo11"; 255 regulator-always-on = <1>; 256 regulator-min-microvolt = <300000>; 257 regulator-max-microvolt = <3300000>; 258 }; 259 260 bio { 261 regulator-name = "bio"; 262 regulator-always-on = <1>; 263 regulator-min-microvolt = <1800000>; 264 regulator-max-microvolt = <1800000>; 265 }; 266 }; 267 }; 268 269 tmp103: tmp103@71 { 270 compatible = "ti,tmp103"; 271 reg = <0x71>; 272 }; 273}; 274 275&i2c2 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_i2c2>; 278 status = "okay"; 279}; 280 281&i2c3 { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_i2c3>; 284 status = "okay"; 285 286 expander: tca6416@20 { 287 compatible = "ti,tca6416"; 288 reg = <0x20>; 289 #gpio-cells = <2>; 290 gpio-controller; 291 }; 292 293 rtc@68 { 294 compatible = "dallas,m41t00"; 295 reg = <0x68>; 296 }; 297}; 298 299&i2c4 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_i2c4>; 302 status = "okay"; 303 304 eeprom@50{ 305 compatible = "atmel,24c64"; 306 reg = <0x50>; 307 }; 308 309 eeprom@57{ 310 compatible = "atmel,24c64"; 311 reg = <0x57>; 312 }; 313}; 314 315&fec { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_enet>; 318 phy-mode = "rgmii"; 319 phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; 320 txd0-skew-ps = <0>; 321 txd1-skew-ps = <0>; 322 txd2-skew-ps = <0>; 323 txd3-skew-ps = <0>; 324 status = "okay"; 325}; 326 327&gpmi { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_gpmi_nand>; 330 status = "okay"; 331}; 332 333&pcie { 334 reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; 335 status = "okay"; 336}; 337 338&pwm1 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_pwm1>; 341 status = "okay"; 342}; 343 344&uart1 { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_uart1>; 347 uart-has-rtscts; 348 status = "okay"; 349}; 350 351&uart2 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_uart2>; 354 status = "okay"; 355}; 356 357&uart3 { 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_uart3>; 360 uart-has-rtscts; 361 status = "okay"; 362}; 363 364&uart4 { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_uart4>; 367 status = "okay"; 368}; 369 370&usbh1 { 371 vbus-supply = <®_usbh1_vbus>; 372 dr_mode = "host"; 373 status = "okay"; 374}; 375 376&usbotg { 377 vbus-supply = <®_usbotg_vbus>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_usbotg>; 380 disable-over-current; 381 dr_mode = "host"; 382 status = "okay"; 383}; 384 385&usdhc1 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_usdhc1>; 388 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 389 no-1-8-v; 390 status = "okay"; 391}; 392 393&usdhc2 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_usdhc2>; 396 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; 397 wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 398 no-1-8-v; 399 status = "okay"; 400}; 401 402&iomuxc { 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_gpio>; 405 406 pinctrl_audmux: audmux { 407 fsl,pins = < 408 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 409 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 410 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 411 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 412 >; 413 }; 414 415 pinctrl_ecspi1: ecspi1grp { 416 fsl,pins = < 417 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 418 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 419 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 420 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ 421 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ 422 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ 423 >; 424 }; 425 426 pinctrl_ecspi2: ecspi2grp { 427 fsl,pins = < 428 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 429 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 430 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 431 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ 432 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ 433 >; 434 }; 435 436 pinctrl_ecspi4: ecspi4grp { 437 fsl,pins = < 438 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 439 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 440 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 441 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ 442 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ 443 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ 444 >; 445 }; 446 447 pinctrl_enet: enetgrp { 448 fsl,pins = < 449 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 450 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 451 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 452 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 453 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 454 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 455 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 456 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 457 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 458 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 459 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 460 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 461 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 462 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 463 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 464 >; 465 }; 466 467 pinctrl_flexcan1: flexcan1grp { 468 fsl,pins = < 469 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 470 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 471 >; 472 }; 473 474 pinctrl_flexcan2: flexcan2grp { 475 fsl,pins = < 476 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 477 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 478 >; 479 }; 480 481 pinctrl_gpio: gpiogrp { 482 fsl,pins = < 483 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ 484 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ 485 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ 486 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ 487 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ 488 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ 489 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ 490 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ 491 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ 492 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ 493 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ 494 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ 495 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ 496 >; 497 }; 498 499 pinctrl_gpmi_nand: gpmi-nand { 500 fsl,pins = < 501 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 502 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 503 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 504 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 505 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 506 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 507 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 508 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 509 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 510 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 511 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 512 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 513 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 514 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 515 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 516 >; 517 }; 518 519 pinctrl_i2c1: i2c1grp { 520 fsl,pins = < 521 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 522 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 523 >; 524 }; 525 526 pinctrl_i2c2: i2c2grp { 527 fsl,pins = < 528 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 529 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 530 >; 531 }; 532 533 pinctrl_i2c3: i2c3grp { 534 fsl,pins = < 535 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 536 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 537 >; 538 }; 539 540 pinctrl_i2c4: i2c4grp { 541 fsl,pins = < 542 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 543 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 544 >; 545 }; 546 547 pinctrl_pwm1: pwm1grp { 548 fsl,pins = < 549 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 550 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ 551 >; 552 }; 553 554 pinctrl_uart1: uart1grp { 555 fsl,pins = < 556 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 557 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 558 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 559 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 560 >; 561 }; 562 563 pinctrl_uart2: uart2grp { 564 fsl,pins = < 565 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 566 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 567 >; 568 }; 569 570 pinctrl_uart3: uart3grp { 571 fsl,pins = < 572 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 573 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 574 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 575 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 576 >; 577 }; 578 579 pinctrl_uart4: uart4grp { 580 fsl,pins = < 581 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 582 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 583 >; 584 }; 585 586 pinctrl_usbotg: usbotggrp { 587 fsl,pins = < 588 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 589 >; 590 }; 591 592 pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { 593 fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>; 594 }; 595 596 pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { 597 fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>; 598 }; 599 600 pinctrl_usdhc1: usdhc1grp { 601 fsl,pins = < 602 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 603 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 604 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 605 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 606 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 607 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 608 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ 609 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ 610 >; 611 }; 612 613 pinctrl_usdhc2: usdhc2grp { 614 fsl,pins = < 615 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 616 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 617 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 618 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 619 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 620 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 621 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ 622 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ 623 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ 624 >; 625 }; 626}; 627
