1/*
2 * Copyright 2013 Data Modul AG
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include <dt-bindings/gpio/gpio.h>
15#include "imx6q.dtsi"
16
17/ {
18	model = "Data Modul eDM-QMX6 Board";
19	compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
20
21	chosen {
22		stdout-path = &uart2;
23	};
24
25	aliases {
26		gpio7 = &stmpe_gpio1;
27		gpio8 = &stmpe_gpio2;
28		stmpe-i2c0 = &stmpe1;
29		stmpe-i2c1 = &stmpe2;
30	};
31
32	memory@10000000 {
33		reg = <0x10000000 0x80000000>;
34	};
35
36	regulators {
37		compatible = "simple-bus";
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		reg_3p3v: regulator@0 {
42			compatible = "regulator-fixed";
43			reg = <0>;
44			regulator-name = "3P3V";
45			regulator-min-microvolt = <3300000>;
46			regulator-max-microvolt = <3300000>;
47			regulator-always-on;
48		};
49
50		reg_usb_otg_switch: regulator@1 {
51			compatible = "regulator-fixed";
52			reg = <1>;
53			regulator-name = "usb_otg_switch";
54			regulator-min-microvolt = <5000000>;
55			regulator-max-microvolt = <5000000>;
56			gpio = <&gpio7 12 0>;
57			regulator-boot-on;
58			regulator-always-on;
59		};
60
61		reg_usb_host1: regulator@2 {
62			compatible = "regulator-fixed";
63			reg = <2>;
64			regulator-name = "usb_host1_en";
65			regulator-min-microvolt = <3300000>;
66			regulator-max-microvolt = <3300000>;
67			gpio = <&gpio3 31 0>;
68			enable-active-high;
69		};
70	};
71
72	gpio-leds {
73		compatible = "gpio-leds";
74
75		led-blue {
76			label = "blue";
77			gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
78			linux,default-trigger = "heartbeat";
79		};
80
81		led-green {
82			label = "green";
83			gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
84		};
85
86		led-pink {
87			label = "pink";
88			gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
89		};
90
91		led-red {
92			label = "red";
93			gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
94		};
95	};
96};
97
98&can1 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_can1>;
101	status = "okay";
102};
103
104&ecspi5 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_ecspi5>;
107	cs-gpios = <&gpio1 12 0>;
108	status = "okay";
109
110	flash: m25p80@0 {
111		compatible = "m25p80", "jedec,spi-nor";
112		spi-max-frequency = <40000000>;
113		reg = <0>;
114	};
115};
116
117&fec {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_enet>;
120	phy-mode = "rgmii";
121	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
122	phy-supply = <&vgen2_1v2_eth>;
123	status = "okay";
124};
125
126&i2c1 {
127	clock-frequency = <100000>;
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_i2c1>;
130	status = "okay";
131};
132
133&i2c2 {
134	clock-frequency = <100000>;
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_i2c2
137		     &pinctrl_stmpe1
138		     &pinctrl_stmpe2
139		     &pinctrl_pfuze>;
140	status = "okay";
141
142	pmic: pfuze100@8 {
143		compatible = "fsl,pfuze100";
144		reg = <0x08>;
145		interrupt-parent = <&gpio3>;
146		interrupts = <20 8>;
147
148		regulators {
149			sw1a_reg: sw1ab {
150				regulator-min-microvolt = <300000>;
151				regulator-max-microvolt = <1875000>;
152				regulator-boot-on;
153				regulator-always-on;
154			};
155
156			sw1c_reg: sw1c {
157				regulator-min-microvolt = <300000>;
158				regulator-max-microvolt = <1875000>;
159				regulator-boot-on;
160				regulator-always-on;
161			};
162
163			sw2_reg: sw2 {
164				regulator-min-microvolt = <800000>;
165				regulator-max-microvolt = <3300000>;
166				regulator-boot-on;
167				regulator-always-on;
168			};
169
170			sw3a_reg: sw3a {
171				regulator-min-microvolt = <400000>;
172				regulator-max-microvolt = <1975000>;
173				regulator-boot-on;
174				regulator-always-on;
175			};
176
177			sw3b_reg: sw3b {
178				regulator-min-microvolt = <400000>;
179				regulator-max-microvolt = <1975000>;
180				regulator-boot-on;
181				regulator-always-on;
182			};
183
184			sw4_reg: sw4 {
185				regulator-min-microvolt = <400000>;
186				regulator-max-microvolt = <1975000>;
187				regulator-always-on;
188			};
189
190			swbst_reg: swbst {
191				regulator-min-microvolt = <5000000>;
192				regulator-max-microvolt = <5150000>;
193				regulator-always-on;
194			};
195
196			snvs_reg: vsnvs {
197				regulator-min-microvolt = <1000000>;
198				regulator-max-microvolt = <3000000>;
199				regulator-boot-on;
200				regulator-always-on;
201			};
202
203			vref_reg: vrefddr {
204				regulator-boot-on;
205				regulator-always-on;
206			};
207
208			vgen1_reg: vgen1 {
209				regulator-min-microvolt = <800000>;
210				regulator-max-microvolt = <1550000>;
211			};
212
213			vgen2_1v2_eth: vgen2 {
214				regulator-min-microvolt = <800000>;
215				regulator-max-microvolt = <1550000>;
216			};
217
218			vdd_high_in: vgen3 {
219				regulator-min-microvolt = <1800000>;
220				regulator-max-microvolt = <3300000>;
221				regulator-boot-on;
222				regulator-always-on;
223			};
224
225			vgen4_reg: vgen4 {
226				regulator-min-microvolt = <1800000>;
227				regulator-max-microvolt = <3300000>;
228				regulator-always-on;
229			};
230
231			vgen5_reg: vgen5 {
232				regulator-min-microvolt = <1800000>;
233				regulator-max-microvolt = <3300000>;
234				regulator-always-on;
235			};
236
237			vgen6_reg: vgen6 {
238				regulator-min-microvolt = <1800000>;
239				regulator-max-microvolt = <3300000>;
240				regulator-always-on;
241			};
242		};
243	};
244
245	stmpe1: stmpe1601@40 {
246		compatible = "st,stmpe1601";
247		reg = <0x40>;
248		interrupts = <30 0>;
249		interrupt-parent = <&gpio3>;
250		vcc-supply = <&sw2_reg>;
251		vio-supply = <&sw2_reg>;
252
253		stmpe_gpio1: stmpe_gpio {
254			#gpio-cells = <2>;
255			compatible = "st,stmpe-gpio";
256		};
257	};
258
259	stmpe2: stmpe1601@44 {
260		compatible = "st,stmpe1601";
261		reg = <0x44>;
262		interrupts = <2 0>;
263		interrupt-parent = <&gpio5>;
264		vcc-supply = <&sw2_reg>;
265		vio-supply = <&sw2_reg>;
266
267		stmpe_gpio2: stmpe_gpio {
268			#gpio-cells = <2>;
269			compatible = "st,stmpe-gpio";
270		};
271	};
272
273	temp1: ad7414@4c {
274		compatible = "ad,ad7414";
275		reg = <0x4c>;
276	};
277
278	temp2: ad7414@4d {
279		compatible = "ad,ad7414";
280		reg = <0x4d>;
281	};
282
283	rtc: m41t62@68 {
284		compatible = "st,m41t62";
285		reg = <0x68>;
286	};
287};
288
289&i2c3 {
290	clock-frequency = <100000>;
291	pinctrl-names = "default";
292	pinctrl-0 = <&pinctrl_i2c3>;
293	status = "okay";
294};
295
296&iomuxc {
297	pinctrl-names = "default";
298	pinctrl-0 = <&pinctrl_hog>;
299
300	imx6q-dmo-edmqmx6 {
301		pinctrl_hog: hoggrp {
302			fsl,pins = <
303				MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
304				MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
305			>;
306		};
307
308		pinctrl_can1: can1grp {
309			fsl,pins = <
310				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
311				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
312			>;
313		};
314
315		pinctrl_ecspi5: ecspi5rp-1 {
316			fsl,pins = <
317				MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO	0x80000000
318				MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI		0x80000000
319				MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK		0x80000000
320				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x80000000
321			>;
322		};
323
324		pinctrl_enet: enetgrp {
325			fsl,pins = <
326				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
327				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
328				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
329				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
330				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
331				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
332				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
333				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
334				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
335				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
336				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
337				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
338				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
339				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
340				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
341				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0
342				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
343			>;
344		};
345
346		pinctrl_i2c1: i2c1grp {
347			fsl,pins = <
348				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
349				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
350			>;
351		};
352
353		pinctrl_i2c2: i2c2grp {
354			fsl,pins = <
355				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
356				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
357			>;
358		};
359
360		pinctrl_i2c3: i2c3grp {
361			fsl,pins = <
362				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
363				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
364			>;
365		};
366
367		pinctrl_pcie: pciegrp {
368			fsl,pins = <
369				MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x100b1
370			>;
371		};
372
373		pinctrl_pfuze: pfuze100grp1 {
374			fsl,pins = <
375				MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x80000000
376			>;
377		};
378
379		pinctrl_stmpe1: stmpe1grp {
380			fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
381		};
382
383		pinctrl_stmpe2: stmpe2grp {
384			fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
385		};
386
387		pinctrl_uart1: uart1grp {
388			fsl,pins = <
389				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
390				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
391			>;
392		};
393
394		pinctrl_uart2: uart2grp {
395			fsl,pins = <
396				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
397				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
398			>;
399		};
400
401		pinctrl_usbotg: usbotggrp {
402			fsl,pins = <
403				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
404			>;
405		};
406
407		pinctrl_usdhc3: usdhc3grp {
408			fsl,pins = <
409				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
410				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
411				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
412				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
413				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
414				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
415			>;
416		};
417
418		pinctrl_usdhc4: usdhc4grp {
419			fsl,pins = <
420				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
421				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
422				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
423				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
424				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
425				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
426				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
427				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
428				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
429				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
430			>;
431		};
432	};
433};
434
435&pcie {
436	pinctrl-names = "default";
437	pinctrl-0 = <&pinctrl_pcie>;
438	reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
439	status = "okay";
440};
441
442&sata {
443	status = "okay";
444};
445
446&uart1 {
447	pinctrl-names = "default";
448	pinctrl-0 = <&pinctrl_uart1>;
449	status = "okay";
450};
451
452&uart2 {
453	pinctrl-names = "default";
454	pinctrl-0 = <&pinctrl_uart2>;
455	status = "okay";
456};
457
458&usbh1 {
459	vbus-supply = <&reg_usb_host1>;
460	disable-over-current;
461	dr_mode = "host";
462	status = "okay";
463};
464
465&usbotg {
466	pinctrl-names = "default";
467	pinctrl-0 = <&pinctrl_usbotg>;
468	disable-over-current;
469	status = "okay";
470};
471
472&usdhc3 {
473	pinctrl-names = "default";
474	pinctrl-0 = <&pinctrl_usdhc3>;
475	vmmc-supply = <&reg_3p3v>;
476	status = "okay";
477};
478
479&usdhc4 {
480	pinctrl-names = "default";
481	pinctrl-0 = <&pinctrl_usdhc4>;
482	vmmc-supply = <&reg_3p3v>;
483	non-removable;
484	bus-width = <8>;
485	status = "okay";
486};
487