1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2018 BTicino 4 * Copyright (C) 2018 Amarula Solutions B.V. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include "imx6dl.dtsi" 11 12/ { 13 model = "BTicino i.MX6DL Mamoj board"; 14 compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; 15 16 backlight_lcd: backlight-lcd { 17 compatible = "pwm-backlight"; 18 pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ 19 brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; 20 default-brightness-level = <7>; 21 }; 22 23 display: disp0 { 24 compatible = "fsl,imx-parallel-display"; 25 #address-cells = <1>; 26 #size-cells = <0>; 27 interface-pix-fmt = "rgb24"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 30 status = "okay"; 31 32 port@0 { 33 reg = <0>; 34 35 lcd_display_in: endpoint { 36 remote-endpoint = <&ipu1_di0_disp0>; 37 }; 38 }; 39 40 port@1 { 41 reg = <1>; 42 43 lcd_display_out: endpoint { 44 remote-endpoint = <&lcd_panel_in>; 45 }; 46 }; 47 }; 48 49 panel-lcd { 50 compatible = "rocktech,rk070er9427"; 51 backlight = <&backlight_lcd>; 52 power-supply = <®_lcd_lr>; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; 55 56 port { 57 lcd_panel_in: endpoint { 58 remote-endpoint = <&lcd_display_out>; 59 }; 60 }; 61 }; 62 63 reg_lcd_3v3: regulator-lcd-dvdd { 64 compatible = "regulator-fixed"; 65 regulator-name = "lcd-dvdd"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&gpio3 1 0>; 69 enable-active-high; 70 startup-delay-us = <21000>; 71 }; 72 73 reg_lcd_power: regulator-lcd-power { 74 compatible = "regulator-fixed"; 75 regulator-name = "lcd-enable"; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 gpio = <&gpio3 6 0>; 79 enable-active-high; 80 vin-supply = <®_lcd_3v3>; 81 }; 82 83 reg_lcd_vgl: regulator-lcd-vgl { 84 compatible = "regulator-fixed"; 85 regulator-name = "lcd-vgl"; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; 89 startup-delay-us = <6000>; 90 enable-active-high; 91 vin-supply = <®_lcd_power>; 92 }; 93 94 reg_lcd_vgh: regulator-lcd-vgh { 95 compatible = "regulator-fixed"; 96 regulator-name = "lcd-vgh"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 100 startup-delay-us = <6000>; 101 enable-active-high; 102 vin-supply = <®_lcd_avdd>; 103 }; 104 105 reg_lcd_vcom: regulator-lcd-vcom { 106 compatible = "regulator-fixed"; 107 regulator-name = "lcd-vcom"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; 111 startup-delay-us = <11000>; 112 enable-active-high; 113 vin-supply = <®_lcd_vgh>; 114 }; 115 116 reg_lcd_lr: regulator-lcd-lr { 117 compatible = "regulator-fixed"; 118 regulator-name = "lcd-lr"; 119 regulator-min-microvolt = <3300000>; 120 regulator-max-microvolt = <3300000>; 121 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 122 enable-active-high; 123 vin-supply = <®_lcd_vcom>; 124 }; 125 126 reg_lcd_avdd: regulator-lcd-avdd { 127 compatible = "regulator-fixed"; 128 regulator-name = "lcd-avdd"; 129 regulator-min-microvolt = <10280000>; 130 regulator-max-microvolt = <10280000>; 131 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; 132 startup-delay-us = <6000>; 133 enable-active-high; 134 vin-supply = <®_lcd_vgl>; 135 }; 136 137 reg_usb_host: regulator-usb-vbus { 138 compatible = "regulator-fixed"; 139 regulator-name = "usbhost-vbus"; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_usbhost>; 142 regulator-min-microvolt = <50000000>; 143 regulator-max-microvolt = <50000000>; 144 gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; 145 enable-active-high; 146 }; 147 148 reg_wl18xx_vmmc: regulator-wl18xx-vmcc { 149 compatible = "regulator-fixed"; 150 regulator-name = "vwl1807"; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_wlan>; 153 regulator-min-microvolt = <1800000>; 154 regulator-max-microvolt = <1800000>; 155 gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; 156 startup-delay-us = <70000>; 157 enable-active-high; 158 }; 159}; 160 161&fec { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_enet>; 164 phy-mode = "mii"; 165 status = "okay"; 166}; 167 168&i2c3 { 169 clock-frequency = <400000>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_i2c3>; 172 status = "okay"; 173}; 174 175&i2c4 { 176 clock-frequency = <100000>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_i2c4>; 179 status = "okay"; 180 181 pfuze100: pmic@8 { 182 compatible = "fsl,pfuze100"; 183 reg = <0x08>; 184 185 regulators { 186 /* CPU vdd_arm core */ 187 sw1a_reg: sw1ab { 188 regulator-min-microvolt = <300000>; 189 regulator-max-microvolt = <1875000>; 190 regulator-boot-on; 191 regulator-always-on; 192 regulator-ramp-delay = <6250>; 193 }; 194 195 /* SOC vdd_soc */ 196 sw1c_reg: sw1c { 197 regulator-min-microvolt = <300000>; 198 regulator-max-microvolt = <1875000>; 199 regulator-boot-on; 200 regulator-always-on; 201 regulator-ramp-delay = <6250>; 202 }; 203 204 /* I/O power GEN_3V3 */ 205 sw2_reg: sw2 { 206 regulator-min-microvolt = <800000>; 207 regulator-max-microvolt = <3300000>; 208 regulator-boot-on; 209 regulator-always-on; 210 }; 211 212 /* DDR memory */ 213 sw3a_reg: sw3a { 214 regulator-min-microvolt = <400000>; 215 regulator-max-microvolt = <1975000>; 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 220 /* DDR memory */ 221 sw3b_reg: sw3b { 222 regulator-min-microvolt = <400000>; 223 regulator-max-microvolt = <1975000>; 224 regulator-boot-on; 225 regulator-always-on; 226 }; 227 228 /* not used */ 229 sw4_reg: sw4 { 230 regulator-min-microvolt = <800000>; 231 regulator-max-microvolt = <3300000>; 232 }; 233 234 /* not used */ 235 swbst_reg: swbst { 236 regulator-min-microvolt = <5000000>; 237 regulator-max-microvolt = <5150000>; 238 }; 239 240 /* PMIC vsnvs. EX boot mode */ 241 snvs_reg: vsnvs { 242 regulator-min-microvolt = <1000000>; 243 regulator-max-microvolt = <3000000>; 244 regulator-boot-on; 245 regulator-always-on; 246 }; 247 248 vref_reg: vrefddr { 249 regulator-boot-on; 250 regulator-always-on; 251 }; 252 253 /* not used */ 254 vgen1_reg: vgen1 { 255 regulator-min-microvolt = <800000>; 256 regulator-max-microvolt = <1550000>; 257 }; 258 259 /* not used */ 260 vgen2_reg: vgen2 { 261 regulator-min-microvolt = <800000>; 262 regulator-max-microvolt = <1550000>; 263 }; 264 265 /* not used */ 266 vgen3_reg: vgen3 { 267 regulator-min-microvolt = <1800000>; 268 regulator-max-microvolt = <3300000>; 269 }; 270 271 /* 1v8 general power */ 272 vgen4_reg: vgen4 { 273 regulator-min-microvolt = <1800000>; 274 regulator-max-microvolt = <3300000>; 275 regulator-always-on; 276 }; 277 278 /* 2v8 general power IMX6 */ 279 vgen5_reg: vgen5 { 280 regulator-min-microvolt = <1800000>; 281 regulator-max-microvolt = <3300000>; 282 regulator-always-on; 283 }; 284 285 /* 3v3 Ethernet */ 286 vgen6_reg: vgen6 { 287 regulator-min-microvolt = <1800000>; 288 regulator-max-microvolt = <3300000>; 289 regulator-always-on; 290 }; 291 }; 292 }; 293}; 294 295&ipu1_di0_disp0 { 296 remote-endpoint = <&lcd_display_in>; 297}; 298 299&pwm3 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_pwm3>; 302 status = "okay"; 303}; 304 305&uart3 { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_uart3>; 308 status = "okay"; 309}; 310 311&usbh1 { 312 vbus-supply = <®_usb_host>; 313 status = "okay"; 314}; 315 316&usbotg { 317 dr_mode = "peripheral"; 318 status = "okay"; 319}; 320 321&usdhc1 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_usdhc1>; 324 bus-width = <4>; 325 vmmc-supply = <®_wl18xx_vmmc>; 326 no-1-8-v; 327 non-removable; 328 wakeup-source; 329 keep-power-in-suspend; 330 cap-power-off-card; 331 max-frequency = <25000000>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 status = "okay"; 335 336 wlcore: wlcore@2 { 337 compatible = "ti,wl1837"; 338 reg = <2>; 339 interrupt-parent = <&gpio6>; 340 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 341 tcxo-clock-frequency = <26000000>; 342 }; 343}; 344 345&usdhc3 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_usdhc3>; 348 bus-width = <8>; 349 non-removable; 350 keep-power-in-suspend; 351 status = "okay"; 352}; 353 354&iomuxc { 355 pinctrl_enet: enetgrp { 356 fsl,pins = < 357 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 358 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 359 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 360 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 361 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 362 MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 363 MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 364 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 365 MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 366 MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 367 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 368 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 369 MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 370 MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 371 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 372 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 373 MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 374 MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 375 >; 376 }; 377 378 pinctrl_i2c3: i2c3grp { 379 fsl,pins = < 380 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 381 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 382 >; 383 }; 384 385 pinctrl_i2c4: i2c4grp { 386 fsl,pins = < 387 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 388 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 389 >; 390 }; 391 392 pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ 393 fsl,pins = < 394 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ 395 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 396 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ 397 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ 398 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ 399 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 400 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 401 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 402 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 403 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 404 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 405 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 406 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 407 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 408 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 409 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 410 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 411 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 412 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 413 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 414 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 415 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 416 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 417 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 418 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 419 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 420 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 421 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 422 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 423 >; 424 }; 425 426 pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { 427 fsl,pins = < 428 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ 429 MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ 430 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ 431 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ 432 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ 433 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ 434 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ 435 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ 436 >; 437 }; 438 439 pinctrl_pwm3: pwm3grp { 440 fsl,pins = < 441 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 442 >; 443 }; 444 445 pinctrl_uart3: uart3grp { 446 fsl,pins = < 447 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 448 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 449 >; 450 }; 451 452 pinctrl_usbhost: usbhostgrp { 453 fsl,pins = < 454 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 455 >; 456 }; 457 458 pinctrl_usdhc1: usdhc1grp { 459 fsl,pins = < 460 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 461 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 462 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 463 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 464 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 465 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 466 >; 467 }; 468 469 pinctrl_usdhc3: usdhc3grp { 470 fsl,pins = < 471 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 472 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 473 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 474 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 475 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 476 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 477 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 478 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 479 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 480 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 481 >; 482 }; 483 484 pinctrl_wlan: wlangrp { 485 fsl,pins = < 486 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 487 >; 488 }; 489}; 490
