1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
4// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	/*
10	 * The decompressor and also some bootloaders rely on a
11	 * pre-existing /chosen node to be available to insert the
12	 * command line and merge other ATAGS info.
13	 * Also for U-Boot there must be a pre-existing /memory node.
14	 */
15	chosen {};
16	memory { device_type = "memory"; };
17
18	aliases {
19		gpio0 = &gpio1;
20		gpio1 = &gpio2;
21		gpio2 = &gpio3;
22		i2c0 = &i2c1;
23		i2c1 = &i2c2;
24		i2c2 = &i2c3;
25		serial0 = &uart1;
26		serial1 = &uart2;
27		serial2 = &uart3;
28		serial3 = &uart4;
29		serial4 = &uart5;
30		spi0 = &spi1;
31		spi1 = &spi2;
32		spi2 = &spi3;
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		cpu@0 {
40			compatible = "arm,arm1136jf-s";
41			device_type = "cpu";
42			reg = <0>;
43		};
44	};
45
46	avic: interrupt-controller@68000000 {
47		compatible = "fsl,imx31-avic", "fsl,avic";
48		interrupt-controller;
49		#interrupt-cells = <1>;
50		reg = <0x68000000 0x100000>;
51	};
52
53	soc {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		compatible = "simple-bus";
57		interrupt-parent = <&avic>;
58		ranges;
59
60		iram: iram@1fffc000 {
61			compatible = "mmio-sram";
62			reg = <0x1fffc000 0x4000>;
63			#address-cells = <1>;
64			#size-cells = <1>;
65			ranges = <0 0x1fffc000 0x4000>;
66		};
67
68		aips@43f00000 { /* AIPS1 */
69			compatible = "fsl,aips-bus", "simple-bus";
70			#address-cells = <1>;
71			#size-cells = <1>;
72			reg = <0x43f00000 0x100000>;
73			ranges;
74
75			i2c1: i2c@43f80000 {
76				compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
77				reg = <0x43f80000 0x4000>;
78				interrupts = <10>;
79				clocks = <&clks 33>;
80				#address-cells = <1>;
81				#size-cells = <0>;
82				status = "disabled";
83			};
84
85			i2c3: i2c@43f84000 {
86				compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
87				reg = <0x43f84000 0x4000>;
88				interrupts = <3>;
89				clocks = <&clks 35>;
90				#address-cells = <1>;
91				#size-cells = <0>;
92				status = "disabled";
93			};
94
95			ata: ata@43f8c000 {
96				compatible = "fsl,imx31-pata", "fsl,imx27-pata";
97				reg = <0x43f8c000 0x4000>;
98				interrupts = <15>;
99				clocks = <&clks 26>;
100				status = "disabled";
101			};
102
103			uart1: serial@43f90000 {
104				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
105				reg = <0x43f90000 0x4000>;
106				interrupts = <45>;
107				clocks = <&clks 10>, <&clks 30>;
108				clock-names = "ipg", "per";
109				status = "disabled";
110			};
111
112			uart2: serial@43f94000 {
113				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
114				reg = <0x43f94000 0x4000>;
115				interrupts = <32>;
116				clocks = <&clks 10>, <&clks 31>;
117				clock-names = "ipg", "per";
118				status = "disabled";
119			};
120
121			i2c2: i2c@43f98000 {
122				compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
123				reg = <0x43f98000 0x4000>;
124				interrupts = <4>;
125				clocks = <&clks 34>;
126				#address-cells = <1>;
127				#size-cells = <0>;
128				status = "disabled";
129			};
130
131			spi1: spi@43fa4000 {
132				compatible = "fsl,imx31-cspi";
133				reg = <0x43fa4000 0x4000>;
134				interrupts = <14>;
135				clocks = <&clks 10>, <&clks 53>;
136				clock-names = "ipg", "per";
137				dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
138				dma-names = "rx", "tx";
139				#address-cells = <1>;
140				#size-cells = <0>;
141				status = "disabled";
142			};
143
144			kpp: kpp@43fa8000 {
145				compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
146				reg = <0x43fa8000 0x4000>;
147				interrupts = <24>;
148				clocks = <&clks 46>;
149				status = "disabled";
150			};
151
152			uart4: serial@43fb0000 {
153				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
154				reg = <0x43fb0000 0x4000>;
155				clocks = <&clks 10>, <&clks 49>;
156				clock-names = "ipg", "per";
157				interrupts = <46>;
158				status = "disabled";
159			};
160
161			uart5: serial@43fb4000 {
162				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
163				reg = <0x43fb4000 0x4000>;
164				interrupts = <47>;
165				clocks = <&clks 10>, <&clks 50>;
166				clock-names = "ipg", "per";
167				status = "disabled";
168			};
169		};
170
171		spba@50000000 {
172			compatible = "fsl,spba-bus", "simple-bus";
173			#address-cells = <1>;
174			#size-cells = <1>;
175			reg = <0x50000000 0x100000>;
176			ranges;
177
178			sdhci1: sdhci@50004000 {
179				compatible = "fsl,imx31-mmc";
180				reg = <0x50004000 0x4000>;
181				interrupts = <9>;
182				clocks = <&clks 10>, <&clks 20>;
183				clock-names = "ipg", "per";
184				dmas = <&sdma 20 3 0>;
185				dma-names = "rx-tx";
186				status = "disabled";
187			};
188
189			sdhci2: sdhci@50008000 {
190				compatible = "fsl,imx31-mmc";
191				reg = <0x50008000 0x4000>;
192				interrupts = <8>;
193				clocks = <&clks 10>, <&clks 21>;
194				clock-names = "ipg", "per";
195				dmas = <&sdma 21 3 0>;
196				dma-names = "rx-tx";
197				status = "disabled";
198			};
199
200			uart3: serial@5000c000 {
201				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
202				reg = <0x5000c000 0x4000>;
203				interrupts = <18>;
204				clocks = <&clks 10>, <&clks 48>;
205				clock-names = "ipg", "per";
206				status = "disabled";
207			};
208
209			spi2: cspi@50010000 {
210				compatible = "fsl,imx31-cspi";
211				reg = <0x50010000 0x4000>;
212				interrupts = <13>;
213				clocks = <&clks 10>, <&clks 54>;
214				clock-names = "ipg", "per";
215				dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
216				dma-names = "rx", "tx";
217				#address-cells = <1>;
218				#size-cells = <0>;
219				status = "disabled";
220			};
221
222			iim: iim@5001c000 {
223				compatible = "fsl,imx31-iim", "fsl,imx27-iim";
224				reg = <0x5001c000 0x1000>;
225				interrupts = <19>;
226				clocks = <&clks 25>;
227			};
228		};
229
230		aips@53f00000 { /* AIPS2 */
231			compatible = "fsl,aips-bus", "simple-bus";
232			#address-cells = <1>;
233			#size-cells = <1>;
234			reg = <0x53f00000 0x100000>;
235			ranges;
236
237			clks: ccm@53f80000{
238				compatible = "fsl,imx31-ccm";
239				reg = <0x53f80000 0x4000>;
240				interrupts = <31>, <53>;
241				#clock-cells = <1>;
242			};
243
244			spi3: cspi@53f84000 {
245				compatible = "fsl,imx31-cspi";
246				reg = <0x53f84000 0x4000>;
247				interrupts = <17>;
248				clocks = <&clks 10>, <&clks 28>;
249				clock-names = "ipg", "per";
250				dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
251				dma-names = "rx", "tx";
252				#address-cells = <1>;
253				#size-cells = <0>;
254				status = "disabled";
255			};
256
257			gpt: timer@53f90000 {
258				compatible = "fsl,imx31-gpt";
259				reg = <0x53f90000 0x4000>;
260				interrupts = <29>;
261				clocks = <&clks 10>, <&clks 22>;
262				clock-names = "ipg", "per";
263			};
264
265			gpio3: gpio@53fa4000 {
266				compatible = "fsl,imx31-gpio";
267				reg = <0x53fa4000 0x4000>;
268				interrupts = <56>;
269				gpio-controller;
270				#gpio-cells = <2>;
271				interrupt-controller;
272				#interrupt-cells = <2>;
273			};
274
275			rng@53fb0000 {
276				compatible = "fsl,imx31-rnga";
277				reg = <0x53fb0000 0x4000>;
278				interrupts = <22>;
279				clocks = <&clks 29>;
280			};
281
282			gpio1: gpio@53fcc000 {
283				compatible = "fsl,imx31-gpio";
284				reg = <0x53fcc000 0x4000>;
285				interrupts = <52>;
286				gpio-controller;
287				#gpio-cells = <2>;
288				interrupt-controller;
289				#interrupt-cells = <2>;
290			};
291
292			gpio2: gpio@53fd0000 {
293				compatible = "fsl,imx31-gpio";
294				reg = <0x53fd0000 0x4000>;
295				interrupts = <51>;
296				gpio-controller;
297				#gpio-cells = <2>;
298				interrupt-controller;
299				#interrupt-cells = <2>;
300			};
301
302			sdma: sdma@53fd4000 {
303				compatible = "fsl,imx31-sdma";
304				reg = <0x53fd4000 0x4000>;
305				interrupts = <34>;
306				clocks = <&clks 10>, <&clks 27>;
307				clock-names = "ipg", "ahb";
308				#dma-cells = <3>;
309				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
310			};
311
312			rtc: rtc@53fd8000 {
313				compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
314				reg = <0x53fd8000 0x4000>;
315				interrupts = <25>;
316				clocks = <&clks 2>, <&clks 40>;
317				clock-names = "ref", "ipg";
318			};
319
320			wdog: wdog@53fdc000 {
321				compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
322				reg = <0x53fdc000 0x4000>;
323				clocks = <&clks 41>;
324			};
325
326			pwm: pwm@53fe0000 {
327				compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
328				reg = <0x53fe0000 0x4000>;
329				interrupts = <26>;
330				clocks = <&clks 10>, <&clks 42>;
331				clock-names = "ipg", "per";
332				#pwm-cells = <2>;
333				status = "disabled";
334			};
335		};
336
337		emi@b8000000 { /* External Memory Interface */
338			compatible = "simple-bus";
339			reg = <0xb8000000 0x5000>;
340			ranges;
341			#address-cells = <1>;
342			#size-cells = <1>;
343
344			nfc: nand@b8000000 {
345				compatible = "fsl,imx31-nand", "fsl,imx27-nand";
346				reg = <0xb8000000 0x1000>;
347				interrupts = <33>;
348				clocks = <&clks 9>;
349				dmas = <&sdma 30 17 0>;
350				dma-names = "rx-tx";
351				#address-cells = <1>;
352				#size-cells = <1>;
353				status = "disabled";
354			};
355
356			weim: weim@b8002000 {
357				compatible = "fsl,imx31-weim", "fsl,imx27-weim";
358				reg = <0xb8002000 0x1000>;
359				clocks = <&clks 56>;
360				#address-cells = <2>;
361				#size-cells = <1>;
362				ranges = <0 0 0xa0000000 0x08000000
363					  1 0 0xa8000000 0x08000000
364					  2 0 0xb0000000 0x02000000
365					  3 0 0xb2000000 0x02000000
366					  4 0 0xb4000000 0x02000000
367					  5 0 0xb6000000 0x02000000>;
368				status = "disabled";
369			};
370		};
371	};
372};
373