1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16	model = "Freescale MX1 ADS";
17	compatible = "fsl,imx1ads", "fsl,imx1";
18
19	chosen {
20		stdout-path = &uart1;
21	};
22
23	memory@8000000 {
24		reg = <0x08000000 0x04000000>;
25	};
26};
27
28&cspi1 {
29	pinctrl-0 = <&pinctrl_cspi1>;
30	cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
31	status = "okay";
32};
33
34&i2c {
35	pinctrl-names = "default";
36	pinctrl-0 = <&pinctrl_i2c>;
37	status = "okay";
38
39	extgpio0: pcf8575@22 {
40		compatible = "nxp,pcf8575";
41		reg = <0x22>;
42		gpio-controller;
43		#gpio-cells = <2>;
44	};
45
46	extgpio1: pcf8575@24 {
47		compatible = "nxp,pcf8575";
48		reg = <0x24>;
49		gpio-controller;
50		#gpio-cells = <2>;
51	};
52};
53
54&uart1 {
55	pinctrl-names = "default";
56	pinctrl-0 = <&pinctrl_uart1>;
57	uart-has-rtscts;
58	status = "okay";
59};
60
61&uart2 {
62	pinctrl-names = "default";
63	pinctrl-0 = <&pinctrl_uart2>;
64	uart-has-rtscts;
65	status = "okay";
66};
67
68&weim {
69	pinctrl-names = "default";
70	pinctrl-0 = <&pinctrl_weim>;
71	status = "okay";
72
73	nor: nor@0,0 {
74		compatible = "cfi-flash";
75		reg = <0 0x00000000 0x02000000>;
76		bank-width = <4>;
77		fsl,weim-cs-timing = <0x00003e00 0x00000801>;
78		#address-cells = <1>;
79		#size-cells = <1>;
80	};
81};
82
83&iomuxc {
84	imx1-ads {
85		pinctrl_cspi1: cspi1grp {
86			fsl,pins = <
87				MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
88				MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
89				MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
90				MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
91				MX1_PAD_SPI1_SS__GPIO3_15	0x0
92			>;
93		};
94
95		pinctrl_i2c: i2cgrp {
96			fsl,pins = <
97				MX1_PAD_I2C_SCL__I2C_SCL	0x0
98				MX1_PAD_I2C_SDA__I2C_SDA	0x0
99			>;
100		};
101
102		pinctrl_uart1: uart1grp {
103			fsl,pins = <
104				MX1_PAD_UART1_TXD__UART1_TXD	0x0
105				MX1_PAD_UART1_RXD__UART1_RXD	0x0
106				MX1_PAD_UART1_CTS__UART1_CTS	0x0
107				MX1_PAD_UART1_RTS__UART1_RTS	0x0
108			>;
109		};
110
111		pinctrl_uart2: uart2grp {
112			fsl,pins = <
113				MX1_PAD_UART2_TXD__UART2_TXD	0x0
114				MX1_PAD_UART2_RXD__UART2_RXD	0x0
115				MX1_PAD_UART2_CTS__UART2_CTS	0x0
116				MX1_PAD_UART2_RTS__UART2_RTS	0x0
117			>;
118		};
119
120		pinctrl_weim: weimgrp {
121			fsl,pins = <
122				MX1_PAD_A0__A0			0x0
123				MX1_PAD_A16__A16		0x0
124				MX1_PAD_A17__A17		0x0
125				MX1_PAD_A18__A18		0x0
126				MX1_PAD_A19__A19		0x0
127				MX1_PAD_A20__A20		0x0
128				MX1_PAD_A21__A21		0x0
129				MX1_PAD_A22__A22		0x0
130				MX1_PAD_A23__A23		0x0
131				MX1_PAD_A24__A24		0x0
132				MX1_PAD_BCLK__BCLK		0x0
133				MX1_PAD_CS4__CS4		0x0
134				MX1_PAD_DTACK__DTACK		0x0
135				MX1_PAD_ECB__ECB		0x0
136				MX1_PAD_LBA__LBA		0x0
137			>;
138		};
139	};
140};
141