1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree file for Cortina systems Gemini SoC
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/clock/cortina,gemini-clock.h>
8#include <dt-bindings/reset/cortina,gemini-reset.h>
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12	soc {
13		#address-cells = <1>;
14		#size-cells = <1>;
15		ranges;
16		compatible = "simple-bus";
17		interrupt-parent = <&intcon>;
18
19		flash@30000000 {
20			compatible = "cortina,gemini-flash", "cfi-flash";
21			syscon = <&syscon>;
22			pinctrl-names = "default";
23			pinctrl-0 = <&pflash_default_pins>;
24			bank-width = <2>;
25			#address-cells = <1>;
26			#size-cells = <1>;
27			status = "disabled";
28		};
29
30		syscon: syscon@40000000 {
31			compatible = "cortina,gemini-syscon",
32				     "syscon", "simple-mfd";
33			reg = <0x40000000 0x1000>;
34			#clock-cells = <1>;
35			#reset-cells = <1>;
36
37			syscon-reboot {
38				compatible = "syscon-reboot";
39				regmap = <&syscon>;
40				/* GLOBAL_RESET register */
41				offset = <0x0c>;
42				/* RESET_GLOBAL | RESET_CPU1 */
43				mask = <0xC0000000>;
44			};
45
46			pinctrl {
47				compatible = "cortina,gemini-pinctrl";
48				regmap = <&syscon>;
49				/* Hog the DRAM pins */
50				pinctrl-names = "default";
51				pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
52					    <&vcontrol_default_pins>;
53
54				dram_default_pins: pinctrl-dram {
55					mux {
56						function = "dram";
57						groups = "dramgrp";
58					};
59				};
60				rtc_default_pins: pinctrl-rtc {
61					mux {
62						function = "rtc";
63						groups = "rtcgrp";
64					};
65				};
66				power_default_pins: pinctrl-power {
67					mux {
68						function = "power";
69						groups = "powergrp";
70					};
71				};
72				cir_default_pins: pinctrl-cir {
73					mux {
74						function = "cir";
75						groups = "cirgrp";
76					};
77				};
78				system_default_pins: pinctrl-system {
79					mux {
80						function = "system";
81						groups = "systemgrp";
82					};
83				};
84				vcontrol_default_pins: pinctrl-vcontrol {
85					mux {
86						function = "vcontrol";
87						groups = "vcontrolgrp";
88					};
89				};
90				ice_default_pins: pinctrl-ice {
91					mux {
92						function = "ice";
93						groups = "icegrp";
94					};
95				};
96				uart_default_pins: pinctrl-uart {
97					mux {
98						function = "uart";
99						groups = "uartrxtxgrp";
100					};
101				};
102				pflash_default_pins: pinctrl-pflash {
103					mux {
104						function = "pflash";
105						groups = "pflashgrp";
106					};
107				};
108				usb_default_pins: pinctrl-usb {
109					mux {
110						function = "usb";
111						groups = "usbgrp";
112					};
113				};
114				gmii_default_pins: pinctrl-gmii {
115					/*
116					 * Only activate GMAC0 by default since
117					 * GMAC1 will overlap with 8 GPIO lines
118					 * gpio2a, gpio2b. Overlay groups with
119					 * "gmii_gmac0_grp", "gmii_gmac1_grp" for
120					 * both ethernet interfaces.
121					 */
122					mux {
123						function = "gmii";
124						groups = "gmii_gmac0_grp";
125					};
126				};
127				pci_default_pins: pinctrl-pci {
128					mux {
129						function = "pci";
130						groups = "pcigrp";
131					};
132				};
133				sata_default_pins: pinctrl-sata {
134					mux {
135						function = "sata";
136						groups = "satagrp";
137					};
138				};
139				/* Activate both groups of pins for this state */
140				sata_and_ide_pins: pinctrl-sata-ide {
141					mux0 {
142						function = "sata";
143						groups = "satagrp";
144					};
145					mux1 {
146						function = "ide";
147						groups = "idegrp";
148					};
149				};
150				tvc_default_pins: pinctrl-tvc {
151					mux {
152						function = "tvc";
153						groups = "tvcgrp";
154					};
155				};
156			};
157		};
158
159		watchdog@41000000 {
160			compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
161			reg = <0x41000000 0x1000>;
162			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
163			resets = <&syscon GEMINI_RESET_WDOG>;
164			clocks = <&syscon GEMINI_CLK_APB>;
165			clock-names = "PCLK";
166		};
167
168		uart0: serial@42000000 {
169			compatible = "ns16550a";
170			reg = <0x42000000 0x100>;
171			resets = <&syscon GEMINI_RESET_UART>;
172			clocks = <&syscon GEMINI_CLK_UART>;
173			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
174			pinctrl-names = "default";
175			pinctrl-0 = <&uart_default_pins>;
176			reg-shift = <2>;
177		};
178
179		timer@43000000 {
180			compatible = "faraday,fttmr010";
181			reg = <0x43000000 0x1000>;
182			interrupt-parent = <&intcon>;
183			interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
184				     <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
185				     <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
186			resets = <&syscon GEMINI_RESET_TIMER>;
187			/* APB clock or RTC clock */
188			clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
189			clock-names = "PCLK", "EXTCLK";
190			syscon = <&syscon>;
191		};
192
193		rtc@45000000 {
194			compatible = "cortina,gemini-rtc";
195			reg = <0x45000000 0x100>;
196			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
197			resets = <&syscon GEMINI_RESET_RTC>;
198			clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
199			clock-names = "PCLK", "EXTCLK";
200			pinctrl-names = "default";
201			pinctrl-0 = <&rtc_default_pins>;
202		};
203
204		sata: sata@46000000 {
205			compatible = "cortina,gemini-sata-bridge";
206			reg = <0x46000000 0x100>;
207			resets = <&syscon GEMINI_RESET_SATA0>,
208				 <&syscon GEMINI_RESET_SATA1>;
209			reset-names = "sata0", "sata1";
210			clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
211				 <&syscon GEMINI_CLK_GATE_SATA1>;
212			clock-names = "SATA0_PCLK", "SATA1_PCLK";
213			/*
214			 * This defines the special "ide" state that needs
215			 * to be explicitly enabled to enable the IDE pins,
216			 * as these pins are normally used for other things.
217			 */
218			pinctrl-names = "default", "ide";
219			pinctrl-0 = <&sata_default_pins>;
220			pinctrl-1 = <&sata_and_ide_pins>;
221			syscon = <&syscon>;
222			status = "disabled";
223		};
224
225		intcon: interrupt-controller@48000000 {
226			compatible = "faraday,ftintc010";
227			reg = <0x48000000 0x1000>;
228			resets = <&syscon GEMINI_RESET_INTCON0>;
229			interrupt-controller;
230			#interrupt-cells = <2>;
231		};
232
233		power-controller@4b000000 {
234			compatible = "cortina,gemini-power-controller";
235			reg = <0x4b000000 0x100>;
236			interrupts = <26 IRQ_TYPE_EDGE_RISING>;
237			pinctrl-names = "default";
238			pinctrl-0 = <&power_default_pins>;
239		};
240
241		gpio0: gpio@4d000000 {
242			compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
243			reg = <0x4d000000 0x100>;
244			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
245			resets = <&syscon GEMINI_RESET_GPIO0>;
246			clocks = <&syscon GEMINI_CLK_APB>;
247			gpio-controller;
248			#gpio-cells = <2>;
249			interrupt-controller;
250			#interrupt-cells = <2>;
251		};
252
253		gpio1: gpio@4e000000 {
254			compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
255			reg = <0x4e000000 0x100>;
256			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
257			resets = <&syscon GEMINI_RESET_GPIO1>;
258			clocks = <&syscon GEMINI_CLK_APB>;
259			gpio-controller;
260			#gpio-cells = <2>;
261			interrupt-controller;
262			#interrupt-cells = <2>;
263		};
264
265		gpio2: gpio@4f000000 {
266			compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
267			reg = <0x4f000000 0x100>;
268			interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
269			resets = <&syscon GEMINI_RESET_GPIO2>;
270			clocks = <&syscon GEMINI_CLK_APB>;
271			gpio-controller;
272			#gpio-cells = <2>;
273			interrupt-controller;
274			#interrupt-cells = <2>;
275		};
276
277		pci@50000000 {
278			compatible = "cortina,gemini-pci", "faraday,ftpci100";
279			/*
280			 * The first 256 bytes in the IO range is actually used
281			 * to configure the host bridge.
282			 */
283			reg = <0x50000000 0x100>;
284			resets = <&syscon GEMINI_RESET_PCI>;
285			clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
286			clock-names = "PCLK", "PCICLK";
287			pinctrl-names = "default";
288			pinctrl-0 = <&pci_default_pins>;
289			#address-cells = <3>;
290			#size-cells = <2>;
291			#interrupt-cells = <1>;
292			status = "disabled";
293
294			bus-range = <0x00 0xff>;
295			/* PCI ranges mappings */
296			ranges =
297			/* 1MiB I/O space 0x50000000-0x500fffff */
298			<0x01000000 0 0          0x50000000 0 0x00100000>,
299			/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
300			<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
301
302			/* DMA ranges */
303			dma-ranges =
304			/* 128MiB at 0x00000000-0x07ffffff */
305			<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
306			/* 64MiB at 0x00000000-0x03ffffff */
307			<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
308			/* 64MiB at 0x00000000-0x03ffffff */
309			<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
310
311			/*
312			 * This PCI host bridge variant has a cascaded interrupt
313			 * controller embedded in the host bridge.
314			 */
315			pci_intc: interrupt-controller {
316				interrupt-parent = <&intcon>;
317				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
318				interrupt-controller;
319				#address-cells = <0>;
320				#interrupt-cells = <1>;
321			};
322		};
323
324		ethernet@60000000 {
325			compatible = "cortina,gemini-ethernet";
326			reg = <0x60000000 0x4000>, /* Global registers, queue */
327			      <0x60004000 0x2000>, /* V-bit */
328			      <0x60006000 0x2000>; /* A-bit */
329			pinctrl-names = "default";
330			pinctrl-0 = <&gmii_default_pins>;
331			status = "disabled";
332			#address-cells = <1>;
333			#size-cells = <1>;
334			ranges;
335
336			gmac0: ethernet-port@0 {
337				compatible = "cortina,gemini-ethernet-port";
338				reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
339				      <0x6000a000 0x2000>; /* Port 0 GMAC */
340				interrupt-parent = <&intcon>;
341				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
342				resets = <&syscon GEMINI_RESET_GMAC0>;
343				clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
344				clock-names = "PCLK";
345			};
346
347			gmac1: ethernet-port@1 {
348				compatible = "cortina,gemini-ethernet-port";
349				reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
350				      <0x6000e000 0x2000>; /* Port 1 GMAC */
351				interrupt-parent = <&intcon>;
352				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
353				resets = <&syscon GEMINI_RESET_GMAC1>;
354				clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
355				clock-names = "PCLK";
356			};
357		};
358
359		ata@63000000 {
360			compatible = "cortina,gemini-pata", "faraday,ftide010";
361			reg = <0x63000000 0x1000>;
362			interrupts = <4 IRQ_TYPE_EDGE_RISING>;
363			resets = <&syscon GEMINI_RESET_IDE>;
364			clocks = <&syscon GEMINI_CLK_GATE_IDE>;
365			clock-names = "PCLK";
366			sata = <&sata>;
367			status = "disabled";
368		};
369
370		ata@63400000 {
371			compatible = "cortina,gemini-pata", "faraday,ftide010";
372			reg = <0x63400000 0x1000>;
373			interrupts = <5 IRQ_TYPE_EDGE_RISING>;
374			resets = <&syscon GEMINI_RESET_IDE>;
375			clocks = <&syscon GEMINI_CLK_GATE_IDE>;
376			clock-names = "PCLK";
377			sata = <&sata>;
378			status = "disabled";
379		};
380
381		dma-controller@67000000 {
382			compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
383			/* Faraday Technology FTDMAC020 variant */
384			arm,primecell-periphid = <0x0003b080>;
385			reg = <0x67000000 0x1000>;
386			interrupts = <9 IRQ_TYPE_EDGE_RISING>;
387			resets = <&syscon GEMINI_RESET_DMAC>;
388			clocks = <&syscon GEMINI_CLK_AHB>;
389			clock-names = "apb_pclk";
390			/* Bus interface AHB1 (AHB0) is totally tilted */
391			lli-bus-interface-ahb2;
392			mem-bus-interface-ahb2;
393			memcpy-burst-size = <256>;
394			memcpy-bus-width = <32>;
395			#dma-cells = <2>;
396		};
397
398		display-controller@6a000000 {
399			compatible = "cortina,gemini-tvc", "faraday,tve200";
400			reg = <0x6a000000 0x1000>;
401			interrupts = <13 IRQ_TYPE_EDGE_RISING>;
402			resets = <&syscon GEMINI_RESET_TVC>;
403			clocks = <&syscon GEMINI_CLK_GATE_TVC>,
404				 <&syscon GEMINI_CLK_TVC>;
405			clock-names = "PCLK", "TVE";
406			pinctrl-names = "default";
407			pinctrl-0 = <&tvc_default_pins>;
408			#address-cells = <1>;
409			#size-cells = <0>;
410			status = "disabled";
411		};
412	};
413};
414