1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35#include <dt-bindings/clock/bcm-nsp.h> 36 37#include "skeleton.dtsi" 38 39/ { 40 compatible = "brcm,nsp"; 41 model = "Broadcom Northstar Plus SoC"; 42 interrupt-parent = <&gic>; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a9"; 51 next-level-cache = <&L2>; 52 reg = <0x0>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a9"; 58 next-level-cache = <&L2>; 59 enable-method = "brcm,bcm-nsp-smp"; 60 secondary-boot-reg = <0xffff0fec>; 61 reg = <0x1>; 62 }; 63 }; 64 65 pmu { 66 compatible = "arm,cortex-a9-pmu"; 67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>; 70 }; 71 72 mpcore { 73 compatible = "simple-bus"; 74 ranges = <0x00000000 0x19000000 0x00023000>; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 78 a9pll: arm_clk@0 { 79 #clock-cells = <0>; 80 compatible = "brcm,nsp-armpll"; 81 clocks = <&osc>; 82 reg = <0x00000 0x1000>; 83 }; 84 85 timer@20200 { 86 compatible = "arm,cortex-a9-global-timer"; 87 reg = <0x20200 0x100>; 88 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 89 clocks = <&periph_clk>; 90 }; 91 92 twd-timer@20600 { 93 compatible = "arm,cortex-a9-twd-timer"; 94 reg = <0x20600 0x20>; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 96 IRQ_TYPE_EDGE_RISING)>; 97 clocks = <&periph_clk>; 98 }; 99 100 twd-watchdog@20620 { 101 compatible = "arm,cortex-a9-twd-wdt"; 102 reg = <0x20620 0x20>; 103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 104 IRQ_TYPE_LEVEL_HIGH)>; 105 clocks = <&periph_clk>; 106 }; 107 108 gic: interrupt-controller@21000 { 109 compatible = "arm,cortex-a9-gic"; 110 #interrupt-cells = <3>; 111 #address-cells = <0>; 112 interrupt-controller; 113 reg = <0x21000 0x1000>, 114 <0x20100 0x100>; 115 }; 116 117 L2: l2-cache { 118 compatible = "arm,pl310-cache"; 119 reg = <0x22000 0x1000>; 120 cache-unified; 121 cache-level = <2>; 122 }; 123 }; 124 125 clocks { 126 #address-cells = <1>; 127 #size-cells = <1>; 128 ranges; 129 130 osc: oscillator { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 clock-frequency = <25000000>; 134 }; 135 136 iprocmed: iprocmed { 137 #clock-cells = <0>; 138 compatible = "fixed-factor-clock"; 139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 140 clock-div = <2>; 141 clock-mult = <1>; 142 }; 143 144 iprocslow: iprocslow { 145 #clock-cells = <0>; 146 compatible = "fixed-factor-clock"; 147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 148 clock-div = <4>; 149 clock-mult = <1>; 150 }; 151 152 periph_clk: periph_clk { 153 #clock-cells = <0>; 154 compatible = "fixed-factor-clock"; 155 clocks = <&a9pll>; 156 clock-div = <2>; 157 clock-mult = <1>; 158 }; 159 }; 160 161 axi { 162 compatible = "simple-bus"; 163 ranges = <0x00000000 0x18000000 0x0011c40c>; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 gpioa: gpio@20 { 168 compatible = "brcm,nsp-gpio-a"; 169 reg = <0x0020 0x70>, 170 <0x3f1c4 0x1c>; 171 #gpio-cells = <2>; 172 gpio-controller; 173 ngpios = <32>; 174 interrupt-controller; 175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 176 gpio-ranges = <&pinctrl 0 0 32>; 177 }; 178 179 uart0: serial@300 { 180 compatible = "ns16550a"; 181 reg = <0x0300 0x100>; 182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&osc>; 184 status = "disabled"; 185 }; 186 187 uart1: serial@400 { 188 compatible = "ns16550a"; 189 reg = <0x0400 0x100>; 190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&osc>; 192 status = "disabled"; 193 }; 194 195 dma@20000 { 196 compatible = "arm,pl330", "arm,primecell"; 197 reg = <0x20000 0x1000>; 198 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&iprocslow>; 208 clock-names = "apb_pclk"; 209 #dma-cells = <1>; 210 }; 211 212 sdio: sdhci@21000 { 213 compatible = "brcm,sdhci-iproc-cygnus"; 214 reg = <0x21000 0x100>; 215 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 216 sdhci,auto-cmd12; 217 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; 218 dma-coherent; 219 status = "disabled"; 220 }; 221 222 amac0: ethernet@22000 { 223 compatible = "brcm,nsp-amac"; 224 reg = <0x022000 0x1000>, 225 <0x110000 0x1000>; 226 reg-names = "amac_base", "idm_base"; 227 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 228 dma-coherent; 229 status = "disabled"; 230 }; 231 232 amac1: ethernet@23000 { 233 compatible = "brcm,nsp-amac"; 234 reg = <0x023000 0x1000>, 235 <0x111000 0x1000>; 236 reg-names = "amac_base", "idm_base"; 237 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 238 dma-coherent; 239 status = "disabled"; 240 }; 241 242 amac2: ethernet@24000 { 243 compatible = "brcm,nsp-amac"; 244 reg = <0x024000 0x1000>, 245 <0x112000 0x1000>; 246 reg-names = "amac_base", "idm_base"; 247 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 248 dma-coherent; 249 status = "disabled"; 250 }; 251 252 mailbox: mailbox@25000 { 253 compatible = "brcm,iproc-fa2-mbox"; 254 reg = <0x25000 0x445>; 255 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 256 #mbox-cells = <1>; 257 brcm,rx-status-len = <32>; 258 brcm,use-bcm-hdr; 259 dma-coherent; 260 }; 261 262 nand: nand@26000 { 263 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 264 reg = <0x026000 0x600>, 265 <0x11b408 0x600>, 266 <0x026f00 0x20>; 267 reg-names = "nand", "iproc-idm", "iproc-ext"; 268 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 269 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 brcm,nand-has-wp; 274 }; 275 276 qspi: qspi@27200 { 277 compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; 278 reg = <0x027200 0x184>, 279 <0x027000 0x124>, 280 <0x11c408 0x004>, 281 <0x0273a0 0x01c>; 282 reg-names = "mspi", "bspi", "intr_regs", 283 "intr_status_reg"; 284 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-names = "spi_lr_fullness_reached", 292 "spi_lr_session_aborted", 293 "spi_lr_impatient", 294 "spi_lr_session_done", 295 "spi_lr_overhead", 296 "mspi_done", 297 "mspi_halted"; 298 clocks = <&iprocmed>; 299 clock-names = "iprocmed"; 300 num-cs = <2>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 }; 304 305 xhci: usb@29000 { 306 compatible = "generic-xhci"; 307 reg = <0x29000 0x1000>; 308 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 309 phys = <&usb3_phy>; 310 phy-names = "usb3-phy"; 311 dma-coherent; 312 status = "disabled"; 313 }; 314 315 ehci0: usb@2a000 { 316 compatible = "generic-ehci"; 317 reg = <0x2a000 0x100>; 318 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 319 dma-coherent; 320 status = "disabled"; 321 }; 322 323 ohci0: usb@2b000 { 324 compatible = "generic-ohci"; 325 reg = <0x2b000 0x100>; 326 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 327 dma-coherent; 328 status = "disabled"; 329 }; 330 331 crypto@2f000 { 332 compatible = "brcm,spum-nsp-crypto"; 333 reg = <0x2f000 0x900>; 334 mboxes = <&mailbox 0>; 335 }; 336 337 gpiob: gpio@30000 { 338 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; 339 reg = <0x30000 0x50>; 340 #gpio-cells = <2>; 341 gpio-controller; 342 ngpios = <4>; 343 interrupt-controller; 344 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 345 }; 346 347 pwm: pwm@31000 { 348 compatible = "brcm,iproc-pwm"; 349 reg = <0x31000 0x28>; 350 clocks = <&osc>; 351 #pwm-cells = <3>; 352 status = "disabled"; 353 }; 354 355 rng: rng@33000 { 356 compatible = "brcm,bcm-nsp-rng"; 357 reg = <0x33000 0x14>; 358 }; 359 360 ccbtimer0: timer@34000 { 361 compatible = "arm,sp804"; 362 reg = <0x34000 0x1000>; 363 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&iprocslow>; 366 clock-names = "apb_pclk"; 367 }; 368 369 ccbtimer1: timer@35000 { 370 compatible = "arm,sp804"; 371 reg = <0x35000 0x1000>; 372 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&iprocslow>; 375 clock-names = "apb_pclk"; 376 }; 377 378 srab: srab@36000 { 379 compatible = "brcm,nsp-srab"; 380 reg = <0x36000 0x1000>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 384 status = "disabled"; 385 386 /* ports are defined in board DTS */ 387 }; 388 389 i2c0: i2c@38000 { 390 compatible = "brcm,iproc-i2c"; 391 reg = <0x38000 0x50>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 395 clock-frequency = <100000>; 396 dma-coherent; 397 status = "disabled"; 398 }; 399 400 watchdog@39000 { 401 compatible = "arm,sp805", "arm,primecell"; 402 reg = <0x39000 0x1000>; 403 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&iprocslow>, <&iprocslow>; 405 clock-names = "wdogclk", "apb_pclk"; 406 }; 407 408 lcpll0: lcpll0@3f100 { 409 #clock-cells = <1>; 410 compatible = "brcm,nsp-lcpll0"; 411 reg = <0x3f100 0x14>; 412 clocks = <&osc>; 413 clock-output-names = "lcpll0", "pcie_phy", "sdio", 414 "ddr_phy"; 415 }; 416 417 genpll: genpll@3f140 { 418 #clock-cells = <1>; 419 compatible = "brcm,nsp-genpll"; 420 reg = <0x3f140 0x24>; 421 clocks = <&osc>; 422 clock-output-names = "genpll", "phy", "ethernetclk", 423 "usbclk", "iprocfast", "sata1", 424 "sata2"; 425 }; 426 427 pinctrl: pinctrl@3f1c0 { 428 compatible = "brcm,nsp-pinmux"; 429 reg = <0x3f1c0 0x04>, 430 <0x30028 0x04>, 431 <0x3f408 0x04>; 432 }; 433 434 thermal: thermal@3f2c0 { 435 compatible = "brcm,ns-thermal"; 436 reg = <0x3f2c0 0x10>; 437 #thermal-sensor-cells = <0>; 438 }; 439 440 sata_phy: sata_phy@40100 { 441 compatible = "brcm,iproc-nsp-sata-phy"; 442 reg = <0x40100 0x340>; 443 reg-names = "phy"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 447 sata_phy0: sata-phy@0 { 448 reg = <0>; 449 #phy-cells = <0>; 450 status = "disabled"; 451 }; 452 453 sata_phy1: sata-phy@1 { 454 reg = <1>; 455 #phy-cells = <0>; 456 status = "disabled"; 457 }; 458 }; 459 460 sata: ahci@41000 { 461 compatible = "brcm,bcm-nsp-ahci"; 462 reg-names = "ahci", "top-ctrl"; 463 reg = <0x41000 0x1000>, <0x40020 0x1c>; 464 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 dma-coherent; 468 status = "disabled"; 469 470 sata0: sata-port@0 { 471 reg = <0>; 472 phys = <&sata_phy0>; 473 phy-names = "sata-phy"; 474 }; 475 476 sata1: sata-port@1 { 477 reg = <1>; 478 phys = <&sata_phy1>; 479 phy-names = "sata-phy"; 480 }; 481 }; 482 483 usb3_phy: usb3-phy@104000 { 484 compatible = "brcm,ns-bx-usb3-phy"; 485 reg = <0x104000 0x1000>, 486 <0x032000 0x1000>; 487 reg-names = "dmp", "ccb-mii"; 488 #phy-cells = <0>; 489 status = "disabled"; 490 }; 491 }; 492 493 pcie0: pcie@18012000 { 494 compatible = "brcm,iproc-pcie"; 495 reg = <0x18012000 0x1000>; 496 497 #interrupt-cells = <1>; 498 interrupt-map-mask = <0 0 0 0>; 499 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 500 501 linux,pci-domain = <0>; 502 503 bus-range = <0x00 0xff>; 504 505 #address-cells = <3>; 506 #size-cells = <2>; 507 device_type = "pci"; 508 509 /* Note: The HW does not support I/O resources. So, 510 * only the memory resource range is being specified. 511 */ 512 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; 513 514 dma-coherent; 515 status = "disabled"; 516 517 msi-parent = <&msi0>; 518 msi0: msi-controller { 519 compatible = "brcm,iproc-msi"; 520 msi-controller; 521 interrupt-parent = <&gic>; 522 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 526 brcm,pcie-msi-inten; 527 }; 528 }; 529 530 pcie1: pcie@18013000 { 531 compatible = "brcm,iproc-pcie"; 532 reg = <0x18013000 0x1000>; 533 534 #interrupt-cells = <1>; 535 interrupt-map-mask = <0 0 0 0>; 536 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 537 538 linux,pci-domain = <1>; 539 540 bus-range = <0x00 0xff>; 541 542 #address-cells = <3>; 543 #size-cells = <2>; 544 device_type = "pci"; 545 546 /* Note: The HW does not support I/O resources. So, 547 * only the memory resource range is being specified. 548 */ 549 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; 550 551 dma-coherent; 552 status = "disabled"; 553 554 msi-parent = <&msi1>; 555 msi1: msi-controller { 556 compatible = "brcm,iproc-msi"; 557 msi-controller; 558 interrupt-parent = <&gic>; 559 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 563 brcm,pcie-msi-inten; 564 }; 565 }; 566 567 pcie2: pcie@18014000 { 568 compatible = "brcm,iproc-pcie"; 569 reg = <0x18014000 0x1000>; 570 571 #interrupt-cells = <1>; 572 interrupt-map-mask = <0 0 0 0>; 573 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 574 575 linux,pci-domain = <2>; 576 577 bus-range = <0x00 0xff>; 578 579 #address-cells = <3>; 580 #size-cells = <2>; 581 device_type = "pci"; 582 583 /* Note: The HW does not support I/O resources. So, 584 * only the memory resource range is being specified. 585 */ 586 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; 587 588 dma-coherent; 589 status = "disabled"; 590 591 msi-parent = <&msi2>; 592 msi2: msi-controller { 593 compatible = "brcm,iproc-msi"; 594 msi-controller; 595 interrupt-parent = <&gic>; 596 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 600 brcm,pcie-msi-inten; 601 }; 602 }; 603 604 thermal-zones { 605 cpu-thermal { 606 polling-delay-passive = <0>; 607 polling-delay = <1000>; 608 coefficients = <(-556) 418000>; 609 thermal-sensors = <&thermal>; 610 611 trips { 612 cpu-crit { 613 temperature = <125000>; 614 hysteresis = <0>; 615 type = "critical"; 616 }; 617 }; 618 619 cooling-maps { 620 }; 621 }; 622 }; 623}; 624
