1/* 2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC 3 * 4 * Copyright (C) 2011 Atmel, 5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, 6 * 2012 Joachim Eastwood <manabian@gmail.com> 7 * 8 * Based on at91sam9260.dtsi 9 * 10 * Licensed under GPLv2 or later. 11 */ 12 13#include "skeleton.dtsi" 14#include <dt-bindings/pinctrl/at91.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/clock/at91.h> 18 19/ { 20 model = "Atmel AT91RM9200 family SoC"; 21 compatible = "atmel,at91rm9200"; 22 interrupt-parent = <&aic>; 23 24 aliases { 25 serial0 = &dbgu; 26 serial1 = &usart0; 27 serial2 = &usart1; 28 serial3 = &usart2; 29 serial4 = &usart3; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 tcb0 = &tcb0; 35 tcb1 = &tcb1; 36 i2c0 = &i2c0; 37 ssc0 = &ssc0; 38 ssc1 = &ssc1; 39 ssc2 = &ssc2; 40 }; 41 cpus { 42 #address-cells = <0>; 43 #size-cells = <0>; 44 45 cpu { 46 compatible = "arm,arm920t"; 47 device_type = "cpu"; 48 }; 49 }; 50 51 memory { 52 reg = <0x20000000 0x04000000>; 53 }; 54 55 clocks { 56 slow_xtal: slow_xtal { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <0>; 60 }; 61 62 main_xtal: main_xtal { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 }; 68 69 sram: sram@200000 { 70 compatible = "mmio-sram"; 71 reg = <0x00200000 0x4000>; 72 }; 73 74 ahb { 75 compatible = "simple-bus"; 76 #address-cells = <1>; 77 #size-cells = <1>; 78 ranges; 79 80 apb { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 aic: interrupt-controller@fffff000 { 87 #interrupt-cells = <3>; 88 compatible = "atmel,at91rm9200-aic"; 89 interrupt-controller; 90 reg = <0xfffff000 0x200>; 91 atmel,external-irqs = <25 26 27 28 29 30 31>; 92 }; 93 94 ramc0: ramc@ffffff00 { 95 compatible = "atmel,at91rm9200-sdramc", "syscon"; 96 reg = <0xffffff00 0x100>; 97 }; 98 99 pmc: pmc@fffffc00 { 100 compatible = "atmel,at91rm9200-pmc", "syscon"; 101 reg = <0xfffffc00 0x100>; 102 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 103 interrupt-controller; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 #interrupt-cells = <1>; 107 108 main_osc: main_osc { 109 compatible = "atmel,at91rm9200-clk-main-osc"; 110 #clock-cells = <0>; 111 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 112 clocks = <&main_xtal>; 113 }; 114 115 main: mainck { 116 compatible = "atmel,at91rm9200-clk-main"; 117 #clock-cells = <0>; 118 clocks = <&main_osc>; 119 }; 120 121 plla: pllack { 122 compatible = "atmel,at91rm9200-clk-pll"; 123 #clock-cells = <0>; 124 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 125 clocks = <&main>; 126 reg = <0>; 127 atmel,clk-input-range = <1000000 32000000>; 128 #atmel,pll-clk-output-range-cells = <3>; 129 atmel,pll-clk-output-ranges = <80000000 160000000 0>, 130 <150000000 180000000 2>; 131 }; 132 133 pllb: pllbck { 134 compatible = "atmel,at91rm9200-clk-pll"; 135 #clock-cells = <0>; 136 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 137 clocks = <&main>; 138 reg = <1>; 139 atmel,clk-input-range = <1000000 32000000>; 140 #atmel,pll-clk-output-range-cells = <3>; 141 atmel,pll-clk-output-ranges = <80000000 160000000 0>, 142 <150000000 180000000 2>; 143 }; 144 145 mck: masterck { 146 compatible = "atmel,at91rm9200-clk-master"; 147 #clock-cells = <0>; 148 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 149 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; 150 atmel,clk-output-range = <0 80000000>; 151 atmel,clk-divisors = <1 2 3 4>; 152 }; 153 154 usb: usbck { 155 compatible = "atmel,at91rm9200-clk-usb"; 156 #clock-cells = <0>; 157 atmel,clk-divisors = <1 2 0 0>; 158 clocks = <&pllb>; 159 }; 160 161 prog: progck { 162 compatible = "atmel,at91rm9200-clk-programmable"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupt-parent = <&pmc>; 166 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; 167 168 prog0: prog0 { 169 #clock-cells = <0>; 170 reg = <0>; 171 interrupts = <AT91_PMC_PCKRDY(0)>; 172 }; 173 174 prog1: prog1 { 175 #clock-cells = <0>; 176 reg = <1>; 177 interrupts = <AT91_PMC_PCKRDY(1)>; 178 }; 179 180 prog2: prog2 { 181 #clock-cells = <0>; 182 reg = <2>; 183 interrupts = <AT91_PMC_PCKRDY(2)>; 184 }; 185 186 prog3: prog3 { 187 #clock-cells = <0>; 188 reg = <3>; 189 interrupts = <AT91_PMC_PCKRDY(3)>; 190 }; 191 }; 192 193 systemck { 194 compatible = "atmel,at91rm9200-clk-system"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 udpck: udpck { 199 #clock-cells = <0>; 200 reg = <2>; 201 clocks = <&usb>; 202 }; 203 204 uhpck: uhpck { 205 #clock-cells = <0>; 206 reg = <4>; 207 clocks = <&usb>; 208 }; 209 210 pck0: pck0 { 211 #clock-cells = <0>; 212 reg = <8>; 213 clocks = <&prog0>; 214 }; 215 216 pck1: pck1 { 217 #clock-cells = <0>; 218 reg = <9>; 219 clocks = <&prog1>; 220 }; 221 222 pck2: pck2 { 223 #clock-cells = <0>; 224 reg = <10>; 225 clocks = <&prog2>; 226 }; 227 228 pck3: pck3 { 229 #clock-cells = <0>; 230 reg = <11>; 231 clocks = <&prog3>; 232 }; 233 }; 234 235 periphck { 236 compatible = "atmel,at91rm9200-clk-peripheral"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 clocks = <&mck>; 240 241 pioA_clk: pioA_clk { 242 #clock-cells = <0>; 243 reg = <2>; 244 }; 245 246 pioB_clk: pioB_clk { 247 #clock-cells = <0>; 248 reg = <3>; 249 }; 250 251 pioC_clk: pioC_clk { 252 #clock-cells = <0>; 253 reg = <4>; 254 }; 255 256 pioD_clk: pioD_clk { 257 #clock-cells = <0>; 258 reg = <5>; 259 }; 260 261 usart0_clk: usart0_clk { 262 #clock-cells = <0>; 263 reg = <6>; 264 }; 265 266 usart1_clk: usart1_clk { 267 #clock-cells = <0>; 268 reg = <7>; 269 }; 270 271 usart2_clk: usart2_clk { 272 #clock-cells = <0>; 273 reg = <8>; 274 }; 275 276 usart3_clk: usart3_clk { 277 #clock-cells = <0>; 278 reg = <9>; 279 }; 280 281 mci0_clk: mci0_clk { 282 #clock-cells = <0>; 283 reg = <10>; 284 }; 285 286 udc_clk: udc_clk { 287 #clock-cells = <0>; 288 reg = <11>; 289 }; 290 291 twi0_clk: twi0_clk { 292 reg = <12>; 293 #clock-cells = <0>; 294 }; 295 296 spi0_clk: spi0_clk { 297 #clock-cells = <0>; 298 reg = <13>; 299 }; 300 301 ssc0_clk: ssc0_clk { 302 #clock-cells = <0>; 303 reg = <14>; 304 }; 305 306 ssc1_clk: ssc1_clk { 307 #clock-cells = <0>; 308 reg = <15>; 309 }; 310 311 ssc2_clk: ssc2_clk { 312 #clock-cells = <0>; 313 reg = <16>; 314 }; 315 316 tc0_clk: tc0_clk { 317 #clock-cells = <0>; 318 reg = <17>; 319 }; 320 321 tc1_clk: tc1_clk { 322 #clock-cells = <0>; 323 reg = <18>; 324 }; 325 326 tc2_clk: tc2_clk { 327 #clock-cells = <0>; 328 reg = <19>; 329 }; 330 331 tc3_clk: tc3_clk { 332 #clock-cells = <0>; 333 reg = <20>; 334 }; 335 336 tc4_clk: tc4_clk { 337 #clock-cells = <0>; 338 reg = <21>; 339 }; 340 341 tc5_clk: tc5_clk { 342 #clock-cells = <0>; 343 reg = <22>; 344 }; 345 346 ohci_clk: ohci_clk { 347 #clock-cells = <0>; 348 reg = <23>; 349 }; 350 351 macb0_clk: macb0_clk { 352 #clock-cells = <0>; 353 reg = <24>; 354 }; 355 }; 356 }; 357 358 st: timer@fffffd00 { 359 compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; 360 reg = <0xfffffd00 0x100>; 361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 362 clocks = <&slow_xtal>; 363 364 watchdog { 365 compatible = "atmel,at91rm9200-wdt"; 366 }; 367 }; 368 369 rtc: rtc@fffffe00 { 370 compatible = "atmel,at91rm9200-rtc"; 371 reg = <0xfffffe00 0x40>; 372 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 373 clocks = <&slow_xtal>; 374 status = "disabled"; 375 }; 376 377 tcb0: timer@fffa0000 { 378 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 reg = <0xfffa0000 0x100>; 382 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 383 18 IRQ_TYPE_LEVEL_HIGH 0 384 19 IRQ_TYPE_LEVEL_HIGH 0>; 385 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; 386 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 387 }; 388 389 tcb1: timer@fffa4000 { 390 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 reg = <0xfffa4000 0x100>; 394 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 395 21 IRQ_TYPE_LEVEL_HIGH 0 396 22 IRQ_TYPE_LEVEL_HIGH 0>; 397 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; 398 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 399 }; 400 401 i2c0: i2c@fffb8000 { 402 compatible = "atmel,at91rm9200-i2c"; 403 reg = <0xfffb8000 0x4000>; 404 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_twi>; 407 clocks = <&twi0_clk>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 mmc0: mmc@fffb4000 { 414 compatible = "atmel,hsmci"; 415 reg = <0xfffb4000 0x4000>; 416 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 417 clocks = <&mci0_clk>; 418 clock-names = "mci_clk"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 pinctrl-names = "default"; 422 status = "disabled"; 423 }; 424 425 ssc0: ssc@fffd0000 { 426 compatible = "atmel,at91rm9200-ssc"; 427 reg = <0xfffd0000 0x4000>; 428 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 431 clocks = <&ssc0_clk>; 432 clock-names = "pclk"; 433 status = "disabled"; 434 }; 435 436 ssc1: ssc@fffd4000 { 437 compatible = "atmel,at91rm9200-ssc"; 438 reg = <0xfffd4000 0x4000>; 439 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 442 clocks = <&ssc1_clk>; 443 clock-names = "pclk"; 444 status = "disabled"; 445 }; 446 447 ssc2: ssc@fffd8000 { 448 compatible = "atmel,at91rm9200-ssc"; 449 reg = <0xfffd8000 0x4000>; 450 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; 453 clocks = <&ssc2_clk>; 454 clock-names = "pclk"; 455 status = "disabled"; 456 }; 457 458 macb0: ethernet@fffbc000 { 459 compatible = "cdns,at91rm9200-emac", "cdns,emac"; 460 reg = <0xfffbc000 0x4000>; 461 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 462 phy-mode = "rmii"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_macb_rmii>; 465 clocks = <&macb0_clk>; 466 clock-names = "ether_clk"; 467 status = "disabled"; 468 }; 469 470 pinctrl@fffff400 { 471 #address-cells = <1>; 472 #size-cells = <1>; 473 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 474 ranges = <0xfffff400 0xfffff400 0x800>; 475 476 atmel,mux-mask = < 477 /* A B */ 478 0xffffffff 0xffffffff /* pioA */ 479 0xffffffff 0x083fffff /* pioB */ 480 0xffff3fff 0x00000000 /* pioC */ 481 0x03ff87ff 0x0fffff80 /* pioD */ 482 >; 483 484 /* shared pinctrl settings */ 485 dbgu { 486 pinctrl_dbgu: dbgu-0 { 487 atmel,pins = 488 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 489 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 490 }; 491 }; 492 493 uart0 { 494 pinctrl_uart0: uart0-0 { 495 atmel,pins = 496 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE 497 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 498 }; 499 500 pinctrl_uart0_cts: uart0_cts-0 { 501 atmel,pins = 502 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ 503 }; 504 505 pinctrl_uart0_rts: uart0_rts-0 { 506 atmel,pins = 507 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 508 }; 509 }; 510 511 uart1 { 512 pinctrl_uart1: uart1-0 { 513 atmel,pins = 514 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE 515 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 516 }; 517 518 pinctrl_uart1_rts: uart1_rts-0 { 519 atmel,pins = 520 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ 521 }; 522 523 pinctrl_uart1_cts: uart1_cts-0 { 524 atmel,pins = 525 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ 526 }; 527 528 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { 529 atmel,pins = 530 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ 531 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ 532 }; 533 534 pinctrl_uart1_dcd: uart1_dcd-0 { 535 atmel,pins = 536 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ 537 }; 538 539 pinctrl_uart1_ri: uart1_ri-0 { 540 atmel,pins = 541 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 542 }; 543 }; 544 545 uart2 { 546 pinctrl_uart2: uart2-0 { 547 atmel,pins = 548 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 549 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 550 }; 551 552 pinctrl_uart2_rts: uart2_rts-0 { 553 atmel,pins = 554 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 555 }; 556 557 pinctrl_uart2_cts: uart2_cts-0 { 558 atmel,pins = 559 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ 560 }; 561 }; 562 563 uart3 { 564 pinctrl_uart3: uart3-0 { 565 atmel,pins = 566 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE 567 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; 568 }; 569 570 pinctrl_uart3_rts: uart3_rts-0 { 571 atmel,pins = 572 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 573 }; 574 575 pinctrl_uart3_cts: uart3_cts-0 { 576 atmel,pins = 577 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 578 }; 579 }; 580 581 nand { 582 pinctrl_nand: nand-0 { 583 atmel,pins = 584 <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ 585 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ 586 }; 587 }; 588 589 macb { 590 pinctrl_macb_rmii: macb_rmii-0 { 591 atmel,pins = 592 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ 593 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ 594 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ 595 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ 596 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ 597 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 598 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 599 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 600 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 601 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ 602 }; 603 604 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 605 atmel,pins = 606 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ 607 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ 608 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ 609 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ 610 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ 611 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ 612 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ 613 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ 614 }; 615 }; 616 617 mmc0 { 618 pinctrl_mmc0_clk: mmc0_clk-0 { 619 atmel,pins = 620 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ 621 }; 622 623 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 624 atmel,pins = 625 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ 626 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ 627 }; 628 629 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 630 atmel,pins = 631 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ 632 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ 633 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ 634 }; 635 636 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 637 atmel,pins = 638 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ 639 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ 640 }; 641 642 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 643 atmel,pins = 644 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ 645 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ 646 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ 647 }; 648 }; 649 650 ssc0 { 651 pinctrl_ssc0_tx: ssc0_tx-0 { 652 atmel,pins = 653 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ 654 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ 655 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ 656 }; 657 658 pinctrl_ssc0_rx: ssc0_rx-0 { 659 atmel,pins = 660 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ 661 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ 662 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 663 }; 664 }; 665 666 ssc1 { 667 pinctrl_ssc1_tx: ssc1_tx-0 { 668 atmel,pins = 669 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ 670 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ 671 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ 672 }; 673 674 pinctrl_ssc1_rx: ssc1_rx-0 { 675 atmel,pins = 676 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ 677 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ 678 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ 679 }; 680 }; 681 682 ssc2 { 683 pinctrl_ssc2_tx: ssc2_tx-0 { 684 atmel,pins = 685 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ 686 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ 687 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ 688 }; 689 690 pinctrl_ssc2_rx: ssc2_rx-0 { 691 atmel,pins = 692 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ 693 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ 694 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ 695 }; 696 }; 697 698 twi { 699 pinctrl_twi: twi-0 { 700 atmel,pins = 701 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ 702 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ 703 }; 704 705 pinctrl_twi_gpio: twi_gpio-0 { 706 atmel,pins = 707 <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ 708 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ 709 }; 710 }; 711 712 tcb0 { 713 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 714 atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; 715 }; 716 717 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 718 atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 719 }; 720 721 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 722 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; 723 }; 724 725 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 726 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 727 }; 728 729 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 730 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 731 }; 732 733 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 734 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; 735 }; 736 737 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 738 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 739 }; 740 741 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 742 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; 743 }; 744 745 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 746 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 747 }; 748 }; 749 750 tcb1 { 751 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 752 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; 753 }; 754 755 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 756 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; 757 }; 758 759 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 760 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; 761 }; 762 763 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 764 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; 765 }; 766 767 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 768 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 769 }; 770 771 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 772 atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 773 }; 774 775 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 776 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 777 }; 778 779 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 780 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 781 }; 782 783 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 784 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; 785 }; 786 }; 787 788 spi0 { 789 pinctrl_spi0: spi0-0 { 790 atmel,pins = 791 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ 792 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ 793 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ 794 }; 795 }; 796 797 pioA: gpio@fffff400 { 798 compatible = "atmel,at91rm9200-gpio"; 799 reg = <0xfffff400 0x200>; 800 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 801 #gpio-cells = <2>; 802 gpio-controller; 803 interrupt-controller; 804 #interrupt-cells = <2>; 805 clocks = <&pioA_clk>; 806 }; 807 808 pioB: gpio@fffff600 { 809 compatible = "atmel,at91rm9200-gpio"; 810 reg = <0xfffff600 0x200>; 811 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 812 #gpio-cells = <2>; 813 gpio-controller; 814 interrupt-controller; 815 #interrupt-cells = <2>; 816 clocks = <&pioB_clk>; 817 }; 818 819 pioC: gpio@fffff800 { 820 compatible = "atmel,at91rm9200-gpio"; 821 reg = <0xfffff800 0x200>; 822 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 823 #gpio-cells = <2>; 824 gpio-controller; 825 interrupt-controller; 826 #interrupt-cells = <2>; 827 clocks = <&pioC_clk>; 828 }; 829 830 pioD: gpio@fffffa00 { 831 compatible = "atmel,at91rm9200-gpio"; 832 reg = <0xfffffa00 0x200>; 833 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 834 #gpio-cells = <2>; 835 gpio-controller; 836 interrupt-controller; 837 #interrupt-cells = <2>; 838 clocks = <&pioD_clk>; 839 }; 840 }; 841 842 dbgu: serial@fffff200 { 843 compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; 844 reg = <0xfffff200 0x200>; 845 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&pinctrl_dbgu>; 848 clocks = <&mck>; 849 clock-names = "usart"; 850 status = "disabled"; 851 }; 852 853 usart0: serial@fffc0000 { 854 compatible = "atmel,at91rm9200-usart"; 855 reg = <0xfffc0000 0x200>; 856 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 857 atmel,use-dma-rx; 858 atmel,use-dma-tx; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&pinctrl_uart0>; 861 clocks = <&usart0_clk>; 862 clock-names = "usart"; 863 status = "disabled"; 864 }; 865 866 usart1: serial@fffc4000 { 867 compatible = "atmel,at91rm9200-usart"; 868 reg = <0xfffc4000 0x200>; 869 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 870 atmel,use-dma-rx; 871 atmel,use-dma-tx; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&pinctrl_uart1>; 874 clocks = <&usart1_clk>; 875 clock-names = "usart"; 876 status = "disabled"; 877 }; 878 879 usart2: serial@fffc8000 { 880 compatible = "atmel,at91rm9200-usart"; 881 reg = <0xfffc8000 0x200>; 882 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 883 atmel,use-dma-rx; 884 atmel,use-dma-tx; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&pinctrl_uart2>; 887 clocks = <&usart2_clk>; 888 clock-names = "usart"; 889 status = "disabled"; 890 }; 891 892 usart3: serial@fffcc000 { 893 compatible = "atmel,at91rm9200-usart"; 894 reg = <0xfffcc000 0x200>; 895 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; 896 atmel,use-dma-rx; 897 atmel,use-dma-tx; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&pinctrl_uart3>; 900 clocks = <&usart3_clk>; 901 clock-names = "usart"; 902 status = "disabled"; 903 }; 904 905 usb1: gadget@fffb0000 { 906 compatible = "atmel,at91rm9200-udc"; 907 reg = <0xfffb0000 0x4000>; 908 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; 909 clocks = <&udc_clk>, <&udpck>; 910 clock-names = "pclk", "hclk"; 911 status = "disabled"; 912 }; 913 914 spi0: spi@fffe0000 { 915 #address-cells = <1>; 916 #size-cells = <0>; 917 compatible = "atmel,at91rm9200-spi"; 918 reg = <0xfffe0000 0x200>; 919 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&pinctrl_spi0>; 922 clocks = <&spi0_clk>; 923 clock-names = "spi_clk"; 924 status = "disabled"; 925 }; 926 }; 927 928 nand0: nand@40000000 { 929 compatible = "atmel,at91rm9200-nand"; 930 #address-cells = <1>; 931 #size-cells = <1>; 932 reg = <0x40000000 0x10000000>; 933 atmel,nand-addr-offset = <21>; 934 atmel,nand-cmd-offset = <22>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&pinctrl_nand>; 937 nand-ecc-mode = "soft"; 938 gpios = <&pioC 2 GPIO_ACTIVE_HIGH 939 0 940 &pioB 1 GPIO_ACTIVE_HIGH 941 >; 942 status = "disabled"; 943 }; 944 945 usb0: ohci@300000 { 946 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 947 reg = <0x00300000 0x100000>; 948 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 949 clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; 950 clock-names = "ohci_clk", "hclk", "uhpck"; 951 status = "disabled"; 952 }; 953 }; 954 955 i2c-gpio-0 { 956 compatible = "i2c-gpio"; 957 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ 958 &pioA 26 GPIO_ACTIVE_HIGH /* scl */ 959 >; 960 i2c-gpio,sda-open-drain; 961 i2c-gpio,scl-open-drain; 962 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 963 pinctrl-names = "default"; 964 pinctrl-0 = <&pinctrl_twi_gpio>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 status = "disabled"; 968 }; 969}; 970
