1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 39x family of SoCs. 4 * 5 * Copyright (C) 2015 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 */ 9 10#include "skeleton.dtsi" 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13 14#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 15 16/ { 17 model = "Marvell Armada 39x family SoC"; 18 compatible = "marvell,armada390"; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 serial3 = &uart3; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 enable-method = "marvell,armada-390-smp"; 33 34 cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a9"; 37 reg = <0>; 38 }; 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 reg = <1>; 43 }; 44 }; 45 46 pmu { 47 compatible = "arm,cortex-a9-pmu"; 48 interrupts-extended = <&mpic 3>; 49 }; 50 51 soc { 52 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", 53 "simple-bus"; 54 #address-cells = <2>; 55 #size-cells = <1>; 56 controller = <&mbusc>; 57 interrupt-parent = <&gic>; 58 pcie-mem-aperture = <0xe0000000 0x8000000>; 59 pcie-io-aperture = <0xe8000000 0x100000>; 60 61 bootrom { 62 compatible = "marvell,bootrom"; 63 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 64 }; 65 66 internal-regs { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 71 72 L2: cache-controller@8000 { 73 compatible = "arm,pl310-cache"; 74 reg = <0x8000 0x1000>; 75 cache-unified; 76 cache-level = <2>; 77 arm,double-linefill-incr = <0>; 78 arm,double-linefill-wrap = <0>; 79 arm,double-linefill = <0>; 80 prefetch-data = <1>; 81 }; 82 83 scu@c000 { 84 compatible = "arm,cortex-a9-scu"; 85 reg = <0xc000 0x100>; 86 }; 87 88 timer@c600 { 89 compatible = "arm,cortex-a9-twd-timer"; 90 reg = <0xc600 0x20>; 91 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 92 clocks = <&coreclk 2>; 93 }; 94 95 gic: interrupt-controller@d000 { 96 compatible = "arm,cortex-a9-gic"; 97 #interrupt-cells = <3>; 98 #size-cells = <0>; 99 interrupt-controller; 100 reg = <0xd000 0x1000>, 101 <0xc100 0x100>; 102 }; 103 104 i2c0: i2c@11000 { 105 compatible = "marvell,mv64xxx-i2c"; 106 reg = <0x11000 0x20>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 110 timeout-ms = <1000>; 111 clocks = <&coreclk 0>; 112 status = "disabled"; 113 }; 114 115 i2c1: i2c@11100 { 116 compatible = "marvell,mv64xxx-i2c"; 117 reg = <0x11100 0x20>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 121 timeout-ms = <1000>; 122 clocks = <&coreclk 0>; 123 status = "disabled"; 124 }; 125 126 i2c2: i2c@11200 { 127 compatible = "marvell,mv64xxx-i2c"; 128 reg = <0x11200 0x20>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 132 timeout-ms = <1000>; 133 clocks = <&coreclk 0>; 134 status = "disabled"; 135 }; 136 137 i2c3: i2c@11300 { 138 compatible = "marvell,mv64xxx-i2c"; 139 reg = <0x11300 0x20>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 143 timeout-ms = <1000>; 144 clocks = <&coreclk 0>; 145 status = "disabled"; 146 }; 147 148 uart0: serial@12000 { 149 compatible = "snps,dw-apb-uart"; 150 reg = <0x12000 0x100>; 151 reg-shift = <2>; 152 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 153 reg-io-width = <1>; 154 clocks = <&coreclk 0>; 155 status = "disabled"; 156 }; 157 158 uart1: serial@12100 { 159 compatible = "snps,dw-apb-uart"; 160 reg = <0x12100 0x100>; 161 reg-shift = <2>; 162 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 163 reg-io-width = <1>; 164 clocks = <&coreclk 0>; 165 status = "disabled"; 166 }; 167 168 uart2: serial@12200 { 169 compatible = "snps,dw-apb-uart"; 170 reg = <0x12200 0x100>; 171 reg-shift = <2>; 172 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 173 reg-io-width = <1>; 174 clocks = <&coreclk 0>; 175 status = "disabled"; 176 }; 177 178 uart3: serial@12300 { 179 compatible = "snps,dw-apb-uart"; 180 reg = <0x12300 0x100>; 181 reg-shift = <2>; 182 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 183 reg-io-width = <1>; 184 clocks = <&coreclk 0>; 185 status = "disabled"; 186 }; 187 188 pinctrl@18000 { 189 i2c0_pins: i2c0-pins { 190 marvell,pins = "mpp2", "mpp3"; 191 marvell,function = "i2c0"; 192 }; 193 194 uart0_pins: uart0-pins { 195 marvell,pins = "mpp0", "mpp1"; 196 marvell,function = "ua0"; 197 }; 198 199 uart1_pins: uart1-pins { 200 marvell,pins = "mpp19", "mpp20"; 201 marvell,function = "ua1"; 202 }; 203 204 spi1_pins: spi1-pins { 205 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; 206 marvell,function = "spi1"; 207 }; 208 209 nand_pins: nand-pins { 210 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", 211 "mpp38", "mpp28", "mpp40", "mpp42", 212 "mpp35", "mpp36", "mpp25", "mpp30", 213 "mpp32"; 214 marvell,function = "dev"; 215 }; 216 }; 217 218 gpio0: gpio@18100 { 219 compatible = "marvell,orion-gpio"; 220 reg = <0x18100 0x40>; 221 ngpios = <32>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 interrupt-controller; 225 #interrupt-cells = <2>; 226 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 230 }; 231 232 gpio1: gpio@18140 { 233 compatible = "marvell,orion-gpio"; 234 reg = <0x18140 0x40>; 235 ngpios = <28>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 244 }; 245 246 system-controller@18200 { 247 compatible = "marvell,armada-390-system-controller", 248 "marvell,armada-370-xp-system-controller"; 249 reg = <0x18200 0x100>; 250 }; 251 252 gateclk: clock-gating-control@18220 { 253 compatible = "marvell,armada-390-gating-clock"; 254 reg = <0x18220 0x4>; 255 clocks = <&coreclk 0>; 256 #clock-cells = <1>; 257 }; 258 259 coreclk: mvebu-sar@18600 { 260 compatible = "marvell,armada-390-core-clock"; 261 reg = <0x18600 0x04>; 262 #clock-cells = <1>; 263 }; 264 265 mbusc: mbus-controller@20000 { 266 compatible = "marvell,mbus-controller"; 267 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; 268 }; 269 270 mpic: interrupt-controller@20a00 { 271 compatible = "marvell,mpic"; 272 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 273 #interrupt-cells = <1>; 274 #size-cells = <1>; 275 interrupt-controller; 276 msi-controller; 277 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 278 }; 279 280 timer@20300 { 281 compatible = "marvell,armada-380-timer", 282 "marvell,armada-xp-timer"; 283 reg = <0x20300 0x30>, <0x21040 0x30>; 284 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 285 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 286 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 287 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 288 <&mpic 5>, 289 <&mpic 6>; 290 clocks = <&coreclk 2>, <&coreclk 5>; 291 clock-names = "nbclk", "fixed"; 292 }; 293 294 watchdog@20300 { 295 compatible = "marvell,armada-380-wdt"; 296 reg = <0x20300 0x34>, <0x20704 0x4>, 297 <0x18260 0x4>; 298 clocks = <&coreclk 2>, <&refclk>; 299 clock-names = "nbclk", "fixed"; 300 }; 301 302 cpurst@20800 { 303 compatible = "marvell,armada-370-cpu-reset"; 304 reg = <0x20800 0x10>; 305 }; 306 307 mpcore-soc-ctrl@20d20 { 308 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 309 reg = <0x20d20 0x6c>; 310 }; 311 312 coherency-fabric@21010 { 313 compatible = "marvell,armada-380-coherency-fabric"; 314 reg = <0x21010 0x1c>; 315 }; 316 317 pmsu@22000 { 318 compatible = "marvell,armada-390-pmsu", 319 "marvell,armada-380-pmsu"; 320 reg = <0x22000 0x1000>; 321 }; 322 323 xor@60800 { 324 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 325 reg = <0x60800 0x100 326 0x60a00 0x100>; 327 clocks = <&gateclk 22>; 328 status = "okay"; 329 330 xor00 { 331 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 332 dmacap,memcpy; 333 dmacap,xor; 334 }; 335 xor01 { 336 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 337 dmacap,memcpy; 338 dmacap,xor; 339 dmacap,memset; 340 }; 341 }; 342 343 xor@60900 { 344 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 345 reg = <0x60900 0x100 346 0x60b00 0x100>; 347 clocks = <&gateclk 28>; 348 status = "okay"; 349 350 xor10 { 351 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 352 dmacap,memcpy; 353 dmacap,xor; 354 }; 355 xor11 { 356 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 357 dmacap,memcpy; 358 dmacap,xor; 359 dmacap,memset; 360 }; 361 }; 362 363 rtc@a3800 { 364 compatible = "marvell,armada-380-rtc"; 365 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 366 reg-names = "rtc", "rtc-soc"; 367 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 368 }; 369 370 nand_controller: nand-controller@d0000 { 371 compatible = "marvell,armada370-nand-controller"; 372 reg = <0xd0000 0x54>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&coredivclk 0>; 377 status = "disabled"; 378 }; 379 380 sdhci@d8000 { 381 compatible = "marvell,armada-380-sdhci"; 382 reg-names = "sdhci", "mbus", "conf-sdio3"; 383 reg = <0xd8000 0x1000>, 384 <0xdc000 0x100>, 385 <0x18454 0x4>; 386 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&gateclk 17>; 388 mrvl,clk-delay-cycles = <0x1F>; 389 status = "disabled"; 390 }; 391 392 coredivclk: clock@e4250 { 393 compatible = "marvell,armada-390-corediv-clock", 394 "marvell,armada-380-corediv-clock"; 395 reg = <0xe4250 0xc>; 396 #clock-cells = <1>; 397 clocks = <&mainpll>; 398 clock-output-names = "nand"; 399 }; 400 401 thermal@e8078 { 402 compatible = "marvell,armada380-thermal"; 403 reg = <0xe4078 0x4>, <0xe4074 0x4>; 404 status = "okay"; 405 }; 406 }; 407 408 pcie { 409 compatible = "marvell,armada-370-pcie"; 410 status = "disabled"; 411 device_type = "pci"; 412 413 #address-cells = <3>; 414 #size-cells = <2>; 415 416 msi-parent = <&mpic>; 417 bus-range = <0x00 0xff>; 418 419 ranges = 420 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 421 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 422 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 423 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 424 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 425 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 426 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 427 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 428 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 429 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 430 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 431 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 432 433 /* 434 * This port can be either x4 or x1. When 435 * configured in x4 by the bootloader, then 436 * pcie@4,0 is not available. 437 */ 438 pcie@1,0 { 439 device_type = "pci"; 440 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 441 reg = <0x0800 0 0 0 0>; 442 #address-cells = <3>; 443 #size-cells = <2>; 444 #interrupt-cells = <1>; 445 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 446 0x81000000 0 0 0x81000000 0x1 0 1 0>; 447 bus-range = <0x00 0xff>; 448 interrupt-map-mask = <0 0 0 0>; 449 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 450 marvell,pcie-port = <0>; 451 marvell,pcie-lane = <0>; 452 clocks = <&gateclk 8>; 453 status = "disabled"; 454 }; 455 456 /* x1 port */ 457 pcie@2,0 { 458 device_type = "pci"; 459 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 460 reg = <0x1000 0 0 0 0>; 461 #address-cells = <3>; 462 #size-cells = <2>; 463 #interrupt-cells = <1>; 464 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 465 0x81000000 0 0 0x81000000 0x2 0 1 0>; 466 bus-range = <0x00 0xff>; 467 interrupt-map-mask = <0 0 0 0>; 468 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 469 marvell,pcie-port = <1>; 470 marvell,pcie-lane = <0>; 471 clocks = <&gateclk 5>; 472 status = "disabled"; 473 }; 474 475 /* x1 port */ 476 pcie@3,0 { 477 device_type = "pci"; 478 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 479 reg = <0x1800 0 0 0 0>; 480 #address-cells = <3>; 481 #size-cells = <2>; 482 #interrupt-cells = <1>; 483 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 484 0x81000000 0 0 0x81000000 0x3 0 1 0>; 485 bus-range = <0x00 0xff>; 486 interrupt-map-mask = <0 0 0 0>; 487 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 488 marvell,pcie-port = <2>; 489 marvell,pcie-lane = <0>; 490 clocks = <&gateclk 6>; 491 status = "disabled"; 492 }; 493 494 /* 495 * x1 port only available when pcie@1,0 is 496 * configured as a x1 port 497 */ 498 pcie@4,0 { 499 device_type = "pci"; 500 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 501 reg = <0x2000 0 0 0 0>; 502 #address-cells = <3>; 503 #size-cells = <2>; 504 #interrupt-cells = <1>; 505 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 506 0x81000000 0 0 0x81000000 0x4 0 1 0>; 507 bus-range = <0x00 0xff>; 508 interrupt-map-mask = <0 0 0 0>; 509 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 510 marvell,pcie-port = <3>; 511 marvell,pcie-lane = <0>; 512 clocks = <&gateclk 7>; 513 status = "disabled"; 514 }; 515 }; 516 517 spi0: spi@10600 { 518 compatible = "marvell,armada-390-spi", 519 "marvell,orion-spi"; 520 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 cell-index = <0>; 524 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&coreclk 0>; 526 status = "disabled"; 527 }; 528 529 spi1: spi@10680 { 530 compatible = "marvell,armada-390-spi", 531 "marvell,orion-spi"; 532 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 cell-index = <1>; 536 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&coreclk 0>; 538 status = "disabled"; 539 }; 540 }; 541 542 clocks { 543 /* 1 GHz fixed main PLL */ 544 mainpll: mainpll { 545 compatible = "fixed-clock"; 546 #clock-cells = <0>; 547 clock-frequency = <1000000000>; 548 }; 549 550 /* 25 MHz reference crystal */ 551 refclk: oscillator { 552 compatible = "fixed-clock"; 553 #clock-cells = <0>; 554 clock-frequency = <25000000>; 555 }; 556 }; 557}; 558
