1MMUv3 initialization sequence. 2 3The code in the initialize_mmu macro sets up MMUv3 memory mapping 4identically to MMUv2 fixed memory mapping. Depending on 5CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is 6located in addresses it was linked for (symbol undefined), or not 7(symbol defined), so it needs to be position-independent. 8 9The code has the following assumptions: 10 This code fragment is run only on an MMU v3. 11 TLBs are in their reset state. 12 ITLBCFG and DTLBCFG are zero (reset state). 13 RASID is 0x04030201 (reset state). 14 PS.RING is zero (reset state). 15 LITBASE is zero (reset state, PC-relative literals); required to be PIC. 16 17TLB setup proceeds along the following steps. 18 19 Legend: 20 VA = virtual address (two upper nibbles of it); 21 PA = physical address (two upper nibbles of it); 22 pc = physical range that contains this code; 23 24After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff 25or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below 260x40000000 or above. That address corresponds to next instruction to execute 27in this code. After step 4, we jump to intended (linked) address of this code. 28The scheme below assumes that the kernel is loaded below 0x40000000. 29 30 Step0 Step1 Step2 Step3 Step4 Step5 31 ===== ===== ===== ===== ===== ===== 32 VA PA PA PA PA VA PA PA 33 ------ -- -- -- -- ------ -- -- 34 E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0 35 C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0 36 A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00 37 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00 38 60..7F -> 60 -> 60 -> 60 39 40..5F -> 40 -> pc -> pc 40..5F -> pc 40 20..3F -> 20 -> 20 -> 20 41 00..1F -> 00 -> 00 -> 00 42 43The default location of IO peripherals is above 0xf0000000. This may be changed 44using a "ranges" property in a device tree simple-bus node. See the Devicetree 45Specification, section 4.5 for details on the syntax and semantics of 46simple-bus nodes. The following limitations apply: 47 481. Only top level simple-bus nodes are considered 49 502. Only one (first) simple-bus node is considered 51 523. Empty "ranges" properties are not supported 53 544. Only the first triplet in the "ranges" property is considered 55 565. The parent-bus-address value is rounded down to the nearest 256MB boundary 57 586. The IO area covers the entire 256MB segment of parent-bus-address; the 59 "ranges" triplet length field is ignored 60 61 62MMUv3 address space layouts. 63============================ 64 65Default MMUv2-compatible layout. 66 67 Symbol VADDR Size 68+------------------+ 69| Userspace | 0x00000000 TASK_SIZE 70+------------------+ 0x40000000 71+------------------+ 72| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE 73+------------------+ 74| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE 75+------------------+ 0x8e400000 76+------------------+ 77| VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB 78+------------------+ VMALLOC_END 79| Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE 80| remap area 1 | 81+------------------+ 82| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE 83| remap area 2 | 84+------------------+ 85+------------------+ 86| KMAP area | PKMAP_BASE PTRS_PER_PTE * 87| | DCACHE_N_COLORS * 88| | PAGE_SIZE 89| | (4MB * DCACHE_N_COLORS) 90+------------------+ 91| Atomic KMAP area | FIXADDR_START KM_TYPE_NR * 92| | NR_CPUS * 93| | DCACHE_N_COLORS * 94| | PAGE_SIZE 95+------------------+ FIXADDR_TOP 0xcffff000 96+------------------+ 97| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB 98+------------------+ 99| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB 100+------------------+ 101| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB 102+------------------+ 103| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB 104+------------------+ 105 106 107256MB cached + 256MB uncached layout. 108 109 Symbol VADDR Size 110+------------------+ 111| Userspace | 0x00000000 TASK_SIZE 112+------------------+ 0x40000000 113+------------------+ 114| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE 115+------------------+ 116| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE 117+------------------+ 0x8e400000 118+------------------+ 119| VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB 120+------------------+ VMALLOC_END 121| Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE 122| remap area 1 | 123+------------------+ 124| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE 125| remap area 2 | 126+------------------+ 127+------------------+ 128| KMAP area | PKMAP_BASE PTRS_PER_PTE * 129| | DCACHE_N_COLORS * 130| | PAGE_SIZE 131| | (4MB * DCACHE_N_COLORS) 132+------------------+ 133| Atomic KMAP area | FIXADDR_START KM_TYPE_NR * 134| | NR_CPUS * 135| | DCACHE_N_COLORS * 136| | PAGE_SIZE 137+------------------+ FIXADDR_TOP 0xaffff000 138+------------------+ 139| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB 140+------------------+ 141| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB 142+------------------+ 143+------------------+ 144| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB 145+------------------+ 146| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB 147+------------------+ 148 149 150512MB cached + 512MB uncached layout. 151 152 Symbol VADDR Size 153+------------------+ 154| Userspace | 0x00000000 TASK_SIZE 155+------------------+ 0x40000000 156+------------------+ 157| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE 158+------------------+ 159| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE 160+------------------+ 0x8e400000 161+------------------+ 162| VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB 163+------------------+ VMALLOC_END 164| Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE 165| remap area 1 | 166+------------------+ 167| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE 168| remap area 2 | 169+------------------+ 170+------------------+ 171| KMAP area | PKMAP_BASE PTRS_PER_PTE * 172| | DCACHE_N_COLORS * 173| | PAGE_SIZE 174| | (4MB * DCACHE_N_COLORS) 175+------------------+ 176| Atomic KMAP area | FIXADDR_START KM_TYPE_NR * 177| | NR_CPUS * 178| | DCACHE_N_COLORS * 179| | PAGE_SIZE 180+------------------+ FIXADDR_TOP 0x9ffff000 181+------------------+ 182| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB 183+------------------+ 184| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB 185+------------------+ 186| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB 187+------------------+ 188| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB 189+------------------+ 190
