1OpenRISC Linux
2==============
3
4This is a port of Linux to the OpenRISC class of microprocessors; the initial
5target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
6
7For information about OpenRISC processors and ongoing development:
8
9	website		http://openrisc.io
10	email		openrisc@lists.librecores.org
11
12---------------------------------------------------------------------
13
14Build instructions for OpenRISC toolchain and Linux
15===================================================
16
17In order to build and run Linux for OpenRISC, you'll need at least a basic
18toolchain and, perhaps, the architectural simulator.  Steps to get these bits
19in place are outlined here.
20
211) Toolchain
22
23Toolchain binaries can be obtained from openrisc.io or our github releases page.
24Instructions for building the different toolchains can be found on openrisc.io
25or Stafford's toolchain build and release scripts.
26
27	binaries	https://github.com/openrisc/or1k-gcc/releases
28	toolchains	https://openrisc.io/software
29	building	https://github.com/stffrdhrn/or1k-toolchain-build
30
312) Building
32
33Build the Linux kernel as usual
34
35	make ARCH=openrisc defconfig
36	make ARCH=openrisc
37
383) Running on FPGA (optional)
39
40The OpenRISC community typically uses FuseSoC to manage building and programming
41an SoC into an FPGA.  The below is an example of programming a De0 Nano
42development board with the OpenRISC SoC.  During the build FPGA RTL is code
43downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
44tools.  Binaries are loaded onto the board with openocd.
45
46	git clone https://github.com/olofk/fusesoc
47	cd fusesoc
48	sudo pip install -e .
49
50	fusesoc init
51	fusesoc build de0_nano
52	fusesoc pgm de0_nano
53
54	openocd -f interface/altera-usb-blaster.cfg \
55		-f board/or1k_generic.cfg
56
57	telnet localhost 4444
58	> init
59	> halt; load_image vmlinux ; reset
60
614) Running on a Simulator (optional)
62
63QEMU is a processor emulator which we recommend for simulating the OpenRISC
64platform.  Please follow the OpenRISC instructions on the QEMU website to get
65Linux running on QEMU.  You can build QEMU yourself, but your Linux distribution
66likely provides binary packages to support OpenRISC.
67
68	qemu openrisc	https://wiki.qemu.org/Documentation/Platforms/OpenRISC
69
70---------------------------------------------------------------------
71
72Terminology
73===========
74
75In the code, the following particles are used on symbols to limit the scope
76to more or less specific processor implementations:
77
78openrisc: the OpenRISC class of processors
79or1k:     the OpenRISC 1000 family of processors
80or1200:   the OpenRISC 1200 processor
81
82---------------------------------------------------------------------
83
84History
85========
86
8718. 11. 2003	Matjaz Breskvar (phoenix@bsemi.com)
88	initial port of linux to OpenRISC/or32 architecture.
89        all the core stuff is implemented and seams usable.
90
9108. 12. 2003	Matjaz Breskvar (phoenix@bsemi.com)
92	complete change of TLB miss handling.
93	rewrite of exceptions handling.
94	fully functional sash-3.6 in default initrd.
95	a much improved version with changes all around.
96
9710. 04. 2004	Matjaz Breskvar (phoenix@bsemi.com)
98	alot of bugfixes all over.
99	ethernet support, functional http and telnet servers.
100	running many standard linux apps.
101
10226. 06. 2004	Matjaz Breskvar (phoenix@bsemi.com)
103	port to 2.6.x
104
10530. 11. 2004	Matjaz Breskvar (phoenix@bsemi.com)
106	lots of bugfixes and enhancments.
107	added opencores framebuffer driver.
108
10909. 10. 2010    Jonas Bonn (jonas@southpole.se)
110	major rewrite to bring up to par with upstream Linux 2.6.36
111